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/*
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* APIC support
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "hw.h" |
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#include "apic.h" |
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#include "ioapic.h" |
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#include "qemu-timer.h" |
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#include "host-utils.h" |
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#include "sysbus.h" |
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#include "trace.h" |
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/* APIC Local Vector Table */
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#define APIC_LVT_TIMER 0 |
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#define APIC_LVT_THERMAL 1 |
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#define APIC_LVT_PERFORM 2 |
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#define APIC_LVT_LINT0 3 |
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#define APIC_LVT_LINT1 4 |
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#define APIC_LVT_ERROR 5 |
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#define APIC_LVT_NB 6 |
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|
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/* APIC delivery modes */
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#define APIC_DM_FIXED 0 |
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#define APIC_DM_LOWPRI 1 |
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#define APIC_DM_SMI 2 |
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#define APIC_DM_NMI 4 |
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#define APIC_DM_INIT 5 |
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#define APIC_DM_SIPI 6 |
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#define APIC_DM_EXTINT 7 |
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|
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/* APIC destination mode */
|
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#define APIC_DESTMODE_FLAT 0xf |
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#define APIC_DESTMODE_CLUSTER 1 |
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|
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#define APIC_TRIGGER_EDGE 0 |
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#define APIC_TRIGGER_LEVEL 1 |
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|
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#define APIC_LVT_TIMER_PERIODIC (1<<17) |
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#define APIC_LVT_MASKED (1<<16) |
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#define APIC_LVT_LEVEL_TRIGGER (1<<15) |
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#define APIC_LVT_REMOTE_IRR (1<<14) |
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#define APIC_INPUT_POLARITY (1<<13) |
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#define APIC_SEND_PENDING (1<<12) |
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|
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#define ESR_ILLEGAL_ADDRESS (1 << 7) |
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|
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#define APIC_SV_DIRECTED_IO (1<<12) |
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#define APIC_SV_ENABLE (1<<8) |
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|
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#define MAX_APICS 255 |
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#define MAX_APIC_WORDS 8 |
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|
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/* Intel APIC constants: from include/asm/msidef.h */
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#define MSI_DATA_VECTOR_SHIFT 0 |
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#define MSI_DATA_VECTOR_MASK 0x000000ff |
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#define MSI_DATA_DELIVERY_MODE_SHIFT 8 |
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#define MSI_DATA_TRIGGER_SHIFT 15 |
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#define MSI_DATA_LEVEL_SHIFT 14 |
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#define MSI_ADDR_DEST_MODE_SHIFT 2 |
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#define MSI_ADDR_DEST_ID_SHIFT 12 |
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#define MSI_ADDR_DEST_ID_MASK 0x00ffff0 |
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|
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#define MSI_ADDR_SIZE 0x100000 |
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|
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typedef struct APICState APICState; |
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struct APICState {
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SysBusDevice busdev; |
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void *cpu_env;
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uint32_t apicbase; |
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uint8_t id; |
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uint8_t arb_id; |
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uint8_t tpr; |
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uint32_t spurious_vec; |
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uint8_t log_dest; |
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uint8_t dest_mode; |
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uint32_t isr[8]; /* in service register */ |
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uint32_t tmr[8]; /* trigger mode register */ |
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uint32_t irr[8]; /* interrupt request register */ |
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uint32_t lvt[APIC_LVT_NB]; |
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uint32_t esr; /* error register */
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uint32_t icr[2];
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|
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uint32_t divide_conf; |
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int count_shift;
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uint32_t initial_count; |
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int64_t initial_count_load_time, next_time; |
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uint32_t idx; |
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QEMUTimer *timer; |
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int sipi_vector;
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int wait_for_sipi;
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}; |
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|
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static APICState *local_apics[MAX_APICS + 1]; |
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static int apic_irq_delivered; |
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static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); |
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static void apic_update_irq(APICState *s); |
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static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
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uint8_t dest, uint8_t dest_mode); |
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|
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/* Find first bit starting from msb */
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static int fls_bit(uint32_t value) |
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{
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return 31 - clz32(value); |
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} |
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/* Find first bit starting from lsb */
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static int ffs_bit(uint32_t value) |
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{
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return ctz32(value);
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} |
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static inline void set_bit(uint32_t *tab, int index) |
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f); |
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tab[i] |= mask; |
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} |
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static inline void reset_bit(uint32_t *tab, int index) |
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f); |
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tab[i] &= ~mask; |
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} |
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static inline int get_bit(uint32_t *tab, int index) |
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f); |
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return !!(tab[i] & mask);
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} |
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static void apic_local_deliver(APICState *s, int vector) |
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{
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uint32_t lvt = s->lvt[vector]; |
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int trigger_mode;
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trace_apic_local_deliver(vector, (lvt >> 8) & 7); |
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if (lvt & APIC_LVT_MASKED)
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return;
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switch ((lvt >> 8) & 7) { |
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case APIC_DM_SMI:
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI); |
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break;
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case APIC_DM_NMI:
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI); |
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break;
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|
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case APIC_DM_EXTINT:
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
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break;
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case APIC_DM_FIXED:
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trigger_mode = APIC_TRIGGER_EDGE; |
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if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
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(lvt & APIC_LVT_LEVEL_TRIGGER)) |
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trigger_mode = APIC_TRIGGER_LEVEL; |
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apic_set_irq(s, lvt & 0xff, trigger_mode);
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} |
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} |
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void apic_deliver_pic_intr(DeviceState *d, int level) |
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{
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
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if (level) {
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apic_local_deliver(s, APIC_LVT_LINT0); |
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} else {
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uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
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switch ((lvt >> 8) & 7) { |
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case APIC_DM_FIXED:
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if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
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break;
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reset_bit(s->irr, lvt & 0xff);
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/* fall through */
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case APIC_DM_EXTINT:
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cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
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break;
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} |
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} |
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} |
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|
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#define foreach_apic(apic, deliver_bitmask, code) \
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{\
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int __i, __j, __mask;\
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for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ |
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__mask = deliver_bitmask[__i];\ |
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if (__mask) {\
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for(__j = 0; __j < 32; __j++) {\ |
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if (__mask & (1 << __j)) {\ |
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apic = local_apics[__i * 32 + __j];\
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if (apic) {\
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code;\ |
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}\ |
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}\ |
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}\ |
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}\ |
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}\ |
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} |
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static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
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uint8_t delivery_mode, |
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uint8_t vector_num, uint8_t polarity, |
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uint8_t trigger_mode) |
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{
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APICState *apic_iter; |
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switch (delivery_mode) {
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case APIC_DM_LOWPRI:
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/* XXX: search for focus processor, arbitration */
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{
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int i, d;
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d = -1;
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for(i = 0; i < MAX_APIC_WORDS; i++) { |
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if (deliver_bitmask[i]) {
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d = i * 32 + ffs_bit(deliver_bitmask[i]);
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break;
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} |
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} |
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if (d >= 0) { |
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apic_iter = local_apics[d]; |
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if (apic_iter) {
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apic_set_irq(apic_iter, vector_num, trigger_mode); |
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} |
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} |
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} |
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return;
|
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|
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case APIC_DM_FIXED:
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break;
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|
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case APIC_DM_SMI:
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foreach_apic(apic_iter, deliver_bitmask, |
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); |
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return;
|
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|
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case APIC_DM_NMI:
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foreach_apic(apic_iter, deliver_bitmask, |
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); |
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return;
|
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|
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case APIC_DM_INIT:
|
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/* normal INIT IPI sent to processors */
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foreach_apic(apic_iter, deliver_bitmask, |
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ); |
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return;
|
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|
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case APIC_DM_EXTINT:
|
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/* handled in I/O APIC code */
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break;
|
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|
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default:
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return;
|
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} |
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|
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foreach_apic(apic_iter, deliver_bitmask, |
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apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
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} |
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|
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void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
|
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uint8_t delivery_mode, uint8_t vector_num, |
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uint8_t polarity, uint8_t trigger_mode) |
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{
|
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uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
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|
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trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, |
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polarity, trigger_mode); |
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|
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apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
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apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
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trigger_mode); |
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} |
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|
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void cpu_set_apic_base(DeviceState *d, uint64_t val)
|
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{
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
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|
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trace_cpu_set_apic_base(val); |
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|
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if (!s)
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return;
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s->apicbase = (val & 0xfffff000) |
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(s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
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/* if disabled, cannot be enabled again */
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if (!(val & MSR_IA32_APICBASE_ENABLE)) {
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s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; |
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cpu_clear_apic_feature(s->cpu_env); |
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s->spurious_vec &= ~APIC_SV_ENABLE; |
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} |
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} |
| 314 |
|
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uint64_t cpu_get_apic_base(DeviceState *d) |
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{
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
| 318 |
|
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trace_cpu_get_apic_base(s ? (uint64_t)s->apicbase: 0);
|
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|
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return s ? s->apicbase : 0; |
| 322 |
} |
| 323 |
|
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void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
|
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{
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
| 327 |
|
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if (!s)
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return;
|
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s->tpr = (val & 0x0f) << 4; |
| 331 |
apic_update_irq(s); |
| 332 |
} |
| 333 |
|
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uint8_t cpu_get_apic_tpr(DeviceState *d) |
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{
|
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
| 337 |
|
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return s ? s->tpr >> 4 : 0; |
| 339 |
} |
| 340 |
|
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/* return -1 if no bit is set */
|
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static int get_highest_priority_int(uint32_t *tab) |
| 343 |
{
|
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int i;
|
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for(i = 7; i >= 0; i--) { |
| 346 |
if (tab[i] != 0) { |
| 347 |
return i * 32 + fls_bit(tab[i]); |
| 348 |
} |
| 349 |
} |
| 350 |
return -1; |
| 351 |
} |
| 352 |
|
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static int apic_get_ppr(APICState *s) |
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{
|
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int tpr, isrv, ppr;
|
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|
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tpr = (s->tpr >> 4);
|
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isrv = get_highest_priority_int(s->isr); |
| 359 |
if (isrv < 0) |
| 360 |
isrv = 0;
|
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isrv >>= 4;
|
| 362 |
if (tpr >= isrv)
|
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ppr = s->tpr; |
| 364 |
else
|
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ppr = isrv << 4;
|
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return ppr;
|
| 367 |
} |
| 368 |
|
| 369 |
static int apic_get_arb_pri(APICState *s) |
| 370 |
{
|
| 371 |
/* XXX: arbitration */
|
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return 0; |
| 373 |
} |
| 374 |
|
| 375 |
|
| 376 |
/*
|
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* <0 - low prio interrupt,
|
| 378 |
* 0 - no interrupt,
|
| 379 |
* >0 - interrupt number
|
| 380 |
*/
|
| 381 |
static int apic_irq_pending(APICState *s) |
| 382 |
{
|
| 383 |
int irrv, ppr;
|
| 384 |
irrv = get_highest_priority_int(s->irr); |
| 385 |
if (irrv < 0) { |
| 386 |
return 0; |
| 387 |
} |
| 388 |
ppr = apic_get_ppr(s); |
| 389 |
if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) { |
| 390 |
return -1; |
| 391 |
} |
| 392 |
|
| 393 |
return irrv;
|
| 394 |
} |
| 395 |
|
| 396 |
/* signal the CPU if an irq is pending */
|
| 397 |
static void apic_update_irq(APICState *s) |
| 398 |
{
|
| 399 |
if (!(s->spurious_vec & APIC_SV_ENABLE)) {
|
| 400 |
return;
|
| 401 |
} |
| 402 |
if (apic_irq_pending(s) > 0) { |
| 403 |
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
| 404 |
} |
| 405 |
} |
| 406 |
|
| 407 |
void apic_reset_irq_delivered(void) |
| 408 |
{
|
| 409 |
trace_apic_reset_irq_delivered(apic_irq_delivered); |
| 410 |
|
| 411 |
apic_irq_delivered = 0;
|
| 412 |
} |
| 413 |
|
| 414 |
int apic_get_irq_delivered(void) |
| 415 |
{
|
| 416 |
trace_apic_get_irq_delivered(apic_irq_delivered); |
| 417 |
|
| 418 |
return apic_irq_delivered;
|
| 419 |
} |
| 420 |
|
| 421 |
static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) |
| 422 |
{
|
| 423 |
apic_irq_delivered += !get_bit(s->irr, vector_num); |
| 424 |
|
| 425 |
trace_apic_set_irq(apic_irq_delivered); |
| 426 |
|
| 427 |
set_bit(s->irr, vector_num); |
| 428 |
if (trigger_mode)
|
| 429 |
set_bit(s->tmr, vector_num); |
| 430 |
else
|
| 431 |
reset_bit(s->tmr, vector_num); |
| 432 |
apic_update_irq(s); |
| 433 |
} |
| 434 |
|
| 435 |
static void apic_eoi(APICState *s) |
| 436 |
{
|
| 437 |
int isrv;
|
| 438 |
isrv = get_highest_priority_int(s->isr); |
| 439 |
if (isrv < 0) |
| 440 |
return;
|
| 441 |
reset_bit(s->isr, isrv); |
| 442 |
if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, isrv)) {
|
| 443 |
ioapic_eoi_broadcast(isrv); |
| 444 |
} |
| 445 |
apic_update_irq(s); |
| 446 |
} |
| 447 |
|
| 448 |
static int apic_find_dest(uint8_t dest) |
| 449 |
{
|
| 450 |
APICState *apic = local_apics[dest]; |
| 451 |
int i;
|
| 452 |
|
| 453 |
if (apic && apic->id == dest)
|
| 454 |
return dest; /* shortcut in case apic->id == apic->idx */ |
| 455 |
|
| 456 |
for (i = 0; i < MAX_APICS; i++) { |
| 457 |
apic = local_apics[i]; |
| 458 |
if (apic && apic->id == dest)
|
| 459 |
return i;
|
| 460 |
if (!apic)
|
| 461 |
break;
|
| 462 |
} |
| 463 |
|
| 464 |
return -1; |
| 465 |
} |
| 466 |
|
| 467 |
static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
| 468 |
uint8_t dest, uint8_t dest_mode) |
| 469 |
{
|
| 470 |
APICState *apic_iter; |
| 471 |
int i;
|
| 472 |
|
| 473 |
if (dest_mode == 0) { |
| 474 |
if (dest == 0xff) { |
| 475 |
memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); |
| 476 |
} else {
|
| 477 |
int idx = apic_find_dest(dest);
|
| 478 |
memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
| 479 |
if (idx >= 0) |
| 480 |
set_bit(deliver_bitmask, idx); |
| 481 |
} |
| 482 |
} else {
|
| 483 |
/* XXX: cluster mode */
|
| 484 |
memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
| 485 |
for(i = 0; i < MAX_APICS; i++) { |
| 486 |
apic_iter = local_apics[i]; |
| 487 |
if (apic_iter) {
|
| 488 |
if (apic_iter->dest_mode == 0xf) { |
| 489 |
if (dest & apic_iter->log_dest)
|
| 490 |
set_bit(deliver_bitmask, i); |
| 491 |
} else if (apic_iter->dest_mode == 0x0) { |
| 492 |
if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && |
| 493 |
(dest & apic_iter->log_dest & 0x0f)) {
|
| 494 |
set_bit(deliver_bitmask, i); |
| 495 |
} |
| 496 |
} |
| 497 |
} else {
|
| 498 |
break;
|
| 499 |
} |
| 500 |
} |
| 501 |
} |
| 502 |
} |
| 503 |
|
| 504 |
void apic_init_reset(DeviceState *d)
|
| 505 |
{
|
| 506 |
APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
| 507 |
int i;
|
| 508 |
|
| 509 |
if (!s)
|
| 510 |
return;
|
| 511 |
|
| 512 |
s->tpr = 0;
|
| 513 |
s->spurious_vec = 0xff;
|
| 514 |
s->log_dest = 0;
|
| 515 |
s->dest_mode = 0xf;
|
| 516 |
memset(s->isr, 0, sizeof(s->isr)); |
| 517 |
memset(s->tmr, 0, sizeof(s->tmr)); |
| 518 |
memset(s->irr, 0, sizeof(s->irr)); |
| 519 |
for(i = 0; i < APIC_LVT_NB; i++) |
| 520 |
s->lvt[i] = 1 << 16; /* mask LVT */ |
| 521 |
s->esr = 0;
|
| 522 |
memset(s->icr, 0, sizeof(s->icr)); |
| 523 |
s->divide_conf = 0;
|
| 524 |
s->count_shift = 0;
|
| 525 |
s->initial_count = 0;
|
| 526 |
s->initial_count_load_time = 0;
|
| 527 |
s->next_time = 0;
|
| 528 |
s->wait_for_sipi = 1;
|
| 529 |
} |
| 530 |
|
| 531 |
static void apic_startup(APICState *s, int vector_num) |
| 532 |
{
|
| 533 |
s->sipi_vector = vector_num; |
| 534 |
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
| 535 |
} |
| 536 |
|
| 537 |
void apic_sipi(DeviceState *d)
|
| 538 |
{
|
| 539 |
APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
| 540 |
|
| 541 |
cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
| 542 |
|
| 543 |
if (!s->wait_for_sipi)
|
| 544 |
return;
|
| 545 |
cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector); |
| 546 |
s->wait_for_sipi = 0;
|
| 547 |
} |
| 548 |
|
| 549 |
static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode, |
| 550 |
uint8_t delivery_mode, uint8_t vector_num, |
| 551 |
uint8_t polarity, uint8_t trigger_mode) |
| 552 |
{
|
| 553 |
APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
| 554 |
uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
| 555 |
int dest_shorthand = (s->icr[0] >> 18) & 3; |
| 556 |
APICState *apic_iter; |
| 557 |
|
| 558 |
switch (dest_shorthand) {
|
| 559 |
case 0: |
| 560 |
apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
| 561 |
break;
|
| 562 |
case 1: |
| 563 |
memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); |
| 564 |
set_bit(deliver_bitmask, s->idx); |
| 565 |
break;
|
| 566 |
case 2: |
| 567 |
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
| 568 |
break;
|
| 569 |
case 3: |
| 570 |
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
| 571 |
reset_bit(deliver_bitmask, s->idx); |
| 572 |
break;
|
| 573 |
} |
| 574 |
|
| 575 |
switch (delivery_mode) {
|
| 576 |
case APIC_DM_INIT:
|
| 577 |
{
|
| 578 |
int trig_mode = (s->icr[0] >> 15) & 1; |
| 579 |
int level = (s->icr[0] >> 14) & 1; |
| 580 |
if (level == 0 && trig_mode == 1) { |
| 581 |
foreach_apic(apic_iter, deliver_bitmask, |
| 582 |
apic_iter->arb_id = apic_iter->id ); |
| 583 |
return;
|
| 584 |
} |
| 585 |
} |
| 586 |
break;
|
| 587 |
|
| 588 |
case APIC_DM_SIPI:
|
| 589 |
foreach_apic(apic_iter, deliver_bitmask, |
| 590 |
apic_startup(apic_iter, vector_num) ); |
| 591 |
return;
|
| 592 |
} |
| 593 |
|
| 594 |
apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
| 595 |
trigger_mode); |
| 596 |
} |
| 597 |
|
| 598 |
int apic_get_interrupt(DeviceState *d)
|
| 599 |
{
|
| 600 |
APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
| 601 |
int intno;
|
| 602 |
|
| 603 |
/* if the APIC is installed or enabled, we let the 8259 handle the
|
| 604 |
IRQs */
|
| 605 |
if (!s)
|
| 606 |
return -1; |
| 607 |
if (!(s->spurious_vec & APIC_SV_ENABLE))
|
| 608 |
return -1; |
| 609 |
|
| 610 |
intno = apic_irq_pending(s); |
| 611 |
|
| 612 |
if (intno == 0) { |
| 613 |
return -1; |
| 614 |
} else if (intno < 0) { |
| 615 |
return s->spurious_vec & 0xff; |
| 616 |
} |
| 617 |
reset_bit(s->irr, intno); |
| 618 |
set_bit(s->isr, intno); |
| 619 |
apic_update_irq(s); |
| 620 |
return intno;
|
| 621 |
} |
| 622 |
|
| 623 |
int apic_accept_pic_intr(DeviceState *d)
|
| 624 |
{
|
| 625 |
APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
| 626 |
uint32_t lvt0; |
| 627 |
|
| 628 |
if (!s)
|
| 629 |
return -1; |
| 630 |
|
| 631 |
lvt0 = s->lvt[APIC_LVT_LINT0]; |
| 632 |
|
| 633 |
if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
| 634 |
(lvt0 & APIC_LVT_MASKED) == 0)
|
| 635 |
return 1; |
| 636 |
|
| 637 |
return 0; |
| 638 |
} |
| 639 |
|
| 640 |
static uint32_t apic_get_current_count(APICState *s)
|
| 641 |
{
|
| 642 |
int64_t d; |
| 643 |
uint32_t val; |
| 644 |
d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >> |
| 645 |
s->count_shift; |
| 646 |
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
| 647 |
/* periodic */
|
| 648 |
val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
|
| 649 |
} else {
|
| 650 |
if (d >= s->initial_count)
|
| 651 |
val = 0;
|
| 652 |
else
|
| 653 |
val = s->initial_count - d; |
| 654 |
} |
| 655 |
return val;
|
| 656 |
} |
| 657 |
|
| 658 |
static void apic_timer_update(APICState *s, int64_t current_time) |
| 659 |
{
|
| 660 |
int64_t next_time, d; |
| 661 |
|
| 662 |
if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
|
| 663 |
d = (current_time - s->initial_count_load_time) >> |
| 664 |
s->count_shift; |
| 665 |
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
| 666 |
if (!s->initial_count)
|
| 667 |
goto no_timer;
|
| 668 |
d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); |
| 669 |
} else {
|
| 670 |
if (d >= s->initial_count)
|
| 671 |
goto no_timer;
|
| 672 |
d = (uint64_t)s->initial_count + 1;
|
| 673 |
} |
| 674 |
next_time = s->initial_count_load_time + (d << s->count_shift); |
| 675 |
qemu_mod_timer(s->timer, next_time); |
| 676 |
s->next_time = next_time; |
| 677 |
} else {
|
| 678 |
no_timer:
|
| 679 |
qemu_del_timer(s->timer); |
| 680 |
} |
| 681 |
} |
| 682 |
|
| 683 |
static void apic_timer(void *opaque) |
| 684 |
{
|
| 685 |
APICState *s = opaque; |
| 686 |
|
| 687 |
apic_local_deliver(s, APIC_LVT_TIMER); |
| 688 |
apic_timer_update(s, s->next_time); |
| 689 |
} |
| 690 |
|
| 691 |
static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
| 692 |
{
|
| 693 |
return 0; |
| 694 |
} |
| 695 |
|
| 696 |
static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
| 697 |
{
|
| 698 |
return 0; |
| 699 |
} |
| 700 |
|
| 701 |
static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 702 |
{
|
| 703 |
} |
| 704 |
|
| 705 |
static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 706 |
{
|
| 707 |
} |
| 708 |
|
| 709 |
static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
| 710 |
{
|
| 711 |
DeviceState *d; |
| 712 |
APICState *s; |
| 713 |
uint32_t val; |
| 714 |
int index;
|
| 715 |
|
| 716 |
d = cpu_get_current_apic(); |
| 717 |
if (!d) {
|
| 718 |
return 0; |
| 719 |
} |
| 720 |
s = DO_UPCAST(APICState, busdev.qdev, d); |
| 721 |
|
| 722 |
index = (addr >> 4) & 0xff; |
| 723 |
switch(index) {
|
| 724 |
case 0x02: /* id */ |
| 725 |
val = s->id << 24;
|
| 726 |
break;
|
| 727 |
case 0x03: /* version */ |
| 728 |
val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ |
| 729 |
break;
|
| 730 |
case 0x08: |
| 731 |
val = s->tpr; |
| 732 |
break;
|
| 733 |
case 0x09: |
| 734 |
val = apic_get_arb_pri(s); |
| 735 |
break;
|
| 736 |
case 0x0a: |
| 737 |
/* ppr */
|
| 738 |
val = apic_get_ppr(s); |
| 739 |
break;
|
| 740 |
case 0x0b: |
| 741 |
val = 0;
|
| 742 |
break;
|
| 743 |
case 0x0d: |
| 744 |
val = s->log_dest << 24;
|
| 745 |
break;
|
| 746 |
case 0x0e: |
| 747 |
val = s->dest_mode << 28;
|
| 748 |
break;
|
| 749 |
case 0x0f: |
| 750 |
val = s->spurious_vec; |
| 751 |
break;
|
| 752 |
case 0x10 ... 0x17: |
| 753 |
val = s->isr[index & 7];
|
| 754 |
break;
|
| 755 |
case 0x18 ... 0x1f: |
| 756 |
val = s->tmr[index & 7];
|
| 757 |
break;
|
| 758 |
case 0x20 ... 0x27: |
| 759 |
val = s->irr[index & 7];
|
| 760 |
break;
|
| 761 |
case 0x28: |
| 762 |
val = s->esr; |
| 763 |
break;
|
| 764 |
case 0x30: |
| 765 |
case 0x31: |
| 766 |
val = s->icr[index & 1];
|
| 767 |
break;
|
| 768 |
case 0x32 ... 0x37: |
| 769 |
val = s->lvt[index - 0x32];
|
| 770 |
break;
|
| 771 |
case 0x38: |
| 772 |
val = s->initial_count; |
| 773 |
break;
|
| 774 |
case 0x39: |
| 775 |
val = apic_get_current_count(s); |
| 776 |
break;
|
| 777 |
case 0x3e: |
| 778 |
val = s->divide_conf; |
| 779 |
break;
|
| 780 |
default:
|
| 781 |
s->esr |= ESR_ILLEGAL_ADDRESS; |
| 782 |
val = 0;
|
| 783 |
break;
|
| 784 |
} |
| 785 |
trace_apic_mem_readl(addr, val); |
| 786 |
return val;
|
| 787 |
} |
| 788 |
|
| 789 |
static void apic_send_msi(target_phys_addr_t addr, uint32_t data) |
| 790 |
{
|
| 791 |
uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; |
| 792 |
uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; |
| 793 |
uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
|
| 794 |
uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
|
| 795 |
uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
|
| 796 |
/* XXX: Ignore redirection hint. */
|
| 797 |
apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
|
| 798 |
} |
| 799 |
|
| 800 |
static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 801 |
{
|
| 802 |
DeviceState *d; |
| 803 |
APICState *s; |
| 804 |
int index = (addr >> 4) & 0xff; |
| 805 |
if (addr > 0xfff || !index) { |
| 806 |
/* MSI and MMIO APIC are at the same memory location,
|
| 807 |
* but actually not on the global bus: MSI is on PCI bus
|
| 808 |
* APIC is connected directly to the CPU.
|
| 809 |
* Mapping them on the global bus happens to work because
|
| 810 |
* MSI registers are reserved in APIC MMIO and vice versa. */
|
| 811 |
apic_send_msi(addr, val); |
| 812 |
return;
|
| 813 |
} |
| 814 |
|
| 815 |
d = cpu_get_current_apic(); |
| 816 |
if (!d) {
|
| 817 |
return;
|
| 818 |
} |
| 819 |
s = DO_UPCAST(APICState, busdev.qdev, d); |
| 820 |
|
| 821 |
trace_apic_mem_writel(addr, val); |
| 822 |
|
| 823 |
switch(index) {
|
| 824 |
case 0x02: |
| 825 |
s->id = (val >> 24);
|
| 826 |
break;
|
| 827 |
case 0x03: |
| 828 |
break;
|
| 829 |
case 0x08: |
| 830 |
s->tpr = val; |
| 831 |
apic_update_irq(s); |
| 832 |
break;
|
| 833 |
case 0x09: |
| 834 |
case 0x0a: |
| 835 |
break;
|
| 836 |
case 0x0b: /* EOI */ |
| 837 |
apic_eoi(s); |
| 838 |
break;
|
| 839 |
case 0x0d: |
| 840 |
s->log_dest = val >> 24;
|
| 841 |
break;
|
| 842 |
case 0x0e: |
| 843 |
s->dest_mode = val >> 28;
|
| 844 |
break;
|
| 845 |
case 0x0f: |
| 846 |
s->spurious_vec = val & 0x1ff;
|
| 847 |
apic_update_irq(s); |
| 848 |
break;
|
| 849 |
case 0x10 ... 0x17: |
| 850 |
case 0x18 ... 0x1f: |
| 851 |
case 0x20 ... 0x27: |
| 852 |
case 0x28: |
| 853 |
break;
|
| 854 |
case 0x30: |
| 855 |
s->icr[0] = val;
|
| 856 |
apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
| 857 |
(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
| 858 |
(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); |
| 859 |
break;
|
| 860 |
case 0x31: |
| 861 |
s->icr[1] = val;
|
| 862 |
break;
|
| 863 |
case 0x32 ... 0x37: |
| 864 |
{
|
| 865 |
int n = index - 0x32; |
| 866 |
s->lvt[n] = val; |
| 867 |
if (n == APIC_LVT_TIMER)
|
| 868 |
apic_timer_update(s, qemu_get_clock_ns(vm_clock)); |
| 869 |
} |
| 870 |
break;
|
| 871 |
case 0x38: |
| 872 |
s->initial_count = val; |
| 873 |
s->initial_count_load_time = qemu_get_clock_ns(vm_clock); |
| 874 |
apic_timer_update(s, s->initial_count_load_time); |
| 875 |
break;
|
| 876 |
case 0x39: |
| 877 |
break;
|
| 878 |
case 0x3e: |
| 879 |
{
|
| 880 |
int v;
|
| 881 |
s->divide_conf = val & 0xb;
|
| 882 |
v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); |
| 883 |
s->count_shift = (v + 1) & 7; |
| 884 |
} |
| 885 |
break;
|
| 886 |
default:
|
| 887 |
s->esr |= ESR_ILLEGAL_ADDRESS; |
| 888 |
break;
|
| 889 |
} |
| 890 |
} |
| 891 |
|
| 892 |
/* This function is only used for old state version 1 and 2 */
|
| 893 |
static int apic_load_old(QEMUFile *f, void *opaque, int version_id) |
| 894 |
{
|
| 895 |
APICState *s = opaque; |
| 896 |
int i;
|
| 897 |
|
| 898 |
if (version_id > 2) |
| 899 |
return -EINVAL;
|
| 900 |
|
| 901 |
/* XXX: what if the base changes? (registered memory regions) */
|
| 902 |
qemu_get_be32s(f, &s->apicbase); |
| 903 |
qemu_get_8s(f, &s->id); |
| 904 |
qemu_get_8s(f, &s->arb_id); |
| 905 |
qemu_get_8s(f, &s->tpr); |
| 906 |
qemu_get_be32s(f, &s->spurious_vec); |
| 907 |
qemu_get_8s(f, &s->log_dest); |
| 908 |
qemu_get_8s(f, &s->dest_mode); |
| 909 |
for (i = 0; i < 8; i++) { |
| 910 |
qemu_get_be32s(f, &s->isr[i]); |
| 911 |
qemu_get_be32s(f, &s->tmr[i]); |
| 912 |
qemu_get_be32s(f, &s->irr[i]); |
| 913 |
} |
| 914 |
for (i = 0; i < APIC_LVT_NB; i++) { |
| 915 |
qemu_get_be32s(f, &s->lvt[i]); |
| 916 |
} |
| 917 |
qemu_get_be32s(f, &s->esr); |
| 918 |
qemu_get_be32s(f, &s->icr[0]);
|
| 919 |
qemu_get_be32s(f, &s->icr[1]);
|
| 920 |
qemu_get_be32s(f, &s->divide_conf); |
| 921 |
s->count_shift=qemu_get_be32(f); |
| 922 |
qemu_get_be32s(f, &s->initial_count); |
| 923 |
s->initial_count_load_time=qemu_get_be64(f); |
| 924 |
s->next_time=qemu_get_be64(f); |
| 925 |
|
| 926 |
if (version_id >= 2) |
| 927 |
qemu_get_timer(f, s->timer); |
| 928 |
return 0; |
| 929 |
} |
| 930 |
|
| 931 |
static const VMStateDescription vmstate_apic = { |
| 932 |
.name = "apic",
|
| 933 |
.version_id = 3,
|
| 934 |
.minimum_version_id = 3,
|
| 935 |
.minimum_version_id_old = 1,
|
| 936 |
.load_state_old = apic_load_old, |
| 937 |
.fields = (VMStateField []) {
|
| 938 |
VMSTATE_UINT32(apicbase, APICState), |
| 939 |
VMSTATE_UINT8(id, APICState), |
| 940 |
VMSTATE_UINT8(arb_id, APICState), |
| 941 |
VMSTATE_UINT8(tpr, APICState), |
| 942 |
VMSTATE_UINT32(spurious_vec, APICState), |
| 943 |
VMSTATE_UINT8(log_dest, APICState), |
| 944 |
VMSTATE_UINT8(dest_mode, APICState), |
| 945 |
VMSTATE_UINT32_ARRAY(isr, APICState, 8),
|
| 946 |
VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
|
| 947 |
VMSTATE_UINT32_ARRAY(irr, APICState, 8),
|
| 948 |
VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB), |
| 949 |
VMSTATE_UINT32(esr, APICState), |
| 950 |
VMSTATE_UINT32_ARRAY(icr, APICState, 2),
|
| 951 |
VMSTATE_UINT32(divide_conf, APICState), |
| 952 |
VMSTATE_INT32(count_shift, APICState), |
| 953 |
VMSTATE_UINT32(initial_count, APICState), |
| 954 |
VMSTATE_INT64(initial_count_load_time, APICState), |
| 955 |
VMSTATE_INT64(next_time, APICState), |
| 956 |
VMSTATE_TIMER(timer, APICState), |
| 957 |
VMSTATE_END_OF_LIST() |
| 958 |
} |
| 959 |
}; |
| 960 |
|
| 961 |
static void apic_reset(DeviceState *d) |
| 962 |
{
|
| 963 |
APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
| 964 |
int bsp;
|
| 965 |
|
| 966 |
bsp = cpu_is_bsp(s->cpu_env); |
| 967 |
s->apicbase = 0xfee00000 |
|
| 968 |
(bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
|
| 969 |
|
| 970 |
apic_init_reset(d); |
| 971 |
|
| 972 |
if (bsp) {
|
| 973 |
/*
|
| 974 |
* LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
|
| 975 |
* time typically by BIOS, so PIC interrupt can be delivered to the
|
| 976 |
* processor when local APIC is enabled.
|
| 977 |
*/
|
| 978 |
s->lvt[APIC_LVT_LINT0] = 0x700;
|
| 979 |
} |
| 980 |
} |
| 981 |
|
| 982 |
static CPUReadMemoryFunc * const apic_mem_read[3] = { |
| 983 |
apic_mem_readb, |
| 984 |
apic_mem_readw, |
| 985 |
apic_mem_readl, |
| 986 |
}; |
| 987 |
|
| 988 |
static CPUWriteMemoryFunc * const apic_mem_write[3] = { |
| 989 |
apic_mem_writeb, |
| 990 |
apic_mem_writew, |
| 991 |
apic_mem_writel, |
| 992 |
}; |
| 993 |
|
| 994 |
static int apic_init1(SysBusDevice *dev) |
| 995 |
{
|
| 996 |
APICState *s = FROM_SYSBUS(APICState, dev); |
| 997 |
int apic_io_memory;
|
| 998 |
static int last_apic_idx; |
| 999 |
|
| 1000 |
if (last_apic_idx >= MAX_APICS) {
|
| 1001 |
return -1; |
| 1002 |
} |
| 1003 |
apic_io_memory = cpu_register_io_memory(apic_mem_read, |
| 1004 |
apic_mem_write, NULL,
|
| 1005 |
DEVICE_NATIVE_ENDIAN); |
| 1006 |
sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory); |
| 1007 |
|
| 1008 |
s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s); |
| 1009 |
s->idx = last_apic_idx++; |
| 1010 |
local_apics[s->idx] = s; |
| 1011 |
return 0; |
| 1012 |
} |
| 1013 |
|
| 1014 |
static SysBusDeviceInfo apic_info = {
|
| 1015 |
.init = apic_init1, |
| 1016 |
.qdev.name = "apic",
|
| 1017 |
.qdev.size = sizeof(APICState),
|
| 1018 |
.qdev.vmsd = &vmstate_apic, |
| 1019 |
.qdev.reset = apic_reset, |
| 1020 |
.qdev.no_user = 1,
|
| 1021 |
.qdev.props = (Property[]) {
|
| 1022 |
DEFINE_PROP_UINT8("id", APICState, id, -1), |
| 1023 |
DEFINE_PROP_PTR("cpu_env", APICState, cpu_env),
|
| 1024 |
DEFINE_PROP_END_OF_LIST(), |
| 1025 |
} |
| 1026 |
}; |
| 1027 |
|
| 1028 |
static void apic_register_devices(void) |
| 1029 |
{
|
| 1030 |
sysbus_register_withprop(&apic_info); |
| 1031 |
} |
| 1032 |
|
| 1033 |
device_init(apic_register_devices) |