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/*
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* VT82C686B south bridge support
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*
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* Copyright (c) 2008 yajin (yajin@vm-kernel.org)
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* Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
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* Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
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* This code is licensed under the GNU GPL v2.
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "vt82c686.h" |
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#include "i2c.h" |
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#include "smbus.h" |
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#include "pci.h" |
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#include "isa.h" |
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#include "sysbus.h" |
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#include "mips.h" |
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#include "apm.h" |
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#include "acpi.h" |
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#include "pm_smbus.h" |
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#include "sysemu.h" |
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#include "qemu-timer.h" |
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typedef uint32_t pci_addr_t;
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#include "pci_host.h" |
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//#define DEBUG_VT82C686B
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#ifdef DEBUG_VT82C686B
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#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) |
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#else
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#define DPRINTF(fmt, ...)
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#endif
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typedef struct SuperIOConfig |
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{ |
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uint8_t config[0xff];
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uint8_t index; |
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uint8_t data; |
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} SuperIOConfig; |
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typedef struct VT82C686BState { |
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PCIDevice dev; |
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SuperIOConfig superio_conf; |
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} VT82C686BState; |
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|
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static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data) |
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{ |
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int can_write;
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SuperIOConfig *superio_conf = opaque; |
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DPRINTF("superio_ioport_writeb address 0x%x val 0x%x \n", addr, data);
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if (addr == 0x3f0) { |
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superio_conf->index = data & 0xff;
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} else {
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/* 0x3f1 */
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switch (superio_conf->index) {
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case 0x00 ... 0xdf: |
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case 0xe4: |
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case 0xe5: |
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case 0xe9 ... 0xed: |
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case 0xf3: |
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case 0xf5: |
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case 0xf7: |
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case 0xf9 ... 0xfb: |
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case 0xfd ... 0xff: |
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can_write = 0;
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break;
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default:
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can_write = 1;
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if (can_write) {
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switch (superio_conf->index) {
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case 0xe7: |
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if ((data & 0xff) != 0xfe) { |
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DPRINTF("chage uart 1 base. unsupported yet \n");
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} |
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break;
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case 0xe8: |
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if ((data & 0xff) != 0xbe) { |
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DPRINTF("chage uart 2 base. unsupported yet \n");
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} |
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break;
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default:
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superio_conf->config[superio_conf->index] = data & 0xff;
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} |
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} |
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} |
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superio_conf->config[superio_conf->index] = data & 0xff;
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} |
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} |
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static uint32_t superio_ioport_readb(void *opaque, uint32_t addr) |
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{ |
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SuperIOConfig *superio_conf = opaque; |
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DPRINTF("superio_ioport_readb address 0x%x \n", addr);
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return (superio_conf->config[superio_conf->index]);
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} |
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static void vt82c686b_reset(void * opaque) |
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{ |
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PCIDevice *d = opaque; |
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uint8_t *pci_conf = d->config; |
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VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d); |
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pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
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PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); |
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); |
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pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ |
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pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ |
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pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ |
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pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ |
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pci_conf[0x59] = 0x04; |
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pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ |
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pci_conf[0x5f] = 0x04; |
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pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ |
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vt82c->superio_conf.config[0xe0] = 0x3c; |
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vt82c->superio_conf.config[0xe2] = 0x03; |
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vt82c->superio_conf.config[0xe3] = 0xfc; |
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vt82c->superio_conf.config[0xe6] = 0xde; |
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vt82c->superio_conf.config[0xe7] = 0xfe; |
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vt82c->superio_conf.config[0xe8] = 0xbe; |
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} |
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/* write config pci function0 registers. PCI-ISA bridge */
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static void vt82c686b_write_config(PCIDevice * d, uint32_t address, |
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uint32_t val, int len)
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{ |
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VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d); |
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DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x \n",
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address, val, len); |
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pci_default_write_config(d, address, val, len); |
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if (address == 0x85) { /* enable or disable super IO configure */ |
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if (val & 0x2) { |
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/* floppy also uses 0x3f0 and 0x3f1.
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* But we do not emulate flopy,so just set it here. */
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isa_unassign_ioport(0x3f0, 2); |
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register_ioport_read(0x3f0, 2, 1, superio_ioport_readb, |
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&vt686->superio_conf); |
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register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb, |
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&vt686->superio_conf); |
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} else {
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isa_unassign_ioport(0x3f0, 2); |
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} |
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} |
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} |
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#define ACPI_DBG_IO_ADDR 0xb044 |
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typedef struct VT686PMState { |
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PCIDevice dev; |
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uint16_t pmsts; |
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uint16_t pmen; |
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uint16_t pmcntrl; |
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APMState apm; |
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QEMUTimer *tmr_timer; |
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int64_t tmr_overflow_time; |
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PMSMBus smb; |
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uint32_t smb_io_base; |
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} VT686PMState; |
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typedef struct VT686AC97State { |
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PCIDevice dev; |
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} VT686AC97State; |
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typedef struct VT686MC97State { |
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PCIDevice dev; |
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} VT686MC97State; |
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#define RTC_EN (1 << 10) |
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#define PWRBTN_EN (1 << 8) |
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#define GBL_EN (1 << 5) |
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#define TMROF_EN (1 << 0) |
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#define SUS_EN (1 << 13) |
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#define ACPI_ENABLE 0xf1 |
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#define ACPI_DISABLE 0xf0 |
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static uint32_t get_pmtmr(VT686PMState *s)
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{ |
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uint32_t d; |
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d = muldiv64(qemu_get_clock_ns(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec()); |
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return d & 0xffffff; |
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} |
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static int get_pmsts(VT686PMState *s) |
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{ |
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int64_t d; |
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int pmsts;
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pmsts = s->pmsts; |
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d = muldiv64(qemu_get_clock_ns(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec()); |
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if (d >= s->tmr_overflow_time)
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s->pmsts |= TMROF_EN; |
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return pmsts;
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} |
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static void pm_update_sci(VT686PMState *s) |
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{ |
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int sci_level, pmsts;
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int64_t expire_time; |
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pmsts = get_pmsts(s); |
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sci_level = (((pmsts & s->pmen) & |
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(RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
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qemu_set_irq(s->dev.irq[0], sci_level);
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/* schedule a timer interruption if needed */
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if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
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expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(), PM_TIMER_FREQUENCY); |
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qemu_mod_timer(s->tmr_timer, expire_time); |
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} else {
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qemu_del_timer(s->tmr_timer); |
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} |
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} |
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static void pm_tmr_timer(void *opaque) |
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{ |
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VT686PMState *s = opaque; |
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pm_update_sci(s); |
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} |
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static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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VT686PMState *s = opaque; |
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addr &= 0x0f;
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switch (addr) {
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case 0x00: |
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{ |
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int64_t d; |
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int pmsts;
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pmsts = get_pmsts(s); |
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if (pmsts & val & TMROF_EN) {
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/* if TMRSTS is reset, then compute the new overflow time */
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d = muldiv64(qemu_get_clock_ns(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec()); |
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s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; |
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} |
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s->pmsts &= ~val; |
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pm_update_sci(s); |
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} |
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break;
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case 0x02: |
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s->pmen = val; |
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pm_update_sci(s); |
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break;
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case 0x04: |
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{ |
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int sus_typ;
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s->pmcntrl = val & ~(SUS_EN); |
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if (val & SUS_EN) {
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/* change suspend type */
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sus_typ = (val >> 10) & 3; |
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switch (sus_typ) {
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case 0: /* soft power off */ |
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qemu_system_shutdown_request(); |
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break;
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default:
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break;
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} |
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} |
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} |
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break;
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default:
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break;
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} |
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DPRINTF("PM writew port=0x%04x val=0x%02x\n", addr, val);
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} |
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static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) |
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{ |
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VT686PMState *s = opaque; |
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uint32_t val; |
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addr &= 0x0f;
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switch (addr) {
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case 0x00: |
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val = get_pmsts(s); |
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break;
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case 0x02: |
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val = s->pmen; |
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break;
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case 0x04: |
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val = s->pmcntrl; |
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break;
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default:
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val = 0;
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break;
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} |
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DPRINTF("PM readw port=0x%04x val=0x%02x\n", addr, val);
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return val;
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} |
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static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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addr &= 0x0f;
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DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr, val);
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} |
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static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) |
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{ |
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VT686PMState *s = opaque; |
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uint32_t val; |
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addr &= 0x0f;
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switch (addr) {
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case 0x08: |
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val = get_pmtmr(s); |
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break;
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default:
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val = 0;
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break;
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} |
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DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
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return val;
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} |
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static void pm_io_space_update(VT686PMState *s) |
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{ |
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uint32_t pm_io_base; |
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if (s->dev.config[0x80] & 1) { |
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pm_io_base = pci_get_long(s->dev.config + 0x40);
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pm_io_base &= 0xffc0;
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/* XXX: need to improve memory and ioport allocation */
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DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
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register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); |
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register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); |
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register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); |
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register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s); |
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} |
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} |
339 |
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static void pm_write_config(PCIDevice *d, |
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uint32_t address, uint32_t val, int len)
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{ |
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DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x \n",
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address, val, len); |
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pci_default_write_config(d, address, val, len); |
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} |
347 |
|
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static int vmstate_acpi_post_load(void *opaque, int version_id) |
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{ |
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VT686PMState *s = opaque; |
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pm_io_space_update(s); |
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return 0; |
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} |
355 |
|
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static const VMStateDescription vmstate_acpi = { |
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.name = "vt82c686b_pm",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = vmstate_acpi_post_load, |
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.fields = (VMStateField []) { |
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VMSTATE_PCI_DEVICE(dev, VT686PMState), |
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VMSTATE_UINT16(pmsts, VT686PMState), |
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VMSTATE_UINT16(pmen, VT686PMState), |
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VMSTATE_UINT16(pmcntrl, VT686PMState), |
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VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
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VMSTATE_TIMER(tmr_timer, VT686PMState), |
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VMSTATE_INT64(tmr_overflow_time, VT686PMState), |
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VMSTATE_END_OF_LIST() |
371 |
} |
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}; |
373 |
|
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/*
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* TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
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* just register a PCI device now, functionalities will be implemented later.
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*/
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|
379 |
static int vt82c686b_ac97_initfn(PCIDevice *dev) |
380 |
{ |
381 |
VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev); |
382 |
uint8_t *pci_conf = s->dev.config; |
383 |
|
384 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA); |
385 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_AC97); |
386 |
pci_config_set_class(pci_conf, PCI_CLASS_MULTIMEDIA_AUDIO); |
387 |
pci_config_set_revision(pci_conf, 0x50);
|
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|
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
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PCI_COMMAND_PARITY); |
391 |
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST | |
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PCI_STATUS_DEVSEL_MEDIUM); |
393 |
pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
|
394 |
|
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return 0; |
396 |
} |
397 |
|
398 |
void vt82c686b_ac97_init(PCIBus *bus, int devfn) |
399 |
{ |
400 |
PCIDevice *dev; |
401 |
|
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dev = pci_create(bus, devfn, "VT82C686B_AC97");
|
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qdev_init_nofail(&dev->qdev); |
404 |
} |
405 |
|
406 |
static PCIDeviceInfo via_ac97_info = {
|
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.qdev.name = "VT82C686B_AC97",
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.qdev.desc = "AC97",
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.qdev.size = sizeof(VT686AC97State),
|
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.init = vt82c686b_ac97_initfn, |
411 |
}; |
412 |
|
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static void vt82c686b_ac97_register(void) |
414 |
{ |
415 |
pci_qdev_register(&via_ac97_info); |
416 |
} |
417 |
|
418 |
device_init(vt82c686b_ac97_register); |
419 |
|
420 |
static int vt82c686b_mc97_initfn(PCIDevice *dev) |
421 |
{ |
422 |
VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev); |
423 |
uint8_t *pci_conf = s->dev.config; |
424 |
|
425 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA); |
426 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_MC97); |
427 |
pci_config_set_class(pci_conf, PCI_CLASS_COMMUNICATION_OTHER); |
428 |
pci_config_set_revision(pci_conf, 0x30);
|
429 |
|
430 |
pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
431 |
PCI_COMMAND_VGA_PALETTE); |
432 |
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); |
433 |
pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
|
434 |
|
435 |
return 0; |
436 |
} |
437 |
|
438 |
void vt82c686b_mc97_init(PCIBus *bus, int devfn) |
439 |
{ |
440 |
PCIDevice *dev; |
441 |
|
442 |
dev = pci_create(bus, devfn, "VT82C686B_MC97");
|
443 |
qdev_init_nofail(&dev->qdev); |
444 |
} |
445 |
|
446 |
static PCIDeviceInfo via_mc97_info = {
|
447 |
.qdev.name = "VT82C686B_MC97",
|
448 |
.qdev.desc = "MC97",
|
449 |
.qdev.size = sizeof(VT686MC97State),
|
450 |
.init = vt82c686b_mc97_initfn, |
451 |
}; |
452 |
|
453 |
static void vt82c686b_mc97_register(void) |
454 |
{ |
455 |
pci_qdev_register(&via_mc97_info); |
456 |
} |
457 |
|
458 |
device_init(vt82c686b_mc97_register); |
459 |
|
460 |
/* vt82c686 pm init */
|
461 |
static int vt82c686b_pm_initfn(PCIDevice *dev) |
462 |
{ |
463 |
VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev); |
464 |
uint8_t *pci_conf; |
465 |
|
466 |
pci_conf = s->dev.config; |
467 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA); |
468 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_ACPI); |
469 |
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER); |
470 |
pci_config_set_revision(pci_conf, 0x40);
|
471 |
|
472 |
pci_set_word(pci_conf + PCI_COMMAND, 0);
|
473 |
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | |
474 |
PCI_STATUS_DEVSEL_MEDIUM); |
475 |
|
476 |
/* 0x48-0x4B is Power Management I/O Base */
|
477 |
pci_set_long(pci_conf + 0x48, 0x00000001); |
478 |
|
479 |
/* SMB ports:0xeee0~0xeeef */
|
480 |
s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0); |
481 |
pci_conf[0x90] = s->smb_io_base | 1; |
482 |
pci_conf[0x91] = s->smb_io_base >> 8; |
483 |
pci_conf[0xd2] = 0x90; |
484 |
register_ioport_write(s->smb_io_base, 0xf, 1, smb_ioport_writeb, &s->smb); |
485 |
register_ioport_read(s->smb_io_base, 0xf, 1, smb_ioport_readb, &s->smb); |
486 |
|
487 |
apm_init(&s->apm, NULL, s);
|
488 |
|
489 |
s->tmr_timer = qemu_new_timer_ns(vm_clock, pm_tmr_timer, s); |
490 |
|
491 |
pm_smbus_init(&s->dev.qdev, &s->smb); |
492 |
|
493 |
return 0; |
494 |
} |
495 |
|
496 |
i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
497 |
qemu_irq sci_irq) |
498 |
{ |
499 |
PCIDevice *dev; |
500 |
VT686PMState *s; |
501 |
|
502 |
dev = pci_create(bus, devfn, "VT82C686B_PM");
|
503 |
qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
|
504 |
|
505 |
s = DO_UPCAST(VT686PMState, dev, dev); |
506 |
|
507 |
qdev_init_nofail(&dev->qdev); |
508 |
|
509 |
return s->smb.smbus;
|
510 |
} |
511 |
|
512 |
static PCIDeviceInfo via_pm_info = {
|
513 |
.qdev.name = "VT82C686B_PM",
|
514 |
.qdev.desc = "PM",
|
515 |
.qdev.size = sizeof(VT686PMState),
|
516 |
.qdev.vmsd = &vmstate_acpi, |
517 |
.init = vt82c686b_pm_initfn, |
518 |
.config_write = pm_write_config, |
519 |
.qdev.props = (Property[]) { |
520 |
DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0), |
521 |
DEFINE_PROP_END_OF_LIST(), |
522 |
} |
523 |
}; |
524 |
|
525 |
static void vt82c686b_pm_register(void) |
526 |
{ |
527 |
pci_qdev_register(&via_pm_info); |
528 |
} |
529 |
|
530 |
device_init(vt82c686b_pm_register); |
531 |
|
532 |
static const VMStateDescription vmstate_via = { |
533 |
.name = "vt82c686b",
|
534 |
.version_id = 1,
|
535 |
.minimum_version_id = 1,
|
536 |
.minimum_version_id_old = 1,
|
537 |
.fields = (VMStateField []) { |
538 |
VMSTATE_PCI_DEVICE(dev, VT82C686BState), |
539 |
VMSTATE_END_OF_LIST() |
540 |
} |
541 |
}; |
542 |
|
543 |
/* init the PCI-to-ISA bridge */
|
544 |
static int vt82c686b_initfn(PCIDevice *d) |
545 |
{ |
546 |
uint8_t *pci_conf; |
547 |
uint8_t *wmask; |
548 |
int i;
|
549 |
|
550 |
isa_bus_new(&d->qdev); |
551 |
|
552 |
pci_conf = d->config; |
553 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA); |
554 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_ISA_BRIDGE); |
555 |
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA); |
556 |
pci_config_set_prog_interface(pci_conf, 0x0);
|
557 |
pci_config_set_revision(pci_conf,0x40); /* Revision 4.0 */ |
558 |
|
559 |
wmask = d->wmask; |
560 |
for (i = 0x00; i < 0xff; i++) { |
561 |
if (i<=0x03 || (i>=0x08 && i<=0x3f)) { |
562 |
wmask[i] = 0x00;
|
563 |
} |
564 |
} |
565 |
|
566 |
qemu_register_reset(vt82c686b_reset, d); |
567 |
|
568 |
return 0; |
569 |
} |
570 |
|
571 |
int vt82c686b_init(PCIBus *bus, int devfn) |
572 |
{ |
573 |
PCIDevice *d; |
574 |
|
575 |
d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B"); |
576 |
|
577 |
return d->devfn;
|
578 |
} |
579 |
|
580 |
static PCIDeviceInfo via_info = {
|
581 |
.qdev.name = "VT82C686B",
|
582 |
.qdev.desc = "ISA bridge",
|
583 |
.qdev.size = sizeof(VT82C686BState),
|
584 |
.qdev.vmsd = &vmstate_via, |
585 |
.qdev.no_user = 1,
|
586 |
.init = vt82c686b_initfn, |
587 |
.config_write = vt82c686b_write_config, |
588 |
}; |
589 |
|
590 |
static void vt82c686b_register(void) |
591 |
{ |
592 |
pci_qdev_register(&via_info); |
593 |
} |
594 |
device_init(vt82c686b_register); |