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1
/*
2
 *  MIPS emulation helpers for qemu.
3
 * 
4
 *  Copyright (c) 2004-2005 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
20
#include <stdlib.h>
21
#include "exec.h"
22

    
23
#define MIPS_DEBUG_DISAS
24

    
25
#define GETPC() (__builtin_return_address(0))
26

    
27
/*****************************************************************************/
28
/* Exceptions processing helpers */
29
void cpu_loop_exit(void)
30
{
31
    longjmp(env->jmp_env, 1);
32
}
33

    
34
void do_raise_exception_err (uint32_t exception, int error_code)
35
{
36
#if 1
37
    if (logfile && exception < 0x100)
38
        fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
39
#endif
40
    env->exception_index = exception;
41
    env->error_code = error_code;
42
    T0 = 0;
43
    cpu_loop_exit();
44
}
45

    
46
void do_raise_exception (uint32_t exception)
47
{
48
    do_raise_exception_err(exception, 0);
49
}
50

    
51
void do_restore_state (void *pc_ptr)
52
{
53
  TranslationBlock *tb;
54
  unsigned long pc = (unsigned long) pc_ptr;
55

    
56
  tb = tb_find_pc (pc);
57
  cpu_restore_state (tb, env, pc, NULL);
58
}
59

    
60
void do_raise_exception_direct_err (uint32_t exception, int error_code)
61
{
62
    do_restore_state (GETPC ());
63
    do_raise_exception_err (exception, error_code);
64
}
65

    
66
void do_raise_exception_direct (uint32_t exception)
67
{
68
    do_raise_exception_direct_err (exception, 0);
69
}
70

    
71
#define MEMSUFFIX _raw
72
#include "op_helper_mem.c"
73
#undef MEMSUFFIX
74
#if !defined(CONFIG_USER_ONLY)
75
#define MEMSUFFIX _user
76
#include "op_helper_mem.c"
77
#undef MEMSUFFIX
78
#define MEMSUFFIX _kernel
79
#include "op_helper_mem.c"
80
#undef MEMSUFFIX
81
#endif
82

    
83
#ifdef TARGET_MIPS64
84
#if TARGET_LONG_BITS > HOST_LONG_BITS
85
/* Those might call libgcc functions.  */
86
void do_dsll (void)
87
{
88
    T0 = T0 << T1;
89
}
90

    
91
void do_dsll32 (void)
92
{
93
    T0 = T0 << (T1 + 32);
94
}
95

    
96
void do_dsra (void)
97
{
98
    T0 = (int64_t)T0 >> T1;
99
}
100

    
101
void do_dsra32 (void)
102
{
103
    T0 = (int64_t)T0 >> (T1 + 32);
104
}
105

    
106
void do_dsrl (void)
107
{
108
    T0 = T0 >> T1;
109
}
110

    
111
void do_dsrl32 (void)
112
{
113
    T0 = T0 >> (T1 + 32);
114
}
115

    
116
void do_drotr (void)
117
{
118
    target_ulong tmp;
119

    
120
    if (T1) {
121
       tmp = T0 << (0x40 - T1);
122
       T0 = (T0 >> T1) | tmp;
123
    }
124
}
125

    
126
void do_drotr32 (void)
127
{
128
    target_ulong tmp;
129

    
130
    if (T1) {
131
       tmp = T0 << (0x40 - (32 + T1));
132
       T0 = (T0 >> (32 + T1)) | tmp;
133
    }
134
}
135

    
136
void do_dsllv (void)
137
{
138
    T0 = T1 << (T0 & 0x3F);
139
}
140

    
141
void do_dsrav (void)
142
{
143
    T0 = (int64_t)T1 >> (T0 & 0x3F);
144
}
145

    
146
void do_dsrlv (void)
147
{
148
    T0 = T1 >> (T0 & 0x3F);
149
}
150

    
151
void do_drotrv (void)
152
{
153
    target_ulong tmp;
154

    
155
    T0 &= 0x3F;
156
    if (T0) {
157
       tmp = T1 << (0x40 - T0);
158
       T0 = (T1 >> T0) | tmp;
159
    } else
160
       T0 = T1;
161
}
162
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
163
#endif /* TARGET_MIPS64 */
164

    
165
/* 64 bits arithmetic for 32 bits hosts */
166
#if TARGET_LONG_BITS > HOST_LONG_BITS
167
static inline uint64_t get_HILO (void)
168
{
169
    return (env->HI << 32) | (uint32_t)env->LO;
170
}
171

    
172
static inline void set_HILO (uint64_t HILO)
173
{
174
    env->LO = (int32_t)HILO;
175
    env->HI = (int32_t)(HILO >> 32);
176
}
177

    
178
void do_mult (void)
179
{
180
    set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
181
}
182

    
183
void do_multu (void)
184
{
185
    set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
186
}
187

    
188
void do_madd (void)
189
{
190
    int64_t tmp;
191

    
192
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
193
    set_HILO((int64_t)get_HILO() + tmp);
194
}
195

    
196
void do_maddu (void)
197
{
198
    uint64_t tmp;
199

    
200
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
201
    set_HILO(get_HILO() + tmp);
202
}
203

    
204
void do_msub (void)
205
{
206
    int64_t tmp;
207

    
208
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
209
    set_HILO((int64_t)get_HILO() - tmp);
210
}
211

    
212
void do_msubu (void)
213
{
214
    uint64_t tmp;
215

    
216
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
217
    set_HILO(get_HILO() - tmp);
218
}
219
#endif
220

    
221
#ifdef TARGET_MIPS64
222
void do_dmult (void)
223
{
224
    env->LO = (int64_t)T0 * (int64_t)T1;
225
    /* XXX */
226
    env->HI = (env->LO | (1ULL << 63)) ? ~0ULL : 0ULL;
227
}
228

    
229
void do_dmultu (void)
230
{
231
    env->LO = T0 * T1;
232
    /* XXX */
233
    env->HI = 0;
234
}
235

    
236
void do_ddiv (void)
237
{
238
    if (T1 != 0) {
239
        lldiv_t res = lldiv((int64_t)T0, (int64_t)T1);
240
        env->LO = res.quot;
241
        env->HI = res.rem;
242
    }
243
}
244

    
245
void do_ddivu (void)
246
{
247
    if (T1 != 0) {
248
        /* XXX: lldivu? */
249
        lldiv_t res = lldiv(T0, T1);
250
        env->LO = (uint64_t)res.quot;
251
        env->HI = (uint64_t)res.rem;
252
    }
253
}
254
#endif
255

    
256
#if defined(CONFIG_USER_ONLY) 
257
void do_mfc0_random (void)
258
{
259
    cpu_abort(env, "mfc0 random\n");
260
}
261

    
262
void do_mfc0_count (void)
263
{
264
    cpu_abort(env, "mfc0 count\n");
265
}
266

    
267
void cpu_mips_store_count(CPUState *env, uint32_t value)
268
{
269
    cpu_abort(env, "mtc0 count\n");
270
}
271

    
272
void cpu_mips_store_compare(CPUState *env, uint32_t value)
273
{
274
    cpu_abort(env, "mtc0 compare\n");
275
}
276

    
277
void cpu_mips_update_irq(CPUState *env)
278
{
279
    cpu_abort(env, "mtc0 status / mtc0 cause\n");
280
}
281

    
282
void do_mtc0_status_debug(uint32_t old, uint32_t val)
283
{
284
    cpu_abort(env, "mtc0 status debug\n");
285
}
286

    
287
void do_mtc0_status_irqraise_debug (void)
288
{
289
    cpu_abort(env, "mtc0 status irqraise debug\n");
290
}
291

    
292
void do_tlbwi (void)
293
{
294
    cpu_abort(env, "tlbwi\n");
295
}
296

    
297
void do_tlbwr (void)
298
{
299
    cpu_abort(env, "tlbwr\n");
300
}
301

    
302
void do_tlbp (void)
303
{
304
    cpu_abort(env, "tlbp\n");
305
}
306

    
307
void do_tlbr (void)
308
{
309
    cpu_abort(env, "tlbr\n");
310
}
311

    
312
void cpu_mips_tlb_flush (CPUState *env, int flush_global)
313
{
314
    cpu_abort(env, "mips_tlb_flush\n");
315
}
316

    
317
#else
318

    
319
/* CP0 helpers */
320
void do_mfc0_random (void)
321
{
322
    T0 = (int32_t)cpu_mips_get_random(env);
323
}
324

    
325
void do_mfc0_count (void)
326
{
327
    T0 = (int32_t)cpu_mips_get_count(env);
328
}
329

    
330
void do_mtc0_status_debug(uint32_t old, uint32_t val)
331
{
332
    fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
333
            old, old & env->CP0_Cause & CP0Ca_IP_mask,
334
            val, val & env->CP0_Cause & CP0Ca_IP_mask,
335
            env->CP0_Cause);
336
    (env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
337
                                  : fputs("\n", logfile);
338
}
339

    
340
void do_mtc0_status_irqraise_debug(void)
341
{
342
    fprintf(logfile, "Raise pending IRQs\n");
343
}
344

    
345
void fpu_handle_exception(void)
346
{
347
#ifdef CONFIG_SOFTFLOAT
348
    int flags = get_float_exception_flags(&env->fp_status);
349
    unsigned int cpuflags = 0, enable, cause = 0;
350

    
351
    enable = GET_FP_ENABLE(env->fcr31);
352

    
353
    /* determine current flags */   
354
    if (flags & float_flag_invalid) {
355
        cpuflags |= FP_INVALID;
356
        cause |= FP_INVALID & enable;
357
    }
358
    if (flags & float_flag_divbyzero) {
359
        cpuflags |= FP_DIV0;    
360
        cause |= FP_DIV0 & enable;
361
    }
362
    if (flags & float_flag_overflow) {
363
        cpuflags |= FP_OVERFLOW;    
364
        cause |= FP_OVERFLOW & enable;
365
    }
366
    if (flags & float_flag_underflow) {
367
        cpuflags |= FP_UNDERFLOW;   
368
        cause |= FP_UNDERFLOW & enable;
369
    }
370
    if (flags & float_flag_inexact) {
371
        cpuflags |= FP_INEXACT; 
372
        cause |= FP_INEXACT & enable;
373
    }
374
    SET_FP_FLAGS(env->fcr31, cpuflags);
375
    SET_FP_CAUSE(env->fcr31, cause);
376
#else
377
    SET_FP_FLAGS(env->fcr31, 0);
378
    SET_FP_CAUSE(env->fcr31, 0);
379
#endif
380
}
381

    
382
/* TLB management */
383
#if defined(MIPS_USES_R4K_TLB)
384
void cpu_mips_tlb_flush (CPUState *env, int flush_global)
385
{
386
    /* Flush qemu's TLB and discard all shadowed entries.  */
387
    tlb_flush (env, flush_global);
388
    env->tlb_in_use = MIPS_TLB_NB;
389
}
390

    
391
static void mips_tlb_flush_extra (CPUState *env, int first)
392
{
393
    /* Discard entries from env->tlb[first] onwards.  */
394
    while (env->tlb_in_use > first) {
395
        invalidate_tlb(env, --env->tlb_in_use, 0);
396
    }
397
}
398

    
399
static void fill_tlb (int idx)
400
{
401
    tlb_t *tlb;
402

    
403
    /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
404
    tlb = &env->tlb[idx];
405
    tlb->VPN = env->CP0_EntryHi & ~(target_ulong)0x1FFF;
406
    tlb->ASID = env->CP0_EntryHi & 0xFF;
407
    tlb->PageMask = env->CP0_PageMask;
408
    tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
409
    tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
410
    tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
411
    tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
412
    tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
413
    tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
414
    tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
415
    tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
416
    tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
417
}
418

    
419
void do_tlbwi (void)
420
{
421
    /* Discard cached TLB entries.  We could avoid doing this if the
422
       tlbwi is just upgrading access permissions on the current entry;
423
       that might be a further win.  */
424
    mips_tlb_flush_extra (env, MIPS_TLB_NB);
425

    
426
    /* Wildly undefined effects for CP0_Index containing a too high value and
427
       MIPS_TLB_NB not being a power of two.  But so does real silicon.  */
428
    invalidate_tlb(env, env->CP0_Index & (MIPS_TLB_NB - 1), 0);
429
    fill_tlb(env->CP0_Index & (MIPS_TLB_NB - 1));
430
}
431

    
432
void do_tlbwr (void)
433
{
434
    int r = cpu_mips_get_random(env);
435

    
436
    invalidate_tlb(env, r, 1);
437
    fill_tlb(r);
438
}
439

    
440
void do_tlbp (void)
441
{
442
    tlb_t *tlb;
443
    target_ulong tag;
444
    uint8_t ASID;
445
    int i;
446

    
447
    tag = env->CP0_EntryHi & (int32_t)0xFFFFE000;
448
    ASID = env->CP0_EntryHi & 0xFF;
449
    for (i = 0; i < MIPS_TLB_NB; i++) {
450
        tlb = &env->tlb[i];
451
        /* Check ASID, virtual page number & size */
452
        if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
453
            /* TLB match */
454
            env->CP0_Index = i;
455
            break;
456
        }
457
    }
458
    if (i == MIPS_TLB_NB) {
459
        /* No match.  Discard any shadow entries, if any of them match.  */
460
        for (i = MIPS_TLB_NB; i < env->tlb_in_use; i++) {
461
            tlb = &env->tlb[i];
462

    
463
            /* Check ASID, virtual page number & size */
464
            if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
465
                mips_tlb_flush_extra (env, i);
466
                break;
467
            }
468
        }
469

    
470
        env->CP0_Index |= 0x80000000;
471
    }
472
}
473

    
474
void do_tlbr (void)
475
{
476
    tlb_t *tlb;
477
    uint8_t ASID;
478

    
479
    ASID = env->CP0_EntryHi & 0xFF;
480
    tlb = &env->tlb[env->CP0_Index & (MIPS_TLB_NB - 1)];
481

    
482
    /* If this will change the current ASID, flush qemu's TLB.  */
483
    if (ASID != tlb->ASID)
484
        cpu_mips_tlb_flush (env, 1);
485

    
486
    mips_tlb_flush_extra(env, MIPS_TLB_NB);
487

    
488
    env->CP0_EntryHi = tlb->VPN | tlb->ASID;
489
    env->CP0_PageMask = tlb->PageMask;
490
    env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
491
                        (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
492
    env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
493
                        (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
494
}
495
#endif
496

    
497
#endif /* !CONFIG_USER_ONLY */
498

    
499
void dump_ldst (const unsigned char *func)
500
{
501
    if (loglevel)
502
        fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
503
}
504

    
505
void dump_sc (void)
506
{
507
    if (loglevel) {
508
        fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
509
                T1, T0, env->CP0_LLAddr);
510
    }
511
}
512

    
513
void debug_pre_eret (void)
514
{
515
    fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
516
            env->PC, env->CP0_EPC);
517
    if (env->CP0_Status & (1 << CP0St_ERL))
518
        fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
519
    if (env->hflags & MIPS_HFLAG_DM)
520
        fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
521
    fputs("\n", logfile);
522
}
523

    
524
void debug_post_eret (void)
525
{
526
    fprintf(logfile, "  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
527
            env->PC, env->CP0_EPC);
528
    if (env->CP0_Status & (1 << CP0St_ERL))
529
        fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
530
    if (env->hflags & MIPS_HFLAG_DM)
531
        fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
532
    if (env->hflags & MIPS_HFLAG_UM)
533
        fputs(", UM\n", logfile);
534
    else
535
        fputs("\n", logfile);
536
}
537

    
538
void do_pmon (int function)
539
{
540
    function /= 2;
541
    switch (function) {
542
    case 2: /* TODO: char inbyte(int waitflag); */
543
        if (env->gpr[4] == 0)
544
            env->gpr[2] = -1;
545
        /* Fall through */
546
    case 11: /* TODO: char inbyte (void); */
547
        env->gpr[2] = -1;
548
        break;
549
    case 3:
550
    case 12:
551
        printf("%c", (char)(env->gpr[4] & 0xFF));
552
        break;
553
    case 17:
554
        break;
555
    case 158:
556
        {
557
            unsigned char *fmt = (void *)(unsigned long)env->gpr[4];
558
            printf("%s", fmt);
559
        }
560
        break;
561
    }
562
}
563

    
564
#if !defined(CONFIG_USER_ONLY) 
565

    
566
static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
567

    
568
#define MMUSUFFIX _mmu
569
#define ALIGNED_ONLY
570

    
571
#define SHIFT 0
572
#include "softmmu_template.h"
573

    
574
#define SHIFT 1
575
#include "softmmu_template.h"
576

    
577
#define SHIFT 2
578
#include "softmmu_template.h"
579

    
580
#define SHIFT 3
581
#include "softmmu_template.h"
582

    
583
static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
584
{
585
    env->CP0_BadVAddr = addr;
586
    do_restore_state (retaddr);
587
    do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
588
}
589

    
590
void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
591
{
592
    TranslationBlock *tb;
593
    CPUState *saved_env;
594
    unsigned long pc;
595
    int ret;
596

    
597
    /* XXX: hack to restore env in all cases, even if not called from
598
       generated code */
599
    saved_env = env;
600
    env = cpu_single_env;
601
    ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
602
    if (ret) {
603
        if (retaddr) {
604
            /* now we have a real cpu fault */
605
            pc = (unsigned long)retaddr;
606
            tb = tb_find_pc(pc);
607
            if (tb) {
608
                /* the PC is inside the translated code. It means that we have
609
                   a virtual CPU fault */
610
                cpu_restore_state(tb, env, pc, NULL);
611
            }
612
        }
613
        do_raise_exception_err(env->exception_index, env->error_code);
614
    }
615
    env = saved_env;
616
}
617

    
618
#endif