Revision 75554a3c hw/omap1.c

b/hw/omap1.c
1983 1983
    SerialState *serial; /* TODO */
1984 1984
    struct omap_target_agent_s *ta;
1985 1985
    target_phys_addr_t base;
1986
    omap_clk fclk;
1987
    qemu_irq irq;
1986 1988

  
1987 1989
    uint8_t eblr;
1988 1990
    uint8_t syscontrol;
......
2007 2009
    struct omap_uart_s *s = (struct omap_uart_s *)
2008 2010
            qemu_mallocz(sizeof(struct omap_uart_s));
2009 2011

  
2012
    s->base = base;
2013
    s->fclk = fclk;
2014
    s->irq = irq;
2010 2015
    s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
2011 2016
                               chr ?: qemu_chr_open("null"), 1);
2012 2017

  
......
2108 2113
                    omap_uart_writefn, s);
2109 2114

  
2110 2115
    s->ta = ta;
2111
    s->base = base;
2112 2116

  
2113 2117
    cpu_register_physical_memory(s->base + 0x20, 0x100, iomemtype);
2114 2118

  
2115 2119
    return s;
2116 2120
}
2117 2121

  
2122
void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
2123
{
2124
    /* TODO: Should reuse or destroy current s->serial */
2125
    s->serial = serial_mm_init(s->base, 2, s->irq,
2126
                    omap_clk_getrate(s->fclk) / 16,
2127
                    chr ?: qemu_chr_open("null"), 1);
2128
}
2129

  
2118 2130
/* MPU Clock/Reset/Power Mode Control */
2119 2131
static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
2120 2132
{

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