Revision 76a66253

b/cpu-all.h
759 759 
void cpu_dump_state(CPUState *env, FILE *f,
760 760 
                    int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
761 761 
                    int flags);
762 
void cpu_dump_statistics (CPUState *env, FILE *f,
763 
                          int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
764 
                          int flags);
762 765 

  		





  763
  766
  
    
void cpu_abort(CPUState *env, const char *fmt, ...);


  		





  764
  767
  
    
extern CPUState *first_cpu;


  		












  

    
      b/gdbstub.c
    
  






  307
  307
  
    
    registers[98] = tswapl(tmp);


  		





  308
  308
  
    
    registers[99] = tswapl(env->lr);


  		





  309
  309
  
    
    registers[100] = tswapl(env->ctr);


  		





  310
  
  
    
    registers[101] = tswapl(do_load_xer(env));


  		





  
  310
  
    
    registers[101] = tswapl(ppc_load_xer(env));


  		





  311
  311
  
    
    registers[102] = 0;


  		





  312
  312
  
    

  		





  313
  313
  
    
    return 103 * 4;


  		





  ......




  335
  335
  
    
        env->crf[i] = (registers[98] >> (32 - ((i + 1) * 4))) & 0xF;


  		





  336
  336
  
    
    env->lr = tswapl(registers[99]);


  		





  337
  337
  
    
    env->ctr = tswapl(registers[100]);


  		





  338
  
  
    
    do_store_xer(env, tswapl(registers[101]));


  		





  
  338
  
    
    ppc_store_xer(env, tswapl(registers[101]));


  		





  339
  339
  
    
}


  		





  340
  340
  
    
#elif defined (TARGET_SPARC)


  		





  341
  341
  
    
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)


  		












  

    
      b/hw/ppc.c
    
  






  1
  1
  
    
/*


  		





  2
  2
  
    
 * QEMU generic PPC hardware System Emulator


  		





  3
  3
  
    
 * 


  		





  4
  
  
    
 * Copyright (c) 2003-2004 Jocelyn Mayer


  		





  
  4
  
    
 * Copyright (c) 2003-2007 Jocelyn Mayer


  		





  5
  5
  
    
 * 


  		





  6
  6
  
    
 * Permission is hereby granted, free of charge, to any person obtaining a copy


  		





  7
  7
  
    
 * of this software and associated documentation files (the "Software"), to deal


  		





  ......




  41
  41
  
    
{


  		





  42
  42
  
    
    /* TB time in tb periods */


  		





  43
  43
  
    
    return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,


  		





  44
  
  
    
		    tb_env->tb_freq, ticks_per_sec);


  		





  
  44
  
    
                    tb_env->tb_freq, ticks_per_sec);


  		





  45
  45
  
    
}


  		





  46
  46
  
    

  		





  47
  47
  
    
uint32_t cpu_ppc_load_tbl (CPUState *env)


  		





  ......




  52
  52
  
    
    tb = cpu_ppc_get_tb(tb_env);


  		





  53
  53
  
    
#ifdef DEBUG_TB


  		





  54
  54
  
    
    {


  		





  55
  
  
    
         static int last_time;


  		





  56
  
  
    
	 int now;


  		





  57
  
  
    
	 now = time(NULL);


  		





  58
  
  
    
	 if (last_time != now) {


  		





  59
  
  
    
	     last_time = now;


  		





  60
  
  
    
	     printf("%s: tb=0x%016lx %d %08lx\n",


  		





  61
  
  
    
                    __func__, tb, now, tb_env->tb_offset);


  		





  62
  
  
    
	 }


  		





  
  55
  
    
        static int last_time;


  		





  
  56
  
    
        int now;


  		





  
  57
  
    
        now = time(NULL);


  		





  
  58
  
    
        if (last_time != now) {


  		





  
  59
  
    
            last_time = now;


  		





  
  60
  
    
            printf("%s: tb=0x%016lx %d %08lx\n",


  		





  
  61
  
    
                   __func__, tb, now, tb_env->tb_offset);


  		





  
  62
  
    
        }


  		





  63
  63
  
    
    }


  		





  64
  64
  
    
#endif


  		





  65
  65
  
    

  		





  ......




  75
  75
  
    
#ifdef DEBUG_TB


  		





  76
  76
  
    
    printf("%s: tb=0x%016lx\n", __func__, tb);


  		





  77
  77
  
    
#endif


  		





  
  78
  
    

  		





  78
  79
  
    
    return tb >> 32;


  		





  79
  80
  
    
}


  		





  80
  81
  
    

  		





  ......




  117
  118
  
    
#if defined(DEBUG_TB)


  		





  118
  119
  
    
    printf("%s: 0x%08x\n", __func__, decr);


  		





  119
  120
  
    
#endif


  		





  
  121
  
    

  		





  120
  122
  
    
    return decr;


  		





  121
  123
  
    
}


  		





  122
  124
  
    

  		





  ......




  146
  148
  
    
    if (is_excp)


  		





  147
  149
  
    
        next += tb_env->decr_next - now;


  		





  148
  150
  
    
    if (next == now)


  		





  149
  
  
    
	next++;


  		





  
  151
  
    
        next++;


  		





  150
  152
  
    
    tb_env->decr_next = next;


  		





  151
  153
  
    
    /* Adjust timer */


  		





  152
  154
  
    
    qemu_mod_timer(tb_env->decr_timer, next);


  		





  ......




  154
  156
  
    
     * raise an exception.


  		





  155
  157
  
    
     */


  		





  156
  158
  
    
    if ((value & 0x80000000) && !(decr & 0x80000000))


  		





  157
  
  
    
	cpu_ppc_decr_excp(env);


  		





  
  159
  
    
        cpu_ppc_decr_excp(env);


  		





  158
  160
  
    
}


  		





  159
  161
  
    

  		





  160
  162
  
    
void cpu_ppc_store_decr (CPUState *env, uint32_t value)


  		





  ......




  177
  179
  
    
        return NULL;


  		





  178
  180
  
    
    env->tb_env = tb_env;


  		





  179
  181
  
    
    if (tb_env->tb_freq == 0 || 1) {


  		





  180
  
  
    
	tb_env->tb_freq = freq;


  		





  181
  
  
    
	/* Create new timer */


  		





  182
  
  
    
	tb_env->decr_timer =


  		





  
  182
  
    
        tb_env->tb_freq = freq;


  		





  
  183
  
    
        /* Create new timer */


  		





  
  184
  
    
        tb_env->decr_timer =


  		





  183
  185
  
    
            qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);


  		





  184
  
  
    
	/* There is a bug in  2.4 kernels:


  		





  185
  
  
    
	 * if a decrementer exception is pending when it enables msr_ee,


  		





  186
  
  
    
	 * it's not ready to handle it...


  		





  187
  
  
    
	 */


  		





  188
  
  
    
	_cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);


  		





  
  186
  
    
        /* There is a bug in Linux 2.4 kernels:


  		





  
  187
  
    
         * if a decrementer exception is pending when it enables msr_ee,


  		





  
  188
  
    
         * it's not ready to handle it...


  		





  
  189
  
    
         */


  		





  
  190
  
    
        _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);


  		





  189
  191
  
    
    }


  		





  190
  192
  
    

  		





  191
  193
  
    
    return tb_env;


  		





  192
  194
  
    
}


  		





  193
  195
  
    

  		





  
  196
  
    
/* Specific helpers for POWER & PowerPC 601 RTC */


  		





  
  197
  
    
ppc_tb_t *cpu_ppc601_rtc_init (CPUState *env)


  		





  
  198
  
    
{


  		





  
  199
  
    
    return cpu_ppc_tb_init(env, 7812500);


  		





  
  200
  
    
}


  		





  
  201
  
    

  		





  
  202
  
    
void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)


  		





  
  203
  
    
__attribute__ (( alias ("cpu_ppc_store_tbu") ));


  		





  
  204
  
    

  		





  
  205
  
    
uint32_t cpu_ppc601_load_rtcu (CPUState *env)


  		





  
  206
  
    
__attribute__ (( alias ("cpu_ppc_load_tbu") ));


  		





  
  207
  
    

  		





  
  208
  
    
void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)


  		





  
  209
  
    
{


  		





  
  210
  
    
    cpu_ppc_store_tbl(env, value & 0x3FFFFF80);


  		





  
  211
  
    
}


  		





  
  212
  
    

  		





  
  213
  
    
uint32_t cpu_ppc601_load_rtcl (CPUState *env)


  		





  
  214
  
    
{


  		





  
  215
  
    
    return cpu_ppc_load_tbl(env) & 0x3FFFFF80;


  		





  
  216
  
    
}


  		





  
  217
  
    

  		





  
  218
  
    
/* Embedded PowerPC timers */


  		





  
  219
  
    
target_ulong load_40x_pit (CPUState *env)


  		





  
  220
  
    
{


  		





  
  221
  
    
    /* XXX: TODO */


  		





  
  222
  
    
    return 0;


  		





  
  223
  
    
}


  		





  
  224
  
    

  		





  
  225
  
    
void store_40x_pit (CPUState *env, target_ulong val)


  		





  
  226
  
    
{


  		





  
  227
  
    
    /* XXX: TODO */


  		





  
  228
  
    
}


  		





  
  229
  
    

  		





  
  230
  
    
void store_booke_tcr (CPUState *env, target_ulong val)


  		





  
  231
  
    
{


  		





  
  232
  
    
    /* XXX: TODO */


  		





  
  233
  
    
}


  		





  
  234
  
    

  		





  
  235
  
    
void store_booke_tsr (CPUState *env, target_ulong val)


  		





  
  236
  
    
{


  		





  
  237
  
    
    /* XXX: TODO */


  		





  
  238
  
    
}


  		





  
  239
  
    

  		





  194
  240
  
    
#if 0


  		





  195
  241
  
    
/*****************************************************************************/


  		





  196
  242
  
    
/* Handle system reset (for now, just stop emulation) */


  		





  ......




  264
  310
  
    
    tmp |= m48t59_read(nvram, addr + 1) << 16;


  		





  265
  311
  
    
    tmp |= m48t59_read(nvram, addr + 2) << 8;


  		





  266
  312
  
    
    tmp |= m48t59_read(nvram, addr + 3);


  		





  
  313
  
    

  		





  267
  314
  
    
    return tmp;


  		





  268
  315
  
    
}


  		





  269
  316
  
    

  		





  ......




  316
  363
  
    
    odd = count & 1;


  		





  317
  364
  
    
    count &= ~1;


  		





  318
  365
  
    
    for (i = 0; i != count; i++) {


  		





  319
  
  
    
	crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));


  		





  
  366
  
    
        crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));


  		





  320
  367
  
    
    }


  		





  321
  368
  
    
    if (odd) {


  		





  322
  
  
    
	crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);


  		





  
  369
  
    
        crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);


  		





  323
  370
  
    
    }


  		





  324
  371
  
    

  		





  325
  372
  
    
    return crc;


  		












  

    
      b/linux-user/main.c
    
  






  670
  670
  
    
{


  		





  671
  671
  
    
    cpu_ppc_store_tb(env, ((uint64_t)cpu_ppc_load_tbl(env) << 32) | value);


  		





  672
  672
  
    
}


  		





  673
  
  
    
  


  		





  674
  
  
    
uint32_t cpu_ppc_load_decr (CPUState *env)


  		





  
  673
  
    

  		





  
  674
  
    
void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)


  		





  
  675
  
    
__attribute__ (( alias ("cpu_ppc_store_tbu") ));


  		





  
  676
  
    

  		





  
  677
  
    
uint32_t cpu_ppc601_load_rtcu (CPUState *env)


  		





  
  678
  
    
__attribute__ (( alias ("cpu_ppc_load_tbu") ));


  		





  
  679
  
    

  		





  
  680
  
    
void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)


  		





  675
  681
  
    
{


  		





  676
  
  
    
    /* TO FIX */


  		





  677
  
  
    
    return -1;


  		





  
  682
  
    
    cpu_ppc_store_tbl(env, value & 0x3FFFFF80);


  		





  678
  683
  
    
}


  		





  679
  
  
    
 


  		





  680
  
  
    
void cpu_ppc_store_decr (CPUState *env, uint32_t value)


  		





  
  684
  
    

  		





  
  685
  
    
uint32_t cpu_ppc601_load_rtcl (CPUState *env)


  		





  681
  686
  
    
{


  		





  682
  
  
    
    /* TO FIX */


  		





  
  687
  
    
    return cpu_ppc_load_tbl(env) & 0x3FFFFF80;


  		





  683
  688
  
    
}


  		





  684
  
  
    
 


  		





  
  689
  
    

  		





  685
  690
  
    
void cpu_loop(CPUPPCState *env)


  		





  686
  691
  
    
{


  		





  687
  692
  
    
    target_siginfo_t info;


  		












  

    
      b/monitor.c
    
  






  331
  331
  
    
    }


  		





  332
  332
  
    
}


  		





  333
  333
  
    

  		





  
  334
  
    
#if defined(TARGET_PPC)


  		





  
  335
  
    
/* XXX: not implemented in other targets */


  		





  
  336
  
    
static void do_info_cpu_stats (void)


  		





  
  337
  
    
{


  		





  
  338
  
    
    CPUState *env;


  		





  
  339
  
    

  		





  
  340
  
    
    env = mon_get_cpu();


  		





  
  341
  
    
    cpu_dump_statistics(env, NULL, &monitor_fprintf, 0);


  		





  
  342
  
    
}


  		





  
  343
  
    
#endif


  		





  
  344
  
    

  		





  334
  345
  
    
static void do_quit(void)


  		





  335
  346
  
    
{


  		





  336
  347
  
    
    exit(0);


  		





  ......




  1303
  1314
  
    
      "", "show which guest mouse is receiving events" },


  		





  1304
  1315
  
    
    { "vnc", "", do_info_vnc,


  		





  1305
  1316
  
    
      "", "show the vnc server status"},


  		





  
  1317
  
    
#if defined(TARGET_PPC)


  		





  
  1318
  
    
    { "cpustats", "", do_info_cpu_stats,


  		





  
  1319
  
    
      "", "show CPU statistics", },


  		





  
  1320
  
    
#endif


  		





  1306
  1321
  
    
    { NULL, NULL, },


  		





  1307
  1322
  
    
};


  		





  1308
  1323
  
    

  		












  

    
      b/target-ppc/STATUS
    
  






  
  1
  
    
PowerPC emulation status.


  		





  
  2
  
    
The goal of this file is to provide a reference status to avoid regressions.


  		





  
  3
  
    

  		





  
  4
  
    
===============================================================================


  		





  
  5
  
    
PowerPC core emulation status


  		





  
  6
  
    

  		





  
  7
  
    
PowerPC CPU known to work (ie booting at least Linux 2.4):


  		





  
  8
  
    
* main stream PowerPC cores


  		





  
  9
  
    
- PowerPC 603 & derivatives


  		





  
  10
  
    
- PowerPC 604 & derivatives


  		





  
  11
  
    
- PowerPC 740 & derivatives


  		





  
  12
  
    
- PowerPC 750 & derivatives


  		





  
  13
  
    

  		





  
  14
  
    
PowerPC that should work but are not supported by standard Linux kernel


  		





  
  15
  
    
(then remain mostly untested)


  		





  
  16
  
    
- PowerPC 745


  		





  
  17
  
    
- PowerPC 755


  		





  
  18
  
    

  		





  
  19
  
    
Work in progress:


  		





  
  20
  
    
* embedded PowerPC cores


  		





  
  21
  
    
- PowerPC 405


  		





  
  22
  
    
- BookE PowerPC


  		





  
  23
  
    
- e500 core (Freescale PowerQUICC)


  		





  
  24
  
    
* main stream PowerPC cores


  		





  
  25
  
    
- PowerPC 601


  		





  
  26
  
    
- PowerPC 602


  		





  
  27
  
    

  		





  
  28
  
    
TODO:


  		





  
  29
  
    
* embedded PowerPC cores


  		





  
  30
  
    
- PowerPC 401


  		





  
  31
  
    
- PowerPC 403


  		





  
  32
  
    
- PowerPC 440


  		





  
  33
  
    
- PowerPC 460


  		





  
  34
  
    
* main stream PowerPC cores


  		





  
  35
  
    
- PowerPC 7400 (aka G4)


  		





  
  36
  
    
- PowerPC 7410


  		





  
  37
  
    
- PowerPC 7450


  		





  
  38
  
    
- PowerPC 7455


  		





  
  39
  
    
- PowerPC 7457


  		





  
  40
  
    
- PowerPC 7457A


  		





  
  41
  
    
* original POWER


  		





  
  42
  
    
- POWER


  		





  
  43
  
    
- POWER2


  		





  
  44
  
    
* 64 bits PowerPC cores


  		





  
  45
  
    
- PowerPC 620


  		





  
  46
  
    
- PowerPC 630 (aka POWER3)


  		





  
  47
  
    
- PowerPC 631 (aka POWER3+)


  		





  
  48
  
    
- POWER4


  		





  
  49
  
    
- POWER4+


  		





  
  50
  
    
- POWER5


  		





  
  51
  
    
- POWER5+


  		





  
  52
  
    
- PowerPC 970


  		





  
  53
  
    
* RS64 series


  		





  
  54
  
    
- RS64


  		





  
  55
  
    
- RS64-II


  		





  
  56
  
    
- RS64-III


  		





  
  57
  
    
- RS64-IV


  		





  
  58
  
    

  		





  
  59
  
    
===============================================================================


  		





  
  60
  
    
PowerPC microcontrollers emulation status


  		





  
  61
  
    

  		





  
  62
  
    
TODO:


  		





  
  63
  
    
- PowerPC 40x microcontrollers emulation


  		





  
  64
  
    
- PowerQUICC microcontrollers emulation


  		





  
  65
  
    

  		





  
  66
  
    
===============================================================================


  		





  
  67
  
    
PowerPC based platforms emulation status


  		





  
  68
  
    

  		





  
  69
  
    
* PREP platform (RS/6000 7043...) - TO BE CHECKED (broken)


  		





  
  70
  
    
- Gentoo Linux live CDROM 1.4


  		





  
  71
  
    
- Debian Linux 3.0


  		





  
  72
  
    
- Mandrake Linux 9


  		





  
  73
  
    

  		





  
  74
  
    
* heathrow PowerMac platform (beige PowerMac) - TO BE CHECKED (broken)


  		





  
  75
  
    
- Gentoo Linux live CDROM 1.4


  		





  
  76
  
    
- Debian Linux 3.0


  		





  
  77
  
    
- Mandrake Linux 9


  		





  
  78
  
    

  		





  
  79
  
    
* mac99 platform (white and blue PowerMac, ...)


  		





  
  80
  
    
- Gentoo Linux live CDROM 1.4 - boots, compiles linux kernel


  		





  
  81
  
    
- Debian Linux woody - boots from CDROM and HDD


  		





  
  82
  
    
- Mandrake Linux 9 - boots from CDROM, freezes during install


  		





  
  83
  
    

  		





  
  84
  
    
TODO:


  		





  
  85
  
    
- MCA based RS/6000 emulation


  		





  
  86
  
    
- CHRP emulation (not PowerMac)


  		





  
  87
  
    
- PPAR emulation


  		





  
  88
  
    
- misc PowerPC reference boards emulation


  		





  
  89
  
    

  		





  
  90
  
    
===============================================================================


  		





  
  91
  
    
(to be completed)


  		












  

    
      b/target-ppc/cpu.h
    
  






  1
  1
  
    
/*


  		





  2
  2
  
    
 *  PowerPC emulation cpu definitions for qemu.


  		





  3
  3
  
    
 * 


  		





  4
  
  
    
 *  Copyright (c) 2003-2005 Jocelyn Mayer


  		





  
  4
  
    
 *  Copyright (c) 2003-2007 Jocelyn Mayer


  		





  5
  5
  
    
 *


  		





  6
  6
  
    
 * This library is free software; you can redistribute it and/or


  		





  7
  7
  
    
 * modify it under the terms of the GNU Lesser General Public


  		





  ......




  21
  21
  
    
#define __CPU_PPC_H__


  		





  22
  22
  
    

  		





  23
  23
  
    
#include "config.h"


  		





  
  24
  
    
#include <stdint.h>


  		





  24
  25
  
    

  		





  
  26
  
    
#if defined (TARGET_PPC64)


  		





  
  27
  
    
typedef uint64_t ppc_gpr_t;


  		





  
  28
  
    
#define TARGET_LONG_BITS 64


  		





  
  29
  
    
#define REGX "%016" PRIx64


  		





  
  30
  
    
#elif defined(TARGET_E500)


  		





  
  31
  
    
/* GPR are 64 bits: used by vector extension */


  		





  
  32
  
    
typedef uint64_t ppc_gpr_t;


  		





  25
  33
  
    
#define TARGET_LONG_BITS 32


  		





  
  34
  
    
#define REGX "%08" PRIx32


  		





  
  35
  
    
#else


  		





  
  36
  
    
typedef uint32_t ppc_gpr_t;


  		





  
  37
  
    
#define TARGET_LONG_BITS 32


  		





  
  38
  
    
#define REGX "%08" PRIx32


  		





  
  39
  
    
#endif


  		





  26
  40
  
    

  		





  27
  41
  
    
#include "cpu-defs.h"


  		





  28
  42
  
    

  		





  ......




  32
  46
  
    

  		





  33
  47
  
    
#define TARGET_HAS_ICE 1


  		





  34
  48
  
    

  		





  35
  
  
    
#define ELF_MACHINE	EM_PPC


  		





  
  49
  
    
#if defined (TARGET_PPC64)


  		





  
  50
  
    
#define ELF_MACHINE     EM_PPC64


  		





  
  51
  
    
#else


  		





  
  52
  
    
#define ELF_MACHINE     EM_PPC


  		





  
  53
  
    
#endif


  		





  36
  54
  
    

  		





  37
  55
  
    
/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC


  		





  38
  56
  
    
 *                              have different cache line sizes


  		





  ......




  42
  60
  
    

  		





  43
  61
  
    
/* XXX: put this in a common place */


  		





  44
  62
  
    
#define likely(x)   __builtin_expect(!!(x), 1)


  		





  
  63
  
    
#define unlikely(x) __builtin_expect(!!(x), 0)


  		





  45
  64
  
    

  		





  46
  65
  
    
/*****************************************************************************/


  		





  47
  66
  
    
/* PVR definitions for most known PowerPC */


  		





  ......




  54
  73
  
    
    CPU_PPC_401E2     = 0x00250000,


  		





  55
  74
  
    
    CPU_PPC_401F2     = 0x00260000,


  		





  56
  75
  
    
    CPU_PPC_401G2     = 0x00270000,


  		





  57
  
  
    
    CPU_PPC_IOP480    = 0x40100000,


  		





  
  76
  
    
#define CPU_PPC_401 CPU_PPC_401G2


  		





  
  77
  
    
    CPU_PPC_IOP480    = 0x40100000, /* 401B2 ? */


  		





  
  78
  
    
    CPU_PPC_COBRA     = 0x10100000, /* IBM Processor for Network Resources */


  		





  58
  79
  
    
    /* PowerPC 403 cores */


  		





  59
  
  
    
    CPU_PPC_403GA     = 0x00200000,


  		





  
  80
  
    
    CPU_PPC_403GA     = 0x00200011,


  		





  60
  81
  
    
    CPU_PPC_403GB     = 0x00200100,


  		





  61
  82
  
    
    CPU_PPC_403GC     = 0x00200200,


  		





  62
  83
  
    
    CPU_PPC_403GCX    = 0x00201400,


  		





  
  84
  
    
#define CPU_PPC_403 CPU_PPC_403GCX


  		





  63
  85
  
    
    /* PowerPC 405 cores */


  		





  64
  
  
    
    CPU_PPC_405       = 0x40110000,


  		





  65
  
  
    
    CPU_PPC_405EP     = 0x51210000,


  		





  66
  
  
    
    CPU_PPC_405GPR    = 0x50910000,


  		





  
  86
  
    
    CPU_PPC_405CR     = 0x40110145,


  		





  
  87
  
    
#define CPU_PPC_405GP CPU_PPC_405CR


  		





  
  88
  
    
    CPU_PPC_405EP     = 0x51210950,


  		





  
  89
  
    
    CPU_PPC_405GPR    = 0x50910951,


  		





  67
  90
  
    
    CPU_PPC_405D2     = 0x20010000,


  		





  68
  91
  
    
    CPU_PPC_405D4     = 0x41810000,


  		





  69
  
  
    
    CPU_PPC_NPE405H   = 0x41410000,


  		





  70
  
  
    
    CPU_PPC_NPE405L   = 0x41610000,


  		





  
  92
  
    
#define CPU_PPC_405 CPU_PPC_405D4


  		





  
  93
  
    
    CPU_PPC_NPE405H   = 0x414100C0,


  		





  
  94
  
    
    CPU_PPC_NPE405H2  = 0x41410140,


  		





  
  95
  
    
    CPU_PPC_NPE405L   = 0x416100C0,


  		





  
  96
  
    
    /* XXX: missing 405LP, LC77700 */


  		





  
  97
  
    
    /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */


  		





  
  98
  
    
#if 0


  		





  
  99
  
    
    CPU_PPC_STB01000  = xxx,


  		





  
  100
  
    
#endif


  		





  71
  101
  
    
#if 0


  		





  72
  
  
    
    CPU_PPC_STB02     = xxx,


  		





  
  102
  
    
    CPU_PPC_STB01010  = xxx,


  		





  
  103
  
    
#endif


  		





  
  104
  
    
#if 0


  		





  
  105
  
    
    CPU_PPC_STB0210   = xxx,


  		





  73
  106
  
    
#endif


  		





  74
  107
  
    
    CPU_PPC_STB03     = 0x40310000,


  		





  75
  108
  
    
#if 0


  		





  76
  
  
    
    CPU_PPC_STB04     = xxx,


  		





  
  109
  
    
    CPU_PPC_STB043    = xxx,


  		





  77
  110
  
    
#endif


  		





  78
  
  
    
    CPU_PPC_STB25     = 0x51510000,


  		





  
  111
  
    
#if 0


  		





  
  112
  
    
    CPU_PPC_STB045    = xxx,


  		





  
  113
  
    
#endif


  		





  
  114
  
    
    CPU_PPC_STB25     = 0x51510950,


  		





  79
  115
  
    
#if 0


  		





  80
  116
  
    
    CPU_PPC_STB130    = xxx,


  		





  81
  117
  
    
#endif


  		





  
  118
  
    
    /* Xilinx cores */


  		





  
  119
  
    
    CPU_PPC_X2VP4     = 0x20010820,


  		





  
  120
  
    
#define CPU_PPC_X2VP7 CPU_PPC_X2VP4


  		





  
  121
  
    
    CPU_PPC_X2VP20    = 0x20010860,


  		





  
  122
  
    
#define CPU_PPC_X2VP50 CPU_PPC_X2VP20


  		





  82
  123
  
    
    /* PowerPC 440 cores */


  		





  83
  
  
    
    CPU_PPC_440EP     = 0x42220000,


  		





  84
  
  
    
    CPU_PPC_440GP     = 0x40120400,


  		





  85
  
  
    
    CPU_PPC_440GX     = 0x51B20000,


  		





  86
  
  
    
    /* PowerPC MPC 8xx cores */


  		





  87
  
  
    
    CPU_PPC_8540      = 0x80200000,


  		





  
  124
  
    
    CPU_PPC_440EP     = 0x422218D3,


  		





  
  125
  
    
#define CPU_PPC_440GR CPU_PPC_440EP


  		





  
  126
  
    
    CPU_PPC_440GP     = 0x40120481,


  		





  
  127
  
    
    CPU_PPC_440GX     = 0x51B21850,


  		





  
  128
  
    
    CPU_PPC_440GXc    = 0x51B21892,


  		





  
  129
  
    
    CPU_PPC_440GXf    = 0x51B21894,


  		





  
  130
  
    
    CPU_PPC_440SP     = 0x53221850,


  		





  
  131
  
    
    CPU_PPC_440SP2    = 0x53221891,


  		





  
  132
  
    
    CPU_PPC_440SPE    = 0x53421890,


  		





  
  133
  
    
    /* XXX: missing 440GRX */


  		





  
  134
  
    
    /* PowerPC 460 cores - TODO */


  		





  
  135
  
    
    /* PowerPC MPC 5xx cores */


  		





  
  136
  
    
    CPU_PPC_5xx       = 0x00020020,


  		





  
  137
  
    
    /* PowerPC MPC 8xx cores (aka PowerQUICC) */


  		





  88
  138
  
    
    CPU_PPC_8xx       = 0x00500000,


  		





  89
  
  
    
    CPU_PPC_8240      = 0x00810100,


  		





  90
  
  
    
    CPU_PPC_8245      = 0x00811014,


  		





  
  139
  
    
    /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */


  		





  
  140
  
    
    CPU_PPC_82xx_HIP3 = 0x00810101,


  		





  
  141
  
    
    CPU_PPC_82xx_HIP4 = 0x80811014,


  		





  
  142
  
    
    CPU_PPC_827x      = 0x80822013,


  		





  
  143
  
    
    /* eCores */


  		





  
  144
  
    
    CPU_PPC_e200      = 0x81120000,


  		





  
  145
  
    
    CPU_PPC_e500v110  = 0x80200010,


  		





  
  146
  
    
    CPU_PPC_e500v120  = 0x80200020,


  		





  
  147
  
    
    CPU_PPC_e500v210  = 0x80210010,


  		





  
  148
  
    
    CPU_PPC_e500v220  = 0x80210020,


  		





  
  149
  
    
#define CPU_PPC_e500 CPU_PPC_e500v220


  		





  
  150
  
    
    CPU_PPC_e600      = 0x80040010,


  		





  91
  151
  
    
    /* PowerPC 6xx cores */


  		





  92
  
  
    
    CPU_PPC_601       = 0x00010000,


  		





  93
  
  
    
    CPU_PPC_602       = 0x00050000,


  		





  94
  
  
    
    CPU_PPC_603       = 0x00030000,


  		





  95
  
  
    
    CPU_PPC_603E      = 0x00060000,


  		





  96
  
  
    
    CPU_PPC_603EV     = 0x00070000,


  		





  97
  
  
    
    CPU_PPC_603R      = 0x00071000,


  		





  98
  
  
    
    CPU_PPC_G2        = 0x80810000,


  		





  99
  
  
    
    CPU_PPC_G2LE      = 0x80820000,


  		





  
  152
  
    
    CPU_PPC_601       = 0x00010001,


  		





  
  153
  
    
    CPU_PPC_602       = 0x00050100,


  		





  
  154
  
    
    CPU_PPC_603       = 0x00030100,


  		





  
  155
  
    
    CPU_PPC_603E      = 0x00060101,


  		





  
  156
  
    
    CPU_PPC_603P      = 0x00070000,


  		





  
  157
  
    
    CPU_PPC_603E7v    = 0x00070100,


  		





  
  158
  
    
    CPU_PPC_603E7v2   = 0x00070201,


  		





  
  159
  
    
    CPU_PPC_603E7     = 0x00070200,


  		





  
  160
  
    
    CPU_PPC_603R      = 0x00071201,


  		





  
  161
  
    
    CPU_PPC_G2        = 0x00810011,


  		





  
  162
  
    
    CPU_PPC_G2H4      = 0x80811010,


  		





  
  163
  
    
    CPU_PPC_G2gp      = 0x80821010,


  		





  
  164
  
    
    CPU_PPC_G2ls      = 0x90810010,


  		





  
  165
  
    
    CPU_PPC_G2LE      = 0x80820010,


  		





  
  166
  
    
    CPU_PPC_G2LEgp    = 0x80822010,


  		





  
  167
  
    
    CPU_PPC_G2LEls    = 0xA0822010,


  		





  100
  168
  
    
    CPU_PPC_604       = 0x00040000,


  		





  101
  
  
    
    CPU_PPC_604E      = 0x00090000,


  		





  102
  
  
    
    CPU_PPC_604R      = 0x000a0000,


  		





  
  169
  
    
    CPU_PPC_604E      = 0x00090100, /* Also 2110 & 2120 */


  		





  
  170
  
    
    CPU_PPC_604R      = 0x000a0101,


  		





  103
  171
  
    
    /* PowerPC 74x/75x cores (aka G3) */


  		





  104
  172
  
    
    CPU_PPC_74x       = 0x00080000,


  		





  105
  
  
    
    CPU_PPC_755       = 0x00083000,


  		





  
  173
  
    
    CPU_PPC_740E      = 0x00080100,


  		





  
  174
  
    
    CPU_PPC_750E      = 0x00080200,


  		





  
  175
  
    
    CPU_PPC_755_10    = 0x00083100,


  		





  
  176
  
    
    CPU_PPC_755_11    = 0x00083101,


  		





  
  177
  
    
    CPU_PPC_755_20    = 0x00083200,


  		





  
  178
  
    
    CPU_PPC_755D      = 0x00083202,


  		





  
  179
  
    
    CPU_PPC_755E      = 0x00083203,


  		





  
  180
  
    
#define CPU_PPC_755 CPU_PPC_755E


  		





  106
  181
  
    
    CPU_PPC_74xP      = 0x10080000,


  		





  107
  
  
    
    CPU_PPC_750CXE22  = 0x00082202,


  		





  
  182
  
    
    CPU_PPC_750CXE21  = 0x00082201,


  		





  
  183
  
    
    CPU_PPC_750CXE22  = 0x00082212,


  		





  
  184
  
    
    CPU_PPC_750CXE23  = 0x00082203,


  		





  108
  185
  
    
    CPU_PPC_750CXE24  = 0x00082214,


  		





  109
  186
  
    
    CPU_PPC_750CXE24b = 0x00083214,


  		





  110
  187
  
    
    CPU_PPC_750CXE31  = 0x00083211,


  		





  111
  188
  
    
    CPU_PPC_750CXE31b = 0x00083311,


  		





  112
  189
  
    
#define CPU_PPC_750CXE CPU_PPC_750CXE31b


  		





  113
  
  
    
    CPU_PPC_750FX     = 0x70000000,


  		





  114
  
  
    
    CPU_PPC_750GX     = 0x70020000,


  		





  
  190
  
    
    CPU_PPC_750CXR    = 0x00083410,


  		





  
  191
  
    
    CPU_PPC_750FX10   = 0x70000100,


  		





  
  192
  
    
    CPU_PPC_750FX20   = 0x70000200,


  		





  
  193
  
    
    CPU_PPC_750FX21   = 0x70000201,


  		





  
  194
  
    
    CPU_PPC_750FX22   = 0x70000202,


  		





  
  195
  
    
    CPU_PPC_750FX23   = 0x70000203,


  		





  
  196
  
    
#define CPU_PPC_750FX CPU_PPC_750FX23


  		





  
  197
  
    
    CPU_PPC_750FL     = 0x700A0203,


  		





  
  198
  
    
    CPU_PPC_750GX10   = 0x70020100,


  		





  
  199
  
    
    CPU_PPC_750GX11   = 0x70020101,


  		





  
  200
  
    
    CPU_PPC_750GX12   = 0x70020102,


  		





  
  201
  
    
#define CPU_PPC_750GX CPU_PPC_750GX12


  		





  
  202
  
    
    CPU_PPC_750GL     = 0x70020102,


  		





  
  203
  
    
    CPU_PPC_750L30    = 0x00088300,


  		





  
  204
  
    
    CPU_PPC_750L32    = 0x00088302,


  		





  
  205
  
    
    CPU_PPC_750CL     = 0x00087200,


  		





  115
  206
  
    
    /* PowerPC 74xx cores (aka G4) */


  		





  116
  
  
    
    CPU_PPC_7400      = 0x000C0000,


  		





  117
  
  
    
    CPU_PPC_7410      = 0x800C0000,


  		





  118
  
  
    
    CPU_PPC_7441      = 0x80000200,


  		





  119
  
  
    
    CPU_PPC_7450      = 0x80000000,


  		





  
  207
  
    
    CPU_PPC_7400      = 0x000C0100,


  		





  
  208
  
    
    CPU_PPC_7410C     = 0x800C1102,


  		





  
  209
  
    
    CPU_PPC_7410D     = 0x800C1103,


  		





  
  210
  
    
    CPU_PPC_7410E     = 0x800C1104,


  		





  
  211
  
    
    CPU_PPC_7441      = 0x80000210,


  		





  
  212
  
    
    CPU_PPC_7445      = 0x80010100,


  		





  
  213
  
    
    CPU_PPC_7447      = 0x80020100,


  		





  
  214
  
    
    CPU_PPC_7447A     = 0x80030101,


  		





  
  215
  
    
    CPU_PPC_7448      = 0x80040100,


  		





  
  216
  
    
    CPU_PPC_7450      = 0x80000200,


  		





  
  217
  
    
    CPU_PPC_7450b     = 0x80000201,


  		





  120
  218
  
    
    CPU_PPC_7451      = 0x80000203,


  		





  121
  
  
    
    CPU_PPC_7455      = 0x80010000,


  		





  122
  
  
    
    CPU_PPC_7457      = 0x80020000,


  		





  
  219
  
    
    CPU_PPC_7451G     = 0x80000210,


  		





  
  220
  
    
    CPU_PPC_7455      = 0x80010201,


  		





  
  221
  
    
    CPU_PPC_7455F     = 0x80010303,


  		





  
  222
  
    
    CPU_PPC_7455G     = 0x80010304,


  		





  
  223
  
    
    CPU_PPC_7457      = 0x80020101,


  		





  
  224
  
    
    CPU_PPC_7457C     = 0x80020102,


  		





  123
  225
  
    
    CPU_PPC_7457A     = 0x80030000,


  		





  124
  226
  
    
    /* 64 bits PowerPC */


  		





  125
  227
  
    
    CPU_PPC_620       = 0x00140000,


  		





  ......




  130
  232
  
    
    CPU_PPC_POWER5    = 0x003A0000,


  		





  131
  233
  
    
    CPU_PPC_POWER5P   = 0x003B0000,


  		





  132
  234
  
    
    CPU_PPC_970       = 0x00390000,


  		





  133
  
  
    
    CPU_PPC_970FX     = 0x003C0000,


  		





  
  235
  
    
    CPU_PPC_970FX10   = 0x00391100,


  		





  
  236
  
    
    CPU_PPC_970FX20   = 0x003C0200,


  		





  
  237
  
    
    CPU_PPC_970FX21   = 0x003C0201,


  		





  
  238
  
    
    CPU_PPC_970FX30   = 0x003C0300,


  		





  
  239
  
    
    CPU_PPC_970FX31   = 0x003C0301,


  		





  
  240
  
    
#define CPU_PPC_970FX CPU_PPC_970FX31


  		





  
  241
  
    
    CPU_PPC_970MP10   = 0x00440100,


  		





  
  242
  
    
    CPU_PPC_970MP11   = 0x00440101,


  		





  
  243
  
    
#define CPU_PPC_970MP CPU_PPC_970MP11


  		





  
  244
  
    
    CPU_PPC_CELL10    = 0x00700100,


  		





  
  245
  
    
    CPU_PPC_CELL20    = 0x00700400,


  		





  
  246
  
    
    CPU_PPC_CELL30    = 0x00700500,


  		





  
  247
  
    
    CPU_PPC_CELL31    = 0x00700501,


  		





  
  248
  
    
#define CPU_PPC_CELL32 CPU_PPC_CELL31


  		





  
  249
  
    
#define CPU_PPC_CELL CPU_PPC_CELL32


  		





  134
  250
  
    
    CPU_PPC_RS64      = 0x00330000,


  		





  135
  251
  
    
    CPU_PPC_RS64II    = 0x00340000,


  		





  136
  252
  
    
    CPU_PPC_RS64III   = 0x00360000,


  		





  ......




  147
  263
  
    
#endif


  		





  148
  264
  
    
};


  		





  149
  265
  
    

  		





  150
  
  
    
/* System version register (used on MPC 8xx) */


  		





  
  266
  
    
/* System version register (used on MPC 8xxx) */


  		





  151
  267
  
    
enum {


  		





  152
  268
  
    
    PPC_SVR_8540      = 0x80300000,


  		





  153
  
  
    
    PPC_SVR_8541E     = 0x807A0000,


  		





  154
  
  
    
    PPC_SVR_8555E     = 0x80790000,


  		





  155
  
  
    
    PPC_SVR_8560      = 0x80700000,


  		





  
  269
  
    
    PPC_SVR_8541E     = 0x807A0010,


  		





  
  270
  
    
    PPC_SVR_8543v10   = 0x80320010,


  		





  
  271
  
    
    PPC_SVR_8543v11   = 0x80320011,


  		





  
  272
  
    
    PPC_SVR_8543v20   = 0x80320020,


  		





  
  273
  
    
    PPC_SVR_8543Ev10  = 0x803A0010,


  		





  
  274
  
    
    PPC_SVR_8543Ev11  = 0x803A0011,


  		





  
  275
  
    
    PPC_SVR_8543Ev20  = 0x803A0020,


  		





  
  276
  
    
    PPC_SVR_8545      = 0x80310220,


  		





  
  277
  
    
    PPC_SVR_8545E     = 0x80390220,


  		





  
  278
  
    
    PPC_SVR_8547E     = 0x80390120,


  		





  
  279
  
    
    PPC_SCR_8548v10   = 0x80310010,


  		





  
  280
  
    
    PPC_SCR_8548v11   = 0x80310011,


  		





  
  281
  
    
    PPC_SCR_8548v20   = 0x80310020,


  		





  
  282
  
    
    PPC_SVR_8548Ev10  = 0x80390010,


  		





  
  283
  
    
    PPC_SVR_8548Ev11  = 0x80390011,


  		





  
  284
  
    
    PPC_SVR_8548Ev20  = 0x80390020,


  		





  
  285
  
    
    PPC_SVR_8555E     = 0x80790010,


  		





  
  286
  
    
    PPC_SVR_8560v10   = 0x80700010,


  		





  
  287
  
    
    PPC_SVR_8560v20   = 0x80700020,


  		





  156
  288
  
    
};


  		





  157
  289
  
    

  		





  158
  290
  
    
/*****************************************************************************/


  		





  ......




  197
  329
  
    
    /* Time base support                           */


  		





  198
  330
  
    
    PPC_TB          = 0x00002000,


  		





  199
  331
  
    
    /* Embedded PowerPC dedicated instructions     */


  		





  200
  
  
    
    PPC_4xx_COMMON  = 0x00004000,


  		





  
  332
  
    
    PPC_EMB_COMMON  = 0x00004000,


  		





  201
  333
  
    
    /* PowerPC 40x exception model                 */


  		





  202
  334
  
    
    PPC_40x_EXCP    = 0x00008000,


  		





  203
  335
  
    
    /* PowerPC 40x specific instructions           */


  		





  ......




  225
  357
  
    
    PPC_64H         = 0x02000000,


  		





  226
  358
  
    
    /* 64 bits PowerPC "bridge" features           */


  		





  227
  359
  
    
    PPC_64_BRIDGE   = 0x04000000,


  		





  
  360
  
    
    /* BookE (embedded) PowerPC specification      */


  		





  
  361
  
    
    PPC_BOOKE       = 0x08000000,


  		





  
  362
  
    
    /* eieio */


  		





  
  363
  
    
    PPC_MEM_EIEIO   = 0x10000000,


  		





  
  364
  
    
    /* e500 vector instructions */


  		





  
  365
  
    
    PPC_E500_VECTOR = 0x20000000,


  		





  
  366
  
    
    /* PowerPC 4xx dedicated instructions     */


  		





  
  367
  
    
    PPC_4xx_COMMON  = 0x40000000,


  		





  228
  368
  
    
};


  		





  229
  369
  
    

  		





  230
  370
  
    
/* CPU run-time flags (MMU and exception model) */


  		





  231
  371
  
    
enum {


  		





  232
  372
  
    
    /* MMU model */


  		





  233
  
  
    
#define PPC_FLAGS_MMU_MASK (0x0000000F)


  		





  
  373
  
    
    PPC_FLAGS_MMU_MASK     = 0x0000000F,


  		





  234
  374
  
    
    /* Standard 32 bits PowerPC MMU */


  		





  235
  375
  
    
    PPC_FLAGS_MMU_32B      = 0x00000000,


  		





  236
  376
  
    
    /* Standard 64 bits PowerPC MMU */


  		





  ......




  243
  383
  
    
    PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,


  		





  244
  384
  
    
    /* PowerPC 403 MMU */


  		





  245
  385
  
    
    PPC_FLAGS_MMU_403      = 0x00000005,


  		





  
  386
  
    
    /* Freescale e500 MMU model */


  		





  
  387
  
    
    PPC_FLAGS_MMU_e500     = 0x00000006,


  		





  246
  388
  
    
    /* Exception model */


  		





  247
  
  
    
#define PPC_FLAGS_EXCP_MASK (0x000000F0)


  		





  
  389
  
    
    PPC_FLAGS_EXCP_MASK    = 0x000000F0,


  		





  248
  390
  
    
    /* Standard PowerPC exception model */


  		





  249
  391
  
    
    PPC_FLAGS_EXCP_STD     = 0x00000000,


  		





  250
  392
  
    
    /* PowerPC 40x exception model */


  		





  ......




  277
  419
  
    
#define PPC_FLAGS_TODO (0x00000000)


  		





  278
  420
  
    

  		





  279
  421
  
    
/* PowerPC 40x instruction set */


  		





  280
  
  
    
#define PPC_INSNS_4xx (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_4xx_COMMON)


  		





  
  422
  
    
#define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_EMB_COMMON)


  		





  281
  423
  
    
/* PowerPC 401 */


  		





  282
  424
  
    
#define PPC_INSNS_401 (PPC_INSNS_TODO)


  		





  283
  425
  
    
#define PPC_FLAGS_401 (PPC_FLAGS_TODO)


  		





  284
  426
  
    
/* PowerPC 403 */


  		





  285
  
  
    
#define PPC_INSNS_403 (PPC_INSNS_4xx | PPC_MEM_SYNC | PPC_MEM_TLBIA |         \


  		





  286
  
  
    
                       PPC_40x_EXCP | PPC_40x_SPEC)


  		





  
  427
  
    
#define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO |         \


  		





  
  428
  
    
                       PPC_MEM_TLBIA | PPC_4xx_COMMON | PPC_40x_EXCP |        \


  		





  
  429
  
    
                       PPC_40x_SPEC)


  		





  287
  430
  
    
#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x)


  		





  288
  431
  
    
/* PowerPC 405 */


  		





  289
  
  
    
#define PPC_INSNS_405 (PPC_INSNS_4xx | PPC_MEM_SYNC | PPC_CACHE_OPT |         \


  		





  290
  
  
    
                       PPC_MEM_TLBIA | PPC_TB | PPC_40x_SPEC | PPC_40x_EXCP | \


  		





  
  432
  
    
#define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO |         \


  		





  
  433
  
    
                       PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_TB |               \


  		





  
  434
  
    
                       PPC_4xx_COMMON | PPC_40x_SPEC |  PPC_40x_EXCP |        \


  		





  291
  435
  
    
                       PPC_405_MAC)


  		





  292
  436
  
    
#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)


  		





  293
  437
  
    
/* PowerPC 440 */


  		





  294
  
  
    
#define PPC_INSNS_440 (PPC_INSNS_4xx | PPC_CACHE_OPT | PPC_405_MAC |          \


  		





  295
  
  
    
                       PPC_440_SPEC)


  		





  
  438
  
    
#define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE |            \


  		





  
  439
  
    
                       PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)


  		





  296
  440
  
    
#define PPC_FLAGS_440 (PPC_FLAGS_TODO)


  		





  
  441
  
    
/* Generic BookE PowerPC */


  		





  
  442
  
    
#define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO |          \


  		





  
  443
  
    
                         PPC_FLOAT | PPC_FLOAT_OPT | PPC_CACHE_OPT)


  		





  
  444
  
    
#define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)


  		





  
  445
  
    
/* e500 core */


  		





  
  446
  
    
#define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO |           \


  		





  
  447
  
    
                        PPC_CACHE_OPT | PPC_E500_VECTOR)


  		





  
  448
  
    
#define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)


  		





  297
  449
  
    
/* Non-embedded PowerPC */


  		





  298
  450
  
    
#define PPC_INSNS_COMMON  (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC |        \


  		





  299
  
  
    
                           PPC_SEGMENT | PPC_MEM_TLBIE)


  		





  
  451
  
    
                            PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)


  		





  300
  452
  
    
/* PowerPC 601 */


  		





  301
  453
  
    
#define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)


  		





  302
  454
  
    
#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601)


  		





  303
  455
  
    
/* PowerPC 602 */


  		





  304
  456
  
    
#define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |       \


  		





  305
  
  
    
                       PPC_MEM_TLBSYNC | PPC_TB)


  		





  
  457
  
    
                       PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC)


  		





  306
  458
  
    
#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602)


  		





  307
  459
  
    
/* PowerPC 603 */


  		





  308
  460
  
    
#define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |       \


  		





  ......




  348
  500
  
    
typedef struct ppc_spr_t ppc_spr_t;


  		





  349
  501
  
    
typedef struct ppc_dcr_t ppc_dcr_t;


  		





  350
  502
  
    
typedef struct ppc_avr_t ppc_avr_t;


  		





  
  503
  
    
typedef struct ppc_tlb_t ppc_tlb_t;


  		





  
  504
  
    

  		





  351
  505
  
    

  		





  352
  506
  
    
/* SPR access micro-ops generations callbacks */


  		





  353
  507
  
    
struct ppc_spr_t {


  		





  354
  508
  
    
    void (*uea_read)(void *opaque, int spr_num);


  		





  355
  509
  
    
    void (*uea_write)(void *opaque, int spr_num);


  		





  
  510
  
    
#if !defined(CONFIG_USER_ONLY)


  		





  356
  511
  
    
    void (*oea_read)(void *opaque, int spr_num);


  		





  357
  512
  
    
    void (*oea_write)(void *opaque, int spr_num);


  		





  
  513
  
    
#endif


  		





  358
  514
  
    
    const unsigned char *name;


  		





  359
  515
  
    
};


  		





  360
  516
  
    

  		





  ......




  364
  520
  
    
};


  		





  365
  521
  
    

  		





  366
  522
  
    
/* Software TLB cache */


  		





  367
  
  
    
typedef struct ppc_tlb_t ppc_tlb_t;


  		





  368
  523
  
    
struct ppc_tlb_t {


  		





  369
  
  
    
    /* Physical page number */


  		





  370
  
  
    
    target_phys_addr_t RPN;


  		





  371
  
  
    
    /* Virtual page number */


  		





  372
  
  
    
    target_ulong VPN;


  		





  373
  
  
    
    /* Page size */


  		





  374
  
  
    
    target_ulong size;


  		





  375
  
  
    
    /* Protection bits */


  		





  376
  
  
    
    int prot;


  		





  377
  
  
    
    int is_user;


  		





  378
  
  
    
    uint32_t private;


  		





  379
  
  
    
    uint32_t flags;


  		





  
  524
  
    
    target_ulong pte0;


  		





  
  525
  
    
    target_ulong pte1;


  		





  
  526
  
    
    target_ulong EPN;


  		





  
  527
  
    
    target_ulong PID;


  		





  
  528
  
    
    int size;


  		





  380
  529
  
    
};


  		





  381
  530
  
    

  		





  382
  531
  
    
/*****************************************************************************/


  		





  383
  532
  
    
/* Machine state register bits definition                                    */


  		





  384
  
  
    
#define MSR_SF   63 /* Sixty-four-bit mode                                   */


  		





  
  533
  
    
#define MSR_SF   63 /* Sixty-four-bit mode                            hflags */


  		





  385
  534
  
    
#define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */


  		





  386
  
  
    
#define MSR_HV   60 /* hypervisor state                                      */


  		





  387
  
  
    
#define MSR_VR   25 /* altivec available                                     */


  		





  388
  
  
    
#define MSR_AP   23 /* Access privilege state on 602                         */


  		





  389
  
  
    
#define MSR_SA   22 /* Supervisor access mode on 602                         */


  		





  
  535
  
    
#define MSR_HV   60 /* hypervisor state                               hflags */


  		





  
  536
  
    
#define MSR_UCLE 26 /* User-mode cache lock enable on e500                   */


  		





  
  537
  
    
#define MSR_VR   25 /* altivec available                              hflags */


  		





  
  538
  
    
#define MSR_SPE  25 /* SPE enable on e500                             hflags */


  		





  
  539
  
    
#define MSR_AP   23 /* Access privilege state on 602                  hflags */


  		





  
  540
  
    
#define MSR_SA   22 /* Supervisor access mode on 602                  hflags */


  		





  390
  541
  
    
#define MSR_KEY  19 /* key bit on 603e                                       */


  		





  391
  542
  
    
#define MSR_POW  18 /* Power management                                      */


  		





  392
  543
  
    
#define MSR_WE   18 /* Wait state enable on embedded PowerPC                 */


  		





  393
  544
  
    
#define MSR_TGPR 17 /* TGPR usage on 602/603                                 */


  		





  394
  
  
    
#define MSR_TLB  17 /* TLB on ?                                              */


  		





  
  545
  
    
#define MSR_TLB  17 /* TLB update on ?                                       */


  		





  395
  546
  
    
#define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC         */


  		





  396
  547
  
    
#define MSR_ILE  16 /* Interrupt little-endian mode                          */


  		





  397
  548
  
    
#define MSR_EE   15 /* External interrupt enable                             */


  		





  398
  
  
    
#define MSR_PR   14 /* Problem state                                         */


  		





  399
  
  
    
#define MSR_FP   13 /* Floating point available                              */


  		





  
  549
  
    
#define MSR_PR   14 /* Problem state                                  hflags */


  		





  
  550
  
    
#define MSR_FP   13 /* Floating point available                       hflags */


  		





  400
  551
  
    
#define MSR_ME   12 /* Machine check interrupt enable                        */


  		





  401
  
  
    
#define MSR_FE0  11 /* Floating point exception mode 0                       */


  		





  402
  
  
    
#define MSR_SE   10 /* Single-step trace enable                              */


  		





  
  552
  
    
#define MSR_FE0  11 /* Floating point exception mode 0                hflags */


  		





  
  553
  
    
#define MSR_SE   10 /* Single-step trace enable                       hflags */


  		





  403
  554
  
    
#define MSR_DWE  10 /* Debug wait enable on 405                              */


  		





  404
  
  
    
#define MSR_BE   9  /* Branch trace enable                                   */


  		





  
  555
  
    
#define MSR_UBLE 10 /* User BTB lock enable on e500                          */


  		





  
  556
  
    
#define MSR_BE   9  /* Branch trace enable                            hflags */


  		





  405
  557
  
    
#define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC           */


  		





  406
  
  
    
#define MSR_FE1  8  /* Floating point exception mode 1                       */


  		





  
  558
  
    
#define MSR_FE1  8  /* Floating point exception mode 1                hflags */


  		





  407
  559
  
    
#define MSR_AL   7  /* AL bit on POWER                                       */


  		





  408
  560
  
    
#define MSR_IP   6  /* Interrupt prefix                                      */


  		





  409
  561
  
    
#define MSR_IR   5  /* Instruction relocate                                  */


  		





  ......




  415
  567
  
    
#define MSR_PX   2  /* Protection exclusive on 403                           */


  		





  416
  568
  
    
#define MSR_PMM  2  /* Performance monitor mark on POWER                     */


  		





  417
  569
  
    
#define MSR_RI   1  /* Recoverable interrupt                                 */


  		





  418
  
  
    
#define MSR_LE   0  /* Little-endian mode                                    */


  		





  
  570
  
    
#define MSR_LE   0  /* Little-endian mode                             hflags */


  		





  419
  571
  
    
#define msr_sf   env->msr[MSR_SF]


  		





  420
  572
  
    
#define msr_isf  env->msr[MSR_ISF]


  		





  421
  573
  
    
#define msr_hv   env->msr[MSR_HV]


  		





  
  574
  
    
#define msr_ucle env->msr[MSR_UCLE]


  		





  422
  575
  
    
#define msr_vr   env->msr[MSR_VR]


  		





  
  576
  
    
#define msr_spe  env->msr[MSR_SPE]


  		





  423
  577
  
    
#define msr_ap   env->msr[MSR_AP]


  		





  424
  578
  
    
#define msr_sa   env->msr[MSR_SA]


  		





  425
  579
  
    
#define msr_key  env->msr[MSR_KEY]


  		





  426
  
  
    
#define msr_pow env->msr[MSR_POW]


  		





  
  580
  
    
#define msr_pow  env->msr[MSR_POW]


  		





  427
  581
  
    
#define msr_we   env->msr[MSR_WE]


  		





  428
  582
  
    
#define msr_tgpr env->msr[MSR_TGPR]


  		





  429
  583
  
    
#define msr_tlb  env->msr[MSR_TLB]


  		





  430
  584
  
    
#define msr_ce   env->msr[MSR_CE]


  		





  431
  
  
    
#define msr_ile env->msr[MSR_ILE]


  		





  432
  
  
    
#define msr_ee  env->msr[MSR_EE]


  		





  433
  
  
    
#define msr_pr  env->msr[MSR_PR]


  		





  434
  
  
    
#define msr_fp  env->msr[MSR_FP]


  		





  435
  
  
    
#define msr_me  env->msr[MSR_ME]


  		





  436
  
  
    
#define msr_fe0 env->msr[MSR_FE0]


  		





  437
  
  
    
#define msr_se  env->msr[MSR_SE]


  		





  
  585
  
    
#define msr_ile  env->msr[MSR_ILE]


  		





  
  586
  
    
#define msr_ee   env->msr[MSR_EE]


  		





  
  587
  
    
#define msr_pr   env->msr[MSR_PR]


  		





  
  588
  
    
#define msr_fp   env->msr[MSR_FP]


  		





  
  589
  
    
#define msr_me   env->msr[MSR_ME]


  		





  
  590
  
    
#define msr_fe0  env->msr[MSR_FE0]


  		





  
  591
  
    
#define msr_se   env->msr[MSR_SE]


  		





  438
  592
  
    
#define msr_dwe  env->msr[MSR_DWE]


  		





  439
  
  
    
#define msr_be  env->msr[MSR_BE]


  		





  
  593
  
    
#define msr_uble env->msr[MSR_UBLE]


  		





  
  594
  
    
#define msr_be   env->msr[MSR_BE]


  		





  440
  595
  
    
#define msr_de   env->msr[MSR_DE]


  		





  441
  
  
    
#define msr_fe1 env->msr[MSR_FE1]


  		





  
  596
  
    
#define msr_fe1  env->msr[MSR_FE1]


  		





  442
  597
  
    
#define msr_al   env->msr[MSR_AL]


  		





  443
  
  
    
#define msr_ip  env->msr[MSR_IP]


  		





  444
  
  
    
#define msr_ir  env->msr[MSR_IR]


  		





  
  598
  
    
#define msr_ip   env->msr[MSR_IP]


  		





  
  599
  
    
#define msr_ir   env->msr[MSR_IR]


  		





  445
  600
  
    
#define msr_is   env->msr[MSR_IS]


  		





  446
  
  
    
#define msr_dr  env->msr[MSR_DR]


  		





  
  601
  
    
#define msr_dr   env->msr[MSR_DR]


  		





  447
  602
  
    
#define msr_ds   env->msr[MSR_DS]


  		





  448
  603
  
    
#define msr_pe   env->msr[MSR_PE]


  		





  449
  604
  
    
#define msr_ep   env->msr[MSR_EP]


  		





  450
  605
  
    
#define msr_px   env->msr[MSR_PX]


  		





  451
  606
  
    
#define msr_pmm  env->msr[MSR_PMM]


  		





  452
  
  
    
#define msr_ri  env->msr[MSR_RI]


  		





  453
  
  
    
#define msr_le  env->msr[MSR_LE]


  		





  
  607
  
    
#define msr_ri   env->msr[MSR_RI]


  		





  
  608
  
    
#define msr_le   env->msr[MSR_LE]


  		





  454
  609
  
    

  		





  455
  610
  
    
/*****************************************************************************/


  		





  456
  611
  
    
/* The whole PowerPC CPU context */


  		





  ......




  465
  620
  
    
    target_ulong t0, t1, t2;


  		





  466
  621
  
    
#endif


  		





  467
  622
  
    
    /* general purpose registers */


  		





  468
  
  
    
    target_ulong gpr[32];


  		





  
  623
  
    
    ppc_gpr_t gpr[32];


  		





  469
  624
  
    
    /* LR */


  		





  470
  625
  
    
    target_ulong lr;


  		





  471
  626
  
    
    /* CTR */


  		





  ......




  482
  637
  
    
    /* machine state register */


  		





  483
  638
  
    
    uint8_t msr[64];


  		





  484
  639
  
    
    /* temporary general purpose registers */


  		





  485
  
  
    
    target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */


  		





  
  640
  
    
    ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */


  		





  486
  641
  
    

  		





  487
  642
  
    
    /* Floating point execution context */


  		





  488
  
  
    
     /* temporary float registers */


  		





  
  643
  
    
    /* temporary float registers */


  		





  489
  644
  
    
    float64 ft0;


  		





  490
  645
  
    
    float64 ft1;


  		





  491
  646
  
    
    float64 ft2;


  		





  ......




  529
  684
  
    
    ppc_dcr_t *dcr_env;


  		





  530
  685
  
    

  		





  531
  686
  
    
    /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */


  		





  532
  
  
    
    int nb_tlb;


  		





  533
  
  
    
    int nb_ways, last_way;


  		





  534
  
  
    
    ppc_tlb_t tlb[128];


  		





  
  687
  
    
    int nb_tlb;      /* Total number of TLB                                  */


  		





  
  688
  
    
    int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */


  		





  
  689
  
    
    int nb_ways;     /* Number of ways in the TLB set                        */


  		





  
  690
  
    
    int last_way;    /* Last used way used to allocate TLB in a LRU way      */


  		





  
  691
  
    
    int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */


  		





  
  692
  
    
    ppc_tlb_t *tlb;  /* TLB is optional. Allocate them only if needed        */


  		





  535
  693
  
    
    /* Callbacks for specific checks on some implementations */


  		





  536
  694
  
    
    int (*tlb_check_more)(CPUPPCState *env, struct ppc_tlb_t *tlb, int *prot,


  		





  537
  695
  
    
                          target_ulong vaddr, int rw, int acc_type,


  		





  ......




  568
  726
  
    
    int (*osi_call)(struct CPUPPCState *env);


  		





  569
  727
  
    
};


  		





  570
  728
  
    

  		





  
  729
  
    
/* Context used internally during MMU translations */


  		





  
  730
  
    
typedef struct mmu_ctx_t mmu_ctx_t;


  		





  
  731
  
    
struct mmu_ctx_t {


  		





  
  732
  
    
    target_phys_addr_t raddr;      /* Real address              */


  		





  
  733
  
    
    int prot;                      /* Protection bits           */


  		





  
  734
  
    
    target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */


  		





  
  735
  
    
    target_ulong ptem;             /* Virtual segment ID | API  */


  		





  
  736
  
    
    int key;                       /* Access key                */


  		





  
  737
  
    
};


  		





  
  738
  
    

  		





  571
  739
  
    
/*****************************************************************************/


  		





  572
  740
  
    
CPUPPCState *cpu_ppc_init(void);


  		





  573
  741
  
    
int cpu_ppc_exec(CPUPPCState *s);


  		





  ......




  583
  751
  
    

  		





  584
  752
  
    
void dump_stack (CPUPPCState *env);


  		





  585
  753
  
    

  		





  
  754
  
    
#if !defined(CONFIG_USER_ONLY)


  		





  586
  755
  
    
target_ulong do_load_ibatu (CPUPPCState *env, int nr);


  		





  587
  756
  
    
target_ulong do_load_ibatl (CPUPPCState *env, int nr);


  		





  588
  757
  
    
void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);


  		





  ......




  591
  760
  
    
target_ulong do_load_dbatl (CPUPPCState *env, int nr);


  		





  592
  761
  
    
void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);


  		





  593
  762
  
    
void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);


  		





  594
  
  
    

  		





  595
  
  
    
target_ulong do_load_nip (CPUPPCState *env);


  		





  596
  
  
    
void do_store_nip (CPUPPCState *env, target_ulong value);


  		





  597
  763
  
    
target_ulong do_load_sdr1 (CPUPPCState *env);


  		





  598
  764
  
    
void do_store_sdr1 (CPUPPCState *env, target_ulong value);


  		





  599
  765
  
    
target_ulong do_load_asr (CPUPPCState *env);


  		





  600
  766
  
    
void do_store_asr (CPUPPCState *env, target_ulong value);


  		





  601
  767
  
    
target_ulong do_load_sr (CPUPPCState *env, int srnum);


  		





  602
  768
  
    
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);


  		





  603
  
  
    
uint32_t do_load_cr (CPUPPCState *env);


  		





  604
  
  
    
void do_store_cr (CPUPPCState *env, uint32_t value, uint32_t mask);


  		





  605
  
  
    
uint32_t do_load_xer (CPUPPCState *env);


  		





  606
  
  
    
void do_store_xer (CPUPPCState *env, uint32_t value);


  		





  
  769
  
    
#endif


  		





  
  770
  
    
uint32_t ppc_load_xer (CPUPPCState *env);


  		





  
  771
  
    
void ppc_store_xer (CPUPPCState *env, uint32_t value);


  		





  607
  772
  
    
target_ulong do_load_msr (CPUPPCState *env);


  		





  608
  773
  
    
void do_store_msr (CPUPPCState *env, target_ulong value);


  		





  609
  
  
    
float64 do_load_fpscr (CPUPPCState *env);


  		





  610
  
  
    
void do_store_fpscr (CPUPPCState *env, float64 f, uint32_t mask);


  		





  611
  774
  
    

  		





  612
  775
  
    
void do_compute_hflags (CPUPPCState *env);


  		





  613
  776
  
    

  		





  ......




  645
  808
  
    
#define xer_bc env->xer[0]


  		





  646
  809
  
    

  		





  647
  810
  
    
/* SPR definitions */


  		





  648
  
  
    
#define SPR_MQ         (0x000)


  		





  649
  
  
    
#define SPR_XER        (0x001)


  		





  650
  
  
    
#define SPR_601_VRTCU  (0x004)


  		





  651
  
  
    
#define SPR_601_VRTCL  (0x005)


  		





  652
  
  
    
#define SPR_601_UDECR  (0x006)


  		





  653
  
  
    
#define SPR_LR         (0x008)


  		





  654
  
  
    
#define SPR_CTR        (0x009)


  		





  655
  
  
    
#define SPR_DSISR      (0x012)


  		





  656
  
  
    
#define SPR_DAR        (0x013)


  		





  657
  
  
    
#define SPR_601_RTCU   (0x014)


  		





  658
  
  
    
#define SPR_601_RTCL   (0x015)


  		





  659
  
  
    
#define SPR_DECR       (0x016)


  		





  660
  
  
    
#define SPR_SDR1       (0x019)


  		





  661
  
  
    
#define SPR_SRR0       (0x01A)


  		





  662
  
  
    
#define SPR_SRR1       (0x01B)


  		





  663
  
  
    
#define SPR_440_PID    (0x030)


  		





  664
  
  
    
#define SPR_440_DECAR  (0x036)


  		





  665
  
  
    
#define SPR_CSRR0      (0x03A)


  		





  666
  
  
    
#define SPR_CSRR1      (0x03B)


  		





  667
  
  
    
#define SPR_440_DEAR   (0x03D)


  		





  668
  
  
    
#define SPR_440_ESR    (0x03E)


  		





  669
  
  
    
#define SPR_440_IVPR   (0x03F)


  		





  670
  
  
    
#define SPR_8xx_EIE    (0x050)


  		





  671
  
  
    
#define SPR_8xx_EID    (0x051)


  		





  672
  
  
    
#define SPR_8xx_NRE    (0x052)


  		





  673
  
  
    
#define SPR_58x_CMPA   (0x090)


  		





  674
  
  
    
#define SPR_58x_CMPB   (0x091)


  		





  675
  
  
    
#define SPR_58x_CMPC   (0x092)


  		





  676
  
  
    
#define SPR_58x_CMPD   (0x093)


  		





  677
  
  
    
#define SPR_58x_ICR    (0x094)


  		





  678
  
  
    
#define SPR_58x_DER    (0x094)


  		





  679
  
  
    
#define SPR_58x_COUNTA (0x096)


  		





  680
  
  
    
#define SPR_58x_COUNTB (0x097)


  		





  681
  
  
    
#define SPR_58x_CMPE   (0x098)


  		





  682
  
  
    
#define SPR_58x_CMPF   (0x099)


  		





  683
  
  
    
#define SPR_58x_CMPG   (0x09A)


  		





  684
  
  
    
#define SPR_58x_CMPH   (0x09B)


  		





  685
  
  
    
#define SPR_58x_LCTRL1 (0x09C)


  		





  686
  
  
    
#define SPR_58x_LCTRL2 (0x09D)


  		





  687
  
  
    
#define SPR_58x_ICTRL  (0x09E)


  		





  688
  
  
    
#define SPR_58x_BAR    (0x09F)


  		





  689
  
  
    
#define SPR_VRSAVE     (0x100)


  		





  690
  
  
    
#define SPR_USPRG0     (0x100)


  		





  691
  
  
    
#define SPR_USPRG4     (0x104)


  		





  692
  
  
    
#define SPR_USPRG5     (0x105)


  		





  693
  
  
    
#define SPR_USPRG6     (0x106)


  		





  694
  
  
    
#define SPR_USPRG7     (0x107)


  		





  695
  
  
    
#define SPR_VTBL       (0x10C)


  		





  696
  
  
    
#define SPR_VTBU       (0x10D)


  		





  697
  
  
    
#define SPR_SPRG0      (0x110)


  		





  698
  
  
    
#define SPR_SPRG1      (0x111)


  		





  699
  
  
    
#define SPR_SPRG2      (0x112)


  		





  700
  
  
    
#define SPR_SPRG3      (0x113)


  		





  701
  
  
    
#define SPR_SPRG4      (0x114)


  		





  702
  
  
    
#define SPR_SCOMC      (0x114)


  		





  703
  
  
    
#define SPR_SPRG5      (0x115)


  		





  704
  
  
    
#define SPR_SCOMD      (0x115)


  		





  705
  
  
    
#define SPR_SPRG6      (0x116)


  		





  706
  
  
    
#define SPR_SPRG7      (0x117)


  		





  707
  
  
    
#define SPR_ASR        (0x118)


  		





  708
  
  
    
#define SPR_EAR        (0x11A)


  		





  709
  
  
    
#define SPR_TBL        (0x11C)


  		





  710
  
  
    
#define SPR_TBU        (0x11D)


  		





  711
  
  
    
#define SPR_SVR        (0x11E)


  		





  712
  
  
    
#define SPR_440_PIR    (0x11E)


  		





  713
  
  
    
#define SPR_PVR        (0x11F)


  		





  714
  
  
    
#define SPR_HSPRG0     (0x130)


  		





  715
  
  
    
#define SPR_440_DBSR   (0x130)


  		





  716
  
  
    
#define SPR_HSPRG1     (0x131)


  		





  717
  
  
    
#define SPR_440_DBCR0  (0x134)


  		





  718
  
  
    
#define SPR_IBCR       (0x135)


  		





  719
  
  
    
#define SPR_440_DBCR1  (0x135)


  		





  720
  
  
    
#define SPR_DBCR       (0x136)


  		





  721
  
  
    
#define SPR_HDEC       (0x136)


  		





  722
  
  
    
#define SPR_440_DBCR2  (0x136)


  		





  723
  
  
    
#define SPR_HIOR       (0x137)


  		





  724
  
  
    
#define SPR_MBAR       (0x137)


  		





  725
  
  
    
#define SPR_RMOR       (0x138)


  		





  726
  
  
    
#define SPR_440_IAC1   (0x138)


  		





  727
  
  
    
#define SPR_HRMOR      (0x139)


  		





  728
  
  
    
#define SPR_440_IAC2   (0x139)


  		





  729
  
  
    
#define SPR_HSSR0      (0x13A)


  		





  730
  
  
    
#define SPR_440_IAC3   (0x13A)


  		





  731
  
  
    
#define SPR_HSSR1      (0x13B)


  		





  732
  
  
    
#define SPR_440_IAC4   (0x13B)


  		





  733
  
  
    
#define SPR_LPCR       (0x13C)


  		





  734
  
  
    
#define SPR_440_DAC1   (0x13C)


  		





  735
  
  
    
#define SPR_LPIDR      (0x13D)


  		





  736
  
  
    
#define SPR_DABR2      (0x13D)


  		





  737
  
  
    
#define SPR_440_DAC2   (0x13D)


  		





  738
  
  
    
#define SPR_440_DVC1   (0x13E)


  		





  739
  
  
    
#define SPR_440_DVC2   (0x13F)


  		





  740
  
  
    
#define SPR_440_TSR    (0x150)


  		





  741
  
  
    
#define SPR_440_TCR    (0x154)


  		





  742
  
  
    
#define SPR_440_IVOR0  (0x190)


  		





  743
  
  
    
#define SPR_440_IVOR1  (0x191)


  		





  744
  
  
    
#define SPR_440_IVOR2  (0x192)


  		





  745
  
  
    
#define SPR_440_IVOR3  (0x193)


  		





  746
  
  
    
#define SPR_440_IVOR4  (0x194)


  		





  747
  
  
    
#define SPR_440_IVOR5  (0x195)


  		





  748
  
  
    
#define SPR_440_IVOR6  (0x196)


  		





  749
  
  
    
#define SPR_440_IVOR7  (0x197)


  		





  750
  
  
    
#define SPR_440_IVOR8  (0x198)


  		





  751
  
  
    
#define SPR_440_IVOR9  (0x199)


  		





  752
  
  
    
#define SPR_440_IVOR10 (0x19A)


  		





  753
  
  
    
#define SPR_440_IVOR11 (0x19B)


  		





  754
  
  
    
#define SPR_440_IVOR12 (0x19C)


  		





  755
  
  
    
#define SPR_440_IVOR13 (0x19D)


  		





  756
  
  
    
#define SPR_440_IVOR14 (0x19E)


  		





  757
  
  
    
#define SPR_440_IVOR15 (0x19F)


  		





  758
  
  
    
#define SPR_IBAT0U     (0x210)


  		





  759
  
  
    
#define SPR_IBAT0L     (0x211)


  		





  760
  
  
    
#define SPR_IBAT1U     (0x212)


  		





  761
  
  
    
#define SPR_IBAT1L     (0x213)


  		





  762
  
  
    
#define SPR_IBAT2U     (0x214)


  		





  763
  
  
    
#define SPR_IBAT2L     (0x215)


  		





  764
  
  
    
#define SPR_IBAT3U     (0x216)


  		





  765
  
  
    
#define SPR_IBAT3L     (0x217)


  		





  766
  
  
    
#define SPR_DBAT0U     (0x218)


  		





  767
  
  
    
#define SPR_DBAT0L     (0x219)


  		





  768
  
  
    
#define SPR_DBAT1U     (0x21A)


  		





  769
  
  
    
#define SPR_DBAT1L     (0x21B)


  		





  770
  
  
    
#define SPR_DBAT2U     (0x21C)


  		





  771
  
  
    
#define SPR_DBAT2L     (0x21D)


  		





  772
  
  
    
#define SPR_DBAT3U     (0x21E)


  		





  773
  
  
    
#define SPR_DBAT3L     (0x21F)


  		





  774
  
  
    
#define SPR_IBAT4U     (0x230)


  		





  775
  
  
    
#define SPR_IBAT4L     (0x231)


  		





  776
  
  
    
#define SPR_IBAT5U     (0x232)


  		





  777
  
  
    
#define SPR_IBAT5L     (0x233)


  		





  778
  
  
    
#define SPR_IBAT6U     (0x234)


  		





  779
  
  
    
#define SPR_IBAT6L     (0x235)


  		





  780
  
  
    
#define SPR_IBAT7U     (0x236)


  		





  781
  
  
    
#define SPR_IBAT7L     (0x237)


  		





  782
  
  
    
#define SPR_DBAT4U     (0x238)


  		





  783
  
  
    
#define SPR_DBAT4L     (0x239)


  		





  784
  
  
    
#define SPR_DBAT5U     (0x23A)


  		





  785
  
  
    
#define SPR_DBAT5L     (0x23B)


  		





  786
  
  
    
#define SPR_DBAT6U     (0x23C)


  		





  787
  
  
    
#define SPR_DBAT6L     (0x23D)


  		





  788
  
  
    
#define SPR_DBAT7U     (0x23E)


  		





  789
  
  
    
#define SPR_DBAT7L     (0x23F)


  		





  790
  
  
    
#define SPR_440_INV0   (0x370)


  		





  791
  
  
    
#define SPR_440_INV1   (0x371)


  		





  792
  
  
    
#define SPR_440_INV2   (0x372)


  		





  793
  
  
    
#define SPR_440_INV3   (0x373)


  		





  794
  
  
    
#define SPR_440_IVT0   (0x374)


  		





  795
  
  
    
#define SPR_440_IVT1   (0x375)


  		





  796
  
  
    
#define SPR_440_IVT2   (0x376)


  		





  797
  
  
    
#define SPR_440_IVT3   (0x377)


  		





  798
  
  
    
#define SPR_440_DNV0   (0x390)


  		





  799
  
  
    
#define SPR_440_DNV1   (0x391)


  		





  800
  
  
    
#define SPR_440_DNV2   (0x392)


  		





  801
  
  
    
#define SPR_440_DNV3   (0x393)


  		





  802
  
  
    
#define SPR_440_DVT0   (0x394)


  		





  803
  
  
    
#define SPR_440_DVT1   (0x395)


  		





  804
  
  
    
#define SPR_440_DVT2   (0x396)


  		





  805
  
  
    
#define SPR_440_DVT3   (0x397)


  		





  806
  
  
    
#define SPR_440_DVLIM  (0x398)


  		





  807
  
  
    
#define SPR_440_IVLIM  (0x399)


  		





  808
  
  
    
#define SPR_440_RSTCFG (0x39B)


  		





  809
  
  
    
#define SPR_440_DCBTRL (0x39C)


  		





  810
  
  
    
#define SPR_440_DCBTRH (0x39D)


  		





  811
  
  
    
#define SPR_440_ICBTRL (0x39E)


  		





  812
  
  
    
#define SPR_440_ICBTRH (0x39F)


  		





  813
  
  
    
#define SPR_UMMCR0     (0x3A8)


  		





  814
  
  
    
#define SPR_UPMC1      (0x3A9)


  		





  815
  
  
    
#define SPR_UPMC2      (0x3AA)


  		





  816
  
  
    
#define SPR_USIA       (0x3AB)


  		





  817
  
  
    
#define SPR_UMMCR1     (0x3AC)


  		





  818
  
  
    
#define SPR_UPMC3      (0x3AD)


  		





  819
  
  
    
#define SPR_UPMC4      (0x3AE)


  		





  820
  
  
    
#define SPR_USDA       (0x3AF)


  		





  821
  
  
    
#define SPR_40x_ZPR    (0x3B0)


  		





  822
  
  
    
#define SPR_40x_PID    (0x3B1)


  		





  823
  
  
    
#define SPR_440_MMUCR  (0x3B2)


  		





  824
  
  
    
#define SPR_4xx_CCR0   (0x3B3)


  		





  825
  
  
    
#define SPR_405_IAC3   (0x3B4)


  		





  826
  
  
    
#define SPR_405_IAC4   (0x3B5)


  		





  827
  
  
    
#define SPR_405_DVC1   (0x3B6)


  		





  828
  
  
    
#define SPR_405_DVC2   (0x3B7)


  		





  829
  
  
    
#define SPR_MMCR0      (0x3B8)


  		





  830
  
  
    
#define SPR_PMC1       (0x3B9)


  		





  831
  
  
    
#define SPR_40x_SGR    (0x3B9)


  		





  832
  
  
    
#define SPR_PMC2       (0x3BA)


  		





  833
  
  
    
#define SPR_40x_DCWR   (0x3BA)


  		





  834
  
  
    
#define SPR_SIA        (0x3BB)


  		





  835
  
  
    
#define SPR_405_SLER   (0x3BB)


  		





  836
  
  
    
#define SPR_MMCR1      (0x3BC)


  		





  837
  
  
    
#define SPR_405_SU0R   (0x3BC)


  		





  838
  
  
    
#define SPR_PMC3       (0x3BD)


  		





  839
  
  
    
#define SPR_405_DBCR1  (0x3BD)


  		





  840
  
  
    
#define SPR_PMC4       (0x3BE)


  		





  841
  
  
    
#define SPR_SDA        (0x3BF)


  		





  842
  
  
    
#define SPR_403_VTBL   (0x3CC)


  		





  843
  
  
    
#define SPR_403_VTBU   (0x3CD)


  		





  844
  
  
    
#define SPR_DMISS      (0x3D0)


  		





  845
  
  
    
#define SPR_DCMP       (0x3D1)


  		





  846
  
  
    
#define SPR_DHASH1     (0x3D2)


  		





  847
  
  
    
#define SPR_DHASH2     (0x3D3)


  		





  848
  
  
    
#define SPR_4xx_ICDBDR (0x3D3)


  		





  849
  
  
    
#define SPR_IMISS      (0x3D4)


  		





  850
  
  
    
#define SPR_40x_ESR    (0x3D4)


  		





  851
  
  
    
#define SPR_ICMP       (0x3D5)


  		





  852
  
  
    
#define SPR_40x_DEAR   (0x3D5)


  		





  853
  
  
    
#define SPR_RPA        (0x3D6)


  		





  854
  
  
    
#define SPR_40x_EVPR   (0x3D6)


  		





  855
  
  
    
#define SPR_403_CDBCR  (0x3D7)


  		





  856
  
  
    
#define SPR_TCR        (0x3D8)


  		





  857
  
  
    
#define SPR_40x_TSR    (0x3D8)


  		





  858
  
  
    
#define SPR_IBR        (0x3DA)


  		





  859
  
  
    
#define SPR_40x_TCR    (0x3DA)


  		





  860
  
  
    
#define SPR_ESASR      (0x3DB)


  		





  861
  
  
    
#define SPR_40x_PIT    (0x3DB)


  		





  862
  
  
    
#define SPR_403_TBL    (0x3DC)


  		





  863
  
  
    
#define SPR_403_TBU    (0x3DD)


  		





  864
  
  
    
#define SPR_SEBR       (0x3DE)


  		





  865
  
  
    
#define SPR_40x_SRR2   (0x3DE)


  		





  866
  
  
    
#define SPR_SER        (0x3DF)


  		





  867
  
  
    
#define SPR_40x_SRR3   (0x3DF)


  		





  868
  
  
    
#define SPR_HID0       (0x3F0)


  		





  869
  
  
    
#define SPR_40x_DBSR   (0x3F0)


  		





  870
  
  
    
#define SPR_HID1       (0x3F1)


  		





  871
  
  
    
#define SPR_IABR       (0x3F2)


  		





  872
  
  
    
#define SPR_40x_DBCR0  (0x3F2)


  		





  873
  
  
    
#define SPR_601_HID2   (0x3F2)


  		





  874
  
  
    
#define SPR_HID2       (0x3F3)


  		





  875
  
  
    
#define SPR_440_DBDR   (0x3F3)


  		





  876
  
  
    
#define SPR_40x_IAC1   (0x3F4)


  		





  877
  
  
    
#define SPR_DABR       (0x3F5)


  		





  
  811
  
    
#define SPR_MQ           (0x000)


  		





  
  812
  
    
#define SPR_XER          (0x001)


  		





  
  813
  
    
#define SPR_601_VRTCU    (0x004)


  		





  
  814
  
    
#define SPR_601_VRTCL    (0x005)


  		





  
  815
  
    
#define SPR_601_UDECR    (0x006)


  		





  
  816
  
    
#define SPR_LR           (0x008)


  		





  
  817
  
    
#define SPR_CTR          (0x009)


  		





  
  818
  
    
#define SPR_DSISR        (0x012)


  		





  
  819
  
    
#define SPR_DAR          (0x013)


  		





  
  820
  
    
#define SPR_601_RTCU     (0x014)


  		





  
  821
  
    
#define SPR_601_RTCL     (0x015)


  		





  
  822
  
    
#define SPR_DECR         (0x016)


  		





  
  823
  
    
#define SPR_SDR1         (0x019)


  		





  
  824
  
    
#define SPR_SRR0         (0x01A)


  		





  
  825
  
    
#define SPR_SRR1         (0x01B)


  		





  
  826
  
    
#define SPR_BOOKE_PID    (0x030)


  		





  
  827
  
    
#define SPR_BOOKE_DECAR  (0x036)


  		





  
  828
  
    
#define SPR_CSRR0        (0x03A)


  		





  
  829
  
    
#define SPR_CSRR1        (0x03B)


  		





  
  830
  
    
#define SPR_BOOKE_DEAR   (0x03D)


  		





  
  831
  
    
#define SPR_BOOKE_ESR    (0x03E)


  		





  
  832
  
    
#define SPR_BOOKE_EVPR   (0x03F)


  		





  
  833
  
    
#define SPR_8xx_EIE      (0x050)


  		





  
  834
  
    
#define SPR_8xx_EID      (0x051)


  		





  
  835
  
    
#define SPR_8xx_NRE      (0x052)


  		





  
  836
  
    
#define SPR_58x_CMPA     (0x090)


  		





  
  837
  
    
#define SPR_58x_CMPB     (0x091)


  		





  
  838
  
    
#define SPR_58x_CMPC     (0x092)


  		





  
  839
  
    
#define SPR_58x_CMPD     (0x093)


  		





  
  840
  
    
#define SPR_58x_ICR      (0x094)


  		





  
  841
  
    
#define SPR_58x_DER      (0x094)


  		





  
  842
  
    
#define SPR_58x_COUNTA   (0x096)


  		





  
  843
  
    
#define SPR_58x_COUNTB   (0x097)


  		





  
  844
  
    
#define SPR_58x_CMPE     (0x098)


  		





  
  845
  
    
#define SPR_58x_CMPF     (0x099)


  		





  
  846
  
    
#define SPR_58x_CMPG     (0x09A)


  		





  
  847
  
    
#define SPR_58x_CMPH     (0x09B)


  		





  
  848
  
    
#define SPR_58x_LCTRL1   (0x09C)


  		





  
  849
  
    
#define SPR_58x_LCTRL2   (0x09D)


  		





  
  850
  
    
#define SPR_58x_ICTRL    (0x09E)


  		





  
  851
  
    
#define SPR_58x_BAR      (0x09F)


  		





  
  852
  
    
#define SPR_VRSAVE       (0x100)


  		





  
  853
  
    
#define SPR_USPRG0       (0x100)


  		





  
  854
  
    
#define SPR_USPRG4       (0x104)


  		





  
  855
  
    
#define SPR_USPRG5       (0x105)


  		





  
  856
  
    
#define SPR_USPRG6       (0x106)


  		





  
  857
  
    
#define SPR_USPRG7       (0x107)


  		





  
  858
  
    
#define SPR_VTBL         (0x10C)


  		





  
  859
  
    
#define SPR_VTBU         (0x10D)


  		





  
  860
  
    
#define SPR_SPRG0        (0x110)


  		





  
  861
  
    
#define SPR_SPRG1        (0x111)


  		





  
  862
  
    
#define SPR_SPRG2        (0x112)


  		





  
  863
  
    
#define SPR_SPRG3        (0x113)


  		





  
  864
  
    
#define SPR_SPRG4        (0x114)


  		





  
  865
  
    
#define SPR_SCOMC        (0x114)


  		





  
  866
  
    
#define SPR_SPRG5        (0x115)


  		





  
  867
  
    
#define SPR_SCOMD        (0x115)


  		





  
  868
  
    
#define SPR_SPRG6        (0x116)


  		





  
  869
  
    
#define SPR_SPRG7        (0x117)


  		





  
  870
  
    
#define SPR_ASR          (0x118)


  		





  
  871
  
    
#define SPR_EAR          (0x11A)


  		





  
  872
  
    
#define SPR_TBL          (0x11C)


  		





  
  873
  
    
#define SPR_TBU          (0x11D)


  		





  
  874
  
    
#define SPR_SVR          (0x11E)


  		





  
  875
  
    
#define SPR_BOOKE_PIR    (0x11E)


  		





  
  876
  
    
#define SPR_PVR          (0x11F)


  		





  
  877
  
    
#define SPR_HSPRG0       (0x130)


  		





  
  878
  
    
#define SPR_BOOKE_DBSR   (0x130)


  		





  
  879
  
    
#define SPR_HSPRG1       (0x131)


  		





  
  880
  
    
#define SPR_BOOKE_DBCR0  (0x134)


  		





  
  881
  
    
#define SPR_IBCR         (0x135)


  		





  
  882
  
    
#define SPR_BOOKE_DBCR1  (0x135)


  		





  
  883
  
    
#define SPR_DBCR         (0x136)


  		





  
  884
  
    
#define SPR_HDEC         (0x136)


  		





  
  885
  
    
#define SPR_BOOKE_DBCR2  (0x136)


  		





  
  886
  
    
#define SPR_HIOR         (0x137)


  		





  
  887
  
    
#define SPR_MBAR         (0x137)


  		





  
  888
  
    
#define SPR_RMOR         (0x138)


  		





  
  889
  
    
#define SPR_BOOKE_IAC1   (0x138)


  		





  
  890
  
    
#define SPR_HRMOR        (0x139)


  		





  
  891
  
    
#define SPR_BOOKE_IAC2   (0x139)


  		





  
  892
  
    
#define SPR_HSSR0        (0x13A)


  		





  
  893
  
    
#define SPR_BOOKE_IAC3   (0x13A)


  		





  
  894
  
    
#define SPR_HSSR1        (0x13B)


  		





  
  895
  
    
#define SPR_BOOKE_IAC4   (0x13B)


  		





  
  896
  
    
#define SPR_LPCR         (0x13C)


  		





  
  897
  
    
#define SPR_BOOKE_DAC1   (0x13C)


  		





  
  898
  
    
#define SPR_LPIDR        (0x13D)


  		





  
  899
  
    
#define SPR_DABR2        (0x13D)


  		





  
  900
  
    
#define SPR_BOOKE_DAC2   (0x13D)


  		





  
  901
  
    
#define SPR_BOOKE_DVC1   (0x13E)


  		





  
  902
  
    
#define SPR_BOOKE_DVC2   (0x13F)


  		





  
  903
  
    
#define SPR_BOOKE_TSR    (0x150)


  		





  
  904
  
    
#define SPR_BOOKE_TCR    (0x154)


  		





  
  905
  
    
#define SPR_BOOKE_IVOR0  (0x190)


  		





  
  906
  
    
#define SPR_BOOKE_IVOR1  (0x191)


  		





  
  907
  
    
#define SPR_BOOKE_IVOR2  (0x192)


  		





  
  908
  
    
#define SPR_BOOKE_IVOR3  (0x193)


  		





  
  909
  
    
#define SPR_BOOKE_IVOR4  (0x194)


  		





  
  910
  
    
#define SPR_BOOKE_IVOR5  (0x195)


  		





  
  911
  
    
#define SPR_BOOKE_IVOR6  (0x196)


  		





  
  912
  
    
#define SPR_BOOKE_IVOR7  (0x197)


  		





  
  913
  
    
#define SPR_BOOKE_IVOR8  (0x198)


  		





  
  914
  
    
#define SPR_BOOKE_IVOR9  (0x199)


  		





  
  915
  
    
#define SPR_BOOKE_IVOR10 (0x19A)


  		





  
  916
  
    
#define SPR_BOOKE_IVOR11 (0x19B)


  		





  
  917
  
    
#define SPR_BOOKE_IVOR12 (0x19C)


  		





  
  918
  
    
#define SPR_BOOKE_IVOR13 (0x19D)


  		





  
  919
  
    
#define SPR_BOOKE_IVOR14 (0x19E)


  		





  
  920
  
    
#define SPR_BOOKE_IVOR15 (0x19F)


  		





  
  921
  
    
#define SPR_E500_SPEFSCR (0x200)


  		





  
  922
  
    
#define SPR_E500_BBEAR   (0x201)


  		





  
  923
  
    
#define SPR_E500_BBTAR   (0x202)


  		





  
  924
  
    
#define SPR_BOOKE_ATBL   (0x20E)


  		





  
  925
  
    
#define SPR_BOOKE_ATBU   (0x20F)


  		





  
  926
  
    
#define SPR_IBAT0U       (0x210)


  		





  
  927
  
    
#define SPR_E500_IVOR32  (0x210)


  		





  
  928
  
    
#define SPR_IBAT0L       (0x211)


  		





  
  929
  
    
#define SPR_E500_IVOR33  (0x211)


  		





  
  930
  
    
#define SPR_IBAT1U       (0x212)


  		





  
  931
  
    
#define SPR_E500_IVOR34  (0x212)


  		





  
  932
  
    
#define SPR_IBAT1L       (0x213)


  		





  
  933
  
    
#define SPR_E500_IVOR35  (0x213)


  		





  
  934
  
    
#define SPR_IBAT2U       (0x214)


  		





  
  935
  
    
#define SPR_IBAT2L       (0x215)


  		





  
  936
  
    
#define SPR_E500_L1CFG0  (0x215)


  		





  
  937
  
    
#define SPR_IBAT3U       (0x216)


  		





  
  938
  
    
#define SPR_E500_L1CFG1  (0x216)


  		





  
  939
  
    
#define SPR_IBAT3L       (0x217)


  		





  
  940
  
    
#define SPR_DBAT0U       (0x218)


  		





  
  941
  
    
#define SPR_DBAT0L       (0x219)


  		





  
  942
  
    
#define SPR_DBAT1U       (0x21A)


  		





  
  943
  
    
#define SPR_DBAT1L       (0x21B)


  		





  
  944
  
    
#define SPR_DBAT2U       (0x21C)


  		





  
  945
  
    
#define SPR_DBAT2L       (0x21D)


  		





  
  946
  
    
#define SPR_DBAT3U       (0x21E)


  		





  
  947
  
    
#define SPR_DBAT3L       (0x21F)


  		





  
  948
  
    
#define SPR_IBAT4U       (0x230)


  		





  
  949
  
    
#define SPR_IBAT4L       (0x231)


  		





  
  950
  
    
#define SPR_IBAT5U       (0x232)


  		





  
  951
  
    
#define SPR_IBAT5L       (0x233)


  		





  
  952
  
    
#define SPR_IBAT6U       (0x234)


  		





  
  953
  
    
#define SPR_IBAT6L       (0x235)


  		





  
  954
  
    
#define SPR_IBAT7U       (0x236)


  		





  
  955
  
    
#define SPR_IBAT7L       (0x237)


  		





  
  956
  
    
#define SPR_DBAT4U       (0x238)


  		





  
  957
  
    
#define SPR_DBAT4L       (0x239)


  		





  
  958
  
    
#define SPR_DBAT5U       (0x23A)


  		





  
  959
  
    
#define SPR_E500_MCSRR0  (0x23A)


  		





  
  960
  
    
#define SPR_DBAT5L       (0x23B)


  		





  
  961
  
    
#define SPR_E500_MCSRR1  (0x23B)


  		





  
  962
  
    
#define SPR_DBAT6U       (0x23C)


  		





  
  963
  
    
#define SPR_E500_MCSR    (0x23C)


  		





  
  964
  
    
#define SPR_DBAT6L       (0x23D)


  		





  
  965
  
    
#define SPR_E500_MCAR    (0x23D)


  		





  
  966
  
    
#define SPR_DBAT7U       (0x23E)


  		





  
  967
  
    
#define SPR_DBAT7L       (0x23F)


  		





  
  968
  
    
#define SPR_E500_MAS0    (0x270)


  		





  
  969
  
    
#define SPR_E500_MAS1    (0x271)


  		





  
  970
  
    
#define SPR_E500_MAS2    (0x272)


  		





  
  971
  
    
#define SPR_E500_MAS3    (0x273)


  		





  
  972
  
    
#define SPR_E500_MAS4    (0x274)


  		





  
  973
  
    
#define SPR_E500_MAS6    (0x276)


  		





  
  974
  
    
#define SPR_E500_PID1    (0x279)


  		





  
  975
  
    
#define SPR_E500_PID2    (0x27A)


  		





  
  976
  
    
#define SPR_E500_TLB0CFG (0x2B0)


  		





  
  977
  
    
#define SPR_E500_TLB1CFG (0x2B1)


  		





  
  978
  
    
#define SPR_440_INV0     (0x370)


  		





  
  979
  
    
#define SPR_440_INV1     (0x371)


  		





  
  980
  
    
#define SPR_440_INV2     (0x372)


  		





  
  981
  
    
#define SPR_440_INV3     (0x373)


  		





  
  982
  
    
#define SPR_440_IVT0     (0x374)


  		





  
  983
  
    
#define SPR_440_IVT1     (0x375)


  		





  
  984
  
    
#define SPR_440_IVT2     (0x376)


  		





  
  985
  
    
#define SPR_440_IVT3     (0x377)


  		





  
  986
  
    
#define SPR_440_DNV0     (0x390)


  		





  
  987
  
    
#define SPR_440_DNV1     (0x391)


  		





  
  988
  
    
#define SPR_440_DNV2     (0x392)


  		





  
  989
  
    
#define SPR_440_DNV3     (0x393)


  		





  
  990
  
    
#define SPR_440_DVT0     (0x394)


  		





  
  991
  
    
#define SPR_440_DVT1     (0x395)


  		





  
  992
  
    
#define SPR_440_DVT2     (0x396)


  		





  
  993
  
    
#define SPR_440_DVT3     (0x397)


  		





  
  994
  
    
#define SPR_440_DVLIM    (0x398)


  		





  
  995
  
    
#define SPR_440_IVLIM    (0x399)


  		





  
  996
  
    
#define SPR_440_RSTCFG   (0x39B)


  		





  
  997
  
    
#define SPR_440_DCBTRL   (0x39C)


  		





  
  998
  
    
#define SPR_440_DCBTRH   (0x39D)


  		





  
  999
  
    
#define SPR_440_ICBTRL   (0x39E)


  		





  
  1000
  
    
#define SPR_440_ICBTRH   (0x39F)


  		





  
  1001
  
    
#define SPR_UMMCR0       (0x3A8)


  		





  
  1002
  
    
#define SPR_UPMC1        (0x3A9)


  		





  
  1003
  
    
#define SPR_UPMC2        (0x3AA)


  		





  
  1004
  
    
#define SPR_USIA         (0x3AB)


  		





  
  1005
  
    
#define SPR_UMMCR1       (0x3AC)


  		





  
  1006
  
    
#define SPR_UPMC3        (0x3AD)


  		





  
  1007
  
    
#define SPR_UPMC4        (0x3AE)


  		





  
  1008
  
    
#define SPR_USDA         (0x3AF)


  		





  
  1009
  
    
#define SPR_40x_ZPR      (0x3B0)


  		





  
  1010
  
    
#define SPR_E500_MAS7    (0x3B0)


  		





  
  1011
  
    
#define SPR_40x_PID      (0x3B1)


  		





  
  1012
  
    
#define SPR_440_MMUCR    (0x3B2)


  		





  
  1013
  
    
#define SPR_4xx_CCR0     (0x3B3)


  		





  
  1014
  
    
#define SPR_405_IAC3     (0x3B4)


  		





  
  1015
  
    
#define SPR_405_IAC4     (0x3B5)


  		





  
  1016
  
    
#define SPR_405_DVC1     (0x3B6)


  		





  
  1017
  
    
#define SPR_405_DVC2     (0x3B7)


  		





  
  1018
  
    
#define SPR_MMCR0        (0x3B8)


  		





  
  1019
  
    
#define SPR_PMC1         (0x3B9)


  		





  
  1020
  
    
#define SPR_40x_SGR      (0x3B9)


  		





  
  1021
  
    
#define SPR_PMC2         (0x3BA)


  		





  
  1022
  
    
#define SPR_40x_DCWR     (0x3BA)


  		





  
  1023
  
    
#define SPR_SIA          (0x3BB)


  		








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