Revision 76a66253 target-ppc/translate_init.c
| b/target-ppc/translate_init.c | ||
|---|---|---|
| 1 | 1 |
/* |
| 2 | 2 |
* PowerPC CPU initialization for qemu. |
| 3 | 3 |
* |
| 4 |
* Copyright (c) 2003-2005 Jocelyn Mayer
|
|
| 4 |
* Copyright (c) 2003-2007 Jocelyn Mayer
|
|
| 5 | 5 |
* |
| 6 | 6 |
* This library is free software; you can redistribute it and/or |
| 7 | 7 |
* modify it under the terms of the GNU Lesser General Public |
| ... | ... | |
| 48 | 48 |
gen_op_store_spr(sprn); |
| 49 | 49 |
} |
| 50 | 50 |
|
| 51 |
/* SPR common to all PPC */ |
|
| 51 |
/* SPR common to all PowerPC */
|
|
| 52 | 52 |
/* XER */ |
| 53 | 53 |
static void spr_read_xer (void *opaque, int sprn) |
| 54 | 54 |
{
|
| ... | ... | |
| 93 | 93 |
gen_op_load_spr(sprn + 0x10); |
| 94 | 94 |
} |
| 95 | 95 |
|
| 96 |
/* SPR common to all non-embedded PPC (ie not 4xx) */
|
|
| 96 |
/* SPR common to all non-embedded PowerPC */
|
|
| 97 | 97 |
/* DECR */ |
| 98 |
#if !defined(CONFIG_USER_ONLY) |
|
| 98 | 99 |
static void spr_read_decr (void *opaque, int sprn) |
| 99 | 100 |
{
|
| 100 | 101 |
gen_op_load_decr(); |
| ... | ... | |
| 104 | 105 |
{
|
| 105 | 106 |
gen_op_store_decr(); |
| 106 | 107 |
} |
| 108 |
#endif |
|
| 107 | 109 |
|
| 108 |
/* SPR common to all non-embedded PPC, except 601 */ |
|
| 110 |
/* SPR common to all non-embedded PowerPC, except 601 */
|
|
| 109 | 111 |
/* Time base */ |
| 110 | 112 |
static void spr_read_tbl (void *opaque, int sprn) |
| 111 | 113 |
{
|
| 112 | 114 |
gen_op_load_tbl(); |
| 113 | 115 |
} |
| 114 | 116 |
|
| 115 |
static void spr_write_tbl (void *opaque, int sprn)
|
|
| 117 |
static void spr_read_tbu (void *opaque, int sprn)
|
|
| 116 | 118 |
{
|
| 117 |
gen_op_store_tbl();
|
|
| 119 |
gen_op_load_tbu();
|
|
| 118 | 120 |
} |
| 119 | 121 |
|
| 120 |
static void spr_read_tbu (void *opaque, int sprn) |
|
| 122 |
#if !defined(CONFIG_USER_ONLY) |
|
| 123 |
static void spr_write_tbl (void *opaque, int sprn) |
|
| 121 | 124 |
{
|
| 122 |
gen_op_load_tbu();
|
|
| 125 |
gen_op_store_tbl();
|
|
| 123 | 126 |
} |
| 124 | 127 |
|
| 125 | 128 |
static void spr_write_tbu (void *opaque, int sprn) |
| 126 | 129 |
{
|
| 127 | 130 |
gen_op_store_tbu(); |
| 128 | 131 |
} |
| 132 |
#endif |
|
| 129 | 133 |
|
| 134 |
#if !defined(CONFIG_USER_ONLY) |
|
| 130 | 135 |
/* IBAT0U...IBAT0U */ |
| 131 | 136 |
/* IBAT0L...IBAT7L */ |
| 132 | 137 |
static void spr_read_ibat (void *opaque, int sprn) |
| ... | ... | |
| 229 | 234 |
RET_STOP(ctx); |
| 230 | 235 |
} |
| 231 | 236 |
|
| 237 |
/* 64 bits PowerPC specific SPRs */ |
|
| 238 |
/* ASR */ |
|
| 239 |
#if defined(TARGET_PPC64) |
|
| 240 |
static void spr_read_asr (void *opaque, int sprn) |
|
| 241 |
{
|
|
| 242 |
gen_op_load_asr(); |
|
| 243 |
} |
|
| 244 |
|
|
| 245 |
static void spr_write_asr (void *opaque, int sprn) |
|
| 246 |
{
|
|
| 247 |
DisasContext *ctx = opaque; |
|
| 248 |
|
|
| 249 |
gen_op_store_asr(); |
|
| 250 |
RET_STOP(ctx); |
|
| 251 |
} |
|
| 252 |
#endif |
|
| 253 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
|
| 254 |
|
|
| 255 |
/* PowerPC 601 specific registers */ |
|
| 256 |
/* RTC */ |
|
| 257 |
static void spr_read_601_rtcl (void *opaque, int sprn) |
|
| 258 |
{
|
|
| 259 |
gen_op_load_601_rtcl(); |
|
| 260 |
} |
|
| 261 |
|
|
| 262 |
static void spr_read_601_rtcu (void *opaque, int sprn) |
|
| 263 |
{
|
|
| 264 |
gen_op_load_601_rtcu(); |
|
| 265 |
} |
|
| 266 |
|
|
| 267 |
#if !defined(CONFIG_USER_ONLY) |
|
| 268 |
static void spr_write_601_rtcu (void *opaque, int sprn) |
|
| 269 |
{
|
|
| 270 |
gen_op_store_601_rtcu(); |
|
| 271 |
} |
|
| 272 |
|
|
| 273 |
static void spr_write_601_rtcl (void *opaque, int sprn) |
|
| 274 |
{
|
|
| 275 |
gen_op_store_601_rtcl(); |
|
| 276 |
} |
|
| 277 |
#endif |
|
| 278 |
|
|
| 279 |
/* Unified bats */ |
|
| 280 |
#if !defined(CONFIG_USER_ONLY) |
|
| 281 |
static void spr_read_601_ubat (void *opaque, int sprn) |
|
| 282 |
{
|
|
| 283 |
gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2); |
|
| 284 |
} |
|
| 285 |
|
|
| 286 |
static void spr_write_601_ubatu (void *opaque, int sprn) |
|
| 287 |
{
|
|
| 288 |
DisasContext *ctx = opaque; |
|
| 289 |
|
|
| 290 |
gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2); |
|
| 291 |
RET_STOP(ctx); |
|
| 292 |
} |
|
| 293 |
|
|
| 294 |
static void spr_write_601_ubatl (void *opaque, int sprn) |
|
| 295 |
{
|
|
| 296 |
DisasContext *ctx = opaque; |
|
| 297 |
|
|
| 298 |
gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2); |
|
| 299 |
RET_STOP(ctx); |
|
| 300 |
} |
|
| 301 |
#endif |
|
| 302 |
|
|
| 303 |
/* PowerPC 40x specific registers */ |
|
| 304 |
#if !defined(CONFIG_USER_ONLY) |
|
| 305 |
static void spr_read_40x_pit (void *opaque, int sprn) |
|
| 306 |
{
|
|
| 307 |
gen_op_load_40x_pit(); |
|
| 308 |
} |
|
| 309 |
|
|
| 310 |
static void spr_write_40x_pit (void *opaque, int sprn) |
|
| 311 |
{
|
|
| 312 |
gen_op_store_40x_pit(); |
|
| 313 |
} |
|
| 314 |
|
|
| 315 |
static void spr_write_booke_tcr (void *opaque, int sprn) |
|
| 316 |
{
|
|
| 317 |
gen_op_store_booke_tcr(); |
|
| 318 |
} |
|
| 319 |
|
|
| 320 |
static void spr_write_booke_tsr (void *opaque, int sprn) |
|
| 321 |
{
|
|
| 322 |
gen_op_store_booke_tsr(); |
|
| 323 |
} |
|
| 324 |
#endif |
|
| 325 |
|
|
| 326 |
/* PowerPC 403 specific registers */ |
|
| 327 |
/* PBL1 / PBU1 / PBL2 / PBU2 */ |
|
| 328 |
#if !defined(CONFIG_USER_ONLY) |
|
| 329 |
static void spr_read_403_pbr (void *opaque, int sprn) |
|
| 330 |
{
|
|
| 331 |
gen_op_load_403_pb(sprn - SPR_403_PBL1); |
|
| 332 |
} |
|
| 333 |
|
|
| 334 |
static void spr_write_403_pbr (void *opaque, int sprn) |
|
| 335 |
{
|
|
| 336 |
DisasContext *ctx = opaque; |
|
| 337 |
|
|
| 338 |
gen_op_store_403_pb(sprn - SPR_403_PBL1); |
|
| 339 |
RET_STOP(ctx); |
|
| 340 |
} |
|
| 341 |
|
|
| 232 | 342 |
static void spr_write_pir (void *opaque, int sprn) |
| 233 | 343 |
{
|
| 234 | 344 |
gen_op_store_pir(); |
| 235 | 345 |
} |
| 346 |
#endif |
|
| 236 | 347 |
|
| 348 |
#if defined(CONFIG_USER_ONLY) |
|
| 349 |
#define spr_register(env, num, name, uea_read, uea_write, \ |
|
| 350 |
oea_read, oea_write, initial_value) \ |
|
| 351 |
do { \
|
|
| 352 |
_spr_register(env, num, name, uea_read, uea_write, initial_value); \ |
|
| 353 |
} while (0) |
|
| 354 |
static inline void _spr_register (CPUPPCState *env, int num, |
|
| 355 |
const unsigned char *name, |
|
| 356 |
void (*uea_read)(void *opaque, int sprn), |
|
| 357 |
void (*uea_write)(void *opaque, int sprn), |
|
| 358 |
target_ulong initial_value) |
|
| 359 |
#else |
|
| 237 | 360 |
static inline void spr_register (CPUPPCState *env, int num, |
| 238 | 361 |
const unsigned char *name, |
| 239 | 362 |
void (*uea_read)(void *opaque, int sprn), |
| ... | ... | |
| 241 | 364 |
void (*oea_read)(void *opaque, int sprn), |
| 242 | 365 |
void (*oea_write)(void *opaque, int sprn), |
| 243 | 366 |
target_ulong initial_value) |
| 367 |
#endif |
|
| 244 | 368 |
{
|
| 245 | 369 |
ppc_spr_t *spr; |
| 246 | 370 |
|
| 247 | 371 |
spr = &env->spr_cb[num]; |
| 248 | 372 |
if (spr->name != NULL ||env-> spr[num] != 0x00000000 || |
| 249 |
spr->uea_read != NULL || spr->uea_write != NULL || |
|
| 250 |
spr->oea_read != NULL || spr->oea_write != NULL) {
|
|
| 373 |
#if !defined(CONFIG_USER_ONLY) |
|
| 374 |
spr->oea_read != NULL || spr->oea_write != NULL || |
|
| 375 |
#endif |
|
| 376 |
spr->uea_read != NULL || spr->uea_write != NULL) {
|
|
| 251 | 377 |
printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
|
| 252 | 378 |
exit(1); |
| 253 | 379 |
} |
| 254 | 380 |
#if defined(PPC_DEBUG_SPR) |
| 255 |
printf("*** register spr %d (%03x) %s val %08" PRIx64 "\n", num, num, name,
|
|
| 256 |
(unsigned long long)initial_value);
|
|
| 381 |
printf("*** register spr %d (%03x) %s val " REGX "\n", num, num, name,
|
|
| 382 |
initial_value); |
|
| 257 | 383 |
#endif |
| 258 | 384 |
spr->name = name; |
| 259 | 385 |
spr->uea_read = uea_read; |
| 260 | 386 |
spr->uea_write = uea_write; |
| 387 |
#if !defined(CONFIG_USER_ONLY) |
|
| 261 | 388 |
spr->oea_read = oea_read; |
| 262 | 389 |
spr->oea_write = oea_write; |
| 390 |
#endif |
|
| 263 | 391 |
env->spr[num] = initial_value; |
| 264 | 392 |
} |
| 265 | 393 |
|
| ... | ... | |
| 493 | 621 |
0x00000000); |
| 494 | 622 |
} |
| 495 | 623 |
|
| 624 |
/* Softare table search registers */ |
|
| 625 |
static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways) |
|
| 626 |
{
|
|
| 627 |
env->nb_tlb = nb_tlbs; |
|
| 628 |
env->nb_ways = nb_ways; |
|
| 629 |
env->id_tlbs = 1; |
|
| 630 |
spr_register(env, SPR_DMISS, "DMISS", |
|
| 631 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 632 |
&spr_read_generic, SPR_NOACCESS, |
|
| 633 |
0x00000000); |
|
| 634 |
spr_register(env, SPR_DCMP, "DCMP", |
|
| 635 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 636 |
&spr_read_generic, SPR_NOACCESS, |
|
| 637 |
0x00000000); |
|
| 638 |
spr_register(env, SPR_HASH1, "HASH1", |
|
| 639 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 640 |
&spr_read_generic, SPR_NOACCESS, |
|
| 641 |
0x00000000); |
|
| 642 |
spr_register(env, SPR_HASH2, "HASH2", |
|
| 643 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 644 |
&spr_read_generic, SPR_NOACCESS, |
|
| 645 |
0x00000000); |
|
| 646 |
spr_register(env, SPR_IMISS, "IMISS", |
|
| 647 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 648 |
&spr_read_generic, SPR_NOACCESS, |
|
| 649 |
0x00000000); |
|
| 650 |
spr_register(env, SPR_ICMP, "ICMP", |
|
| 651 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 652 |
&spr_read_generic, SPR_NOACCESS, |
|
| 653 |
0x00000000); |
|
| 654 |
spr_register(env, SPR_RPA, "RPA", |
|
| 655 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 656 |
&spr_read_generic, &spr_write_generic, |
|
| 657 |
0x00000000); |
|
| 658 |
} |
|
| 659 |
|
|
| 660 |
/* SPR common to MPC755 and G2 */ |
|
| 661 |
static void gen_spr_G2_755 (CPUPPCState *env) |
|
| 662 |
{
|
|
| 663 |
/* SGPRs */ |
|
| 664 |
spr_register(env, SPR_SPRG4, "SPRG4", |
|
| 665 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 666 |
&spr_read_generic, &spr_write_generic, |
|
| 667 |
0x00000000); |
|
| 668 |
spr_register(env, SPR_SPRG5, "SPRG5", |
|
| 669 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 670 |
&spr_read_generic, &spr_write_generic, |
|
| 671 |
0x00000000); |
|
| 672 |
spr_register(env, SPR_SPRG6, "SPRG6", |
|
| 673 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 674 |
&spr_read_generic, &spr_write_generic, |
|
| 675 |
0x00000000); |
|
| 676 |
spr_register(env, SPR_SPRG7, "SPRG7", |
|
| 677 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 678 |
&spr_read_generic, &spr_write_generic, |
|
| 679 |
0x00000000); |
|
| 680 |
/* External access control */ |
|
| 681 |
/* XXX : not implemented */ |
|
| 682 |
spr_register(env, SPR_EAR, "EAR", |
|
| 683 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 684 |
&spr_read_generic, &spr_write_generic, |
|
| 685 |
0x00000000); |
|
| 686 |
} |
|
| 687 |
|
|
| 496 | 688 |
/* SPR common to all 7xx PowerPC implementations */ |
| 497 | 689 |
static void gen_spr_7xx (CPUPPCState *env) |
| 498 | 690 |
{
|
| ... | ... | |
| 513 | 705 |
SPR_NOACCESS, SPR_NOACCESS, |
| 514 | 706 |
&spr_read_generic, &spr_write_generic, |
| 515 | 707 |
0x00000000); |
| 708 |
/* XXX : not implemented */ |
|
| 709 |
spr_register(env, SPR_L2CR, "L2CR", |
|
| 710 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 711 |
&spr_read_generic, &spr_write_generic, |
|
| 712 |
0x00000000); |
|
| 516 | 713 |
/* Performance monitors */ |
| 517 | 714 |
/* XXX : not implemented */ |
| 518 | 715 |
spr_register(env, SPR_MMCR0, "MMCR0", |
| ... | ... | |
| 669 | 866 |
0x00000000); |
| 670 | 867 |
} |
| 671 | 868 |
|
| 672 |
// XXX: TODO (64 bits PPC sprs) |
|
| 673 |
/* |
|
| 674 |
* ASR => SPR 280 (64 bits) |
|
| 675 |
* FPECR => SPR 1022 (?) |
|
| 676 |
* VRSAVE => SPR 256 (Altivec) |
|
| 677 |
* SCOMC => SPR 276 (64 bits ?) |
|
| 678 |
* SCOMD => SPR 277 (64 bits ?) |
|
| 679 |
* HSPRG0 => SPR 304 (hypervisor) |
|
| 680 |
* HSPRG1 => SPR 305 (hypervisor) |
|
| 681 |
* HDEC => SPR 310 (hypervisor) |
|
| 682 |
* HIOR => SPR 311 (hypervisor) |
|
| 683 |
* RMOR => SPR 312 (970) |
|
| 684 |
* HRMOR => SPR 313 (hypervisor) |
|
| 685 |
* HSRR0 => SPR 314 (hypervisor) |
|
| 686 |
* HSRR1 => SPR 315 (hypervisor) |
|
| 687 |
* LPCR => SPR 316 (970) |
|
| 688 |
* LPIDR => SPR 317 (970) |
|
| 689 |
* ... and more (thermal management, performance counters, ...) |
|
| 690 |
*/ |
|
| 691 |
|
|
| 692 |
static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) |
|
| 869 |
/* SPR specific to PowerPC 603 implementation */ |
|
| 870 |
static void gen_spr_603 (CPUPPCState *env) |
|
| 693 | 871 |
{
|
| 694 |
/* Default MMU definitions */ |
|
| 695 |
env->nb_BATs = -1; |
|
| 696 |
env->nb_tlb = 0; |
|
| 697 |
env->nb_ways = 0; |
|
| 698 |
/* XXX: missing: |
|
| 699 |
* 32 bits PPC: |
|
| 700 |
* - MPC5xx(x) |
|
| 701 |
* - MPC8xx(x) |
|
| 702 |
* - RCPU (MPC5xx) |
|
| 703 |
*/ |
|
| 704 |
spr_register(env, SPR_PVR, "PVR", |
|
| 705 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 706 |
&spr_read_generic, SPR_NOACCESS, |
|
| 707 |
def->pvr); |
|
| 708 |
switch (def->pvr & def->pvr_mask) {
|
|
| 709 |
case CPU_PPC_604: /* PPC 604 */ |
|
| 710 |
case CPU_PPC_604E: /* PPC 604e */ |
|
| 711 |
case CPU_PPC_604R: /* PPC 604r */ |
|
| 712 |
gen_spr_generic(env); |
|
| 713 |
gen_spr_ne_601(env); |
|
| 714 |
/* Memory management */ |
|
| 715 |
gen_low_BATs(env); |
|
| 716 |
/* Time base */ |
|
| 717 |
gen_tbl(env); |
|
| 718 |
gen_spr_604(env); |
|
| 719 |
/* Hardware implementation registers */ |
|
| 720 |
/* XXX : not implemented */ |
|
| 721 |
spr_register(env, SPR_HID0, "HID0", |
|
| 722 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 723 |
&spr_read_generic, &spr_write_generic, |
|
| 724 |
0x00000000); |
|
| 725 |
/* XXX : not implemented */ |
|
| 726 |
spr_register(env, SPR_HID1, "HID1", |
|
| 727 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 728 |
&spr_read_generic, &spr_write_generic, |
|
| 729 |
0x00000000); |
|
| 730 |
break; |
|
| 731 |
|
|
| 732 |
case CPU_PPC_74x: /* PPC 740 / 750 */ |
|
| 733 |
case CPU_PPC_74xP: /* PPC 740P / 750P */ |
|
| 734 |
case CPU_PPC_750CXE: /* IBM PPC 750cxe */ |
|
| 735 |
gen_spr_generic(env); |
|
| 736 |
gen_spr_ne_601(env); |
|
| 737 |
/* Memory management */ |
|
| 738 |
gen_low_BATs(env); |
|
| 739 |
/* Time base */ |
|
| 740 |
gen_tbl(env); |
|
| 741 |
gen_spr_7xx(env); |
|
| 742 |
/* XXX : not implemented */ |
|
| 743 |
spr_register(env, SPR_L2CR, "L2CR", |
|
| 744 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 745 |
&spr_read_generic, &spr_write_generic, |
|
| 746 |
0x00000000); |
|
| 747 |
/* Hardware implementation registers */ |
|
| 748 |
/* XXX : not implemented */ |
|
| 749 |
spr_register(env, SPR_HID0, "HID0", |
|
| 750 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 751 |
&spr_read_generic, &spr_write_generic, |
|
| 752 |
0x00000000); |
|
| 753 |
/* XXX : not implemented */ |
|
| 754 |
spr_register(env, SPR_HID1, "HID1", |
|
| 755 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 756 |
&spr_read_generic, &spr_write_generic, |
|
| 757 |
0x00000000); |
|
| 758 |
break; |
|
| 759 |
|
|
| 760 |
case CPU_PPC_750FX: /* IBM PPC 750 FX */ |
|
| 761 |
case CPU_PPC_750GX: /* IBM PPC 750 GX */ |
|
| 762 |
gen_spr_generic(env); |
|
| 763 |
gen_spr_ne_601(env); |
|
| 764 |
/* Memory management */ |
|
| 765 |
gen_low_BATs(env); |
|
| 766 |
/* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ |
|
| 767 |
gen_high_BATs(env); |
|
| 768 |
/* Time base */ |
|
| 769 |
gen_tbl(env); |
|
| 770 |
gen_spr_7xx(env); |
|
| 771 |
/* XXX : not implemented */ |
|
| 772 |
spr_register(env, SPR_L2CR, "L2CR", |
|
| 773 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 774 |
&spr_read_generic, &spr_write_generic, |
|
| 775 |
0x00000000); |
|
| 776 |
/* Hardware implementation registers */ |
|
| 777 |
/* XXX : not implemented */ |
|
| 778 |
spr_register(env, SPR_HID0, "HID0", |
|
| 779 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 780 |
&spr_read_generic, &spr_write_generic, |
|
| 781 |
0x00000000); |
|
| 782 |
/* XXX : not implemented */ |
|
| 783 |
spr_register(env, SPR_HID1, "HID1", |
|
| 872 |
/* External access control */ |
|
| 873 |
/* XXX : not implemented */ |
|
| 874 |
spr_register(env, SPR_EAR, "EAR", |
|
| 784 | 875 |
SPR_NOACCESS, SPR_NOACCESS, |
| 785 |
&spr_read_generic, &spr_write_generic, |
|
| 786 |
0x00000000); |
|
| 787 |
/* XXX : not implemented */ |
|
| 788 |
spr_register(env, SPR_750_HID2, "HID2", |
|
| 789 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 790 |
&spr_read_generic, &spr_write_generic, |
|
| 791 |
0x00000000); |
|
| 792 |
break; |
|
| 793 |
|
|
| 794 |
default: |
|
| 795 |
gen_spr_generic(env); |
|
| 796 |
break; |
|
| 797 |
} |
|
| 798 |
if (env->nb_BATs == -1) |
|
| 799 |
env->nb_BATs = 4; |
|
| 876 |
&spr_read_generic, &spr_write_generic, |
|
| 877 |
0x00000000); |
|
| 800 | 878 |
} |
| 801 | 879 |
|
| 802 |
#if defined(PPC_DUMP_CPU)
|
|
| 803 |
static void dump_sprs (CPUPPCState *env)
|
|
| 880 |
/* SPR specific to PowerPC G2 implementation */
|
|
| 881 |
static void gen_spr_G2 (CPUPPCState *env)
|
|
| 804 | 882 |
{
|
| 805 |
ppc_spr_t *spr; |
|
| 806 |
uint32_t pvr = env->spr[SPR_PVR]; |
|
| 807 |
uint32_t sr, sw, ur, uw; |
|
| 808 |
int i, j, n; |
|
| 809 |
|
|
| 810 |
printf("* SPRs for PVR=%08x\n", pvr);
|
|
| 811 |
for (i = 0; i < 32; i++) {
|
|
| 812 |
for (j = 0; j < 32; j++) {
|
|
| 813 |
n = (i << 5) | j; |
|
| 814 |
spr = &env->spr_cb[n]; |
|
| 883 |
/* Memory base address */ |
|
| 884 |
/* MBAR */ |
|
| 885 |
spr_register(env, SPR_MBAR, "MBAR", |
|
| 886 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 887 |
&spr_read_generic, &spr_write_generic, |
|
| 888 |
0x00000000); |
|
| 889 |
/* System version register */ |
|
| 890 |
/* SVR */ |
|
| 891 |
spr_register(env, SPR_SVR, "SVR", |
|
| 892 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 893 |
&spr_read_generic, SPR_NOACCESS, |
|
| 894 |
0x00000000); |
|
| 895 |
/* Exception processing */ |
|
| 896 |
spr_register(env, SPR_CSRR0, "CSRR0", |
|
| 897 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 898 |
&spr_read_generic, &spr_write_generic, |
|
| 899 |
0x00000000); |
|
| 900 |
spr_register(env, SPR_CSRR1, "CSRR1", |
|
| 901 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 902 |
&spr_read_generic, &spr_write_generic, |
|
| 903 |
0x00000000); |
|
| 904 |
/* Breakpoints */ |
|
| 905 |
/* XXX : not implemented */ |
|
| 906 |
spr_register(env, SPR_DABR, "DABR", |
|
| 907 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 908 |
&spr_read_generic, &spr_write_generic, |
|
| 909 |
0x00000000); |
|
| 910 |
/* XXX : not implemented */ |
|
| 911 |
spr_register(env, SPR_DABR2, "DABR2", |
|
| 912 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 913 |
&spr_read_generic, &spr_write_generic, |
|
| 914 |
0x00000000); |
|
| 915 |
/* XXX : not implemented */ |
|
| 916 |
spr_register(env, SPR_IABR, "IABR", |
|
| 917 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 918 |
&spr_read_generic, &spr_write_generic, |
|
| 919 |
0x00000000); |
|
| 920 |
/* XXX : not implemented */ |
|
| 921 |
spr_register(env, SPR_IABR2, "IABR2", |
|
| 922 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 923 |
&spr_read_generic, &spr_write_generic, |
|
| 924 |
0x00000000); |
|
| 925 |
/* XXX : not implemented */ |
|
| 926 |
spr_register(env, SPR_IBCR, "IBCR", |
|
| 927 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 928 |
&spr_read_generic, &spr_write_generic, |
|
| 929 |
0x00000000); |
|
| 930 |
/* XXX : not implemented */ |
|
| 931 |
spr_register(env, SPR_DBCR, "DBCR", |
|
| 932 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 933 |
&spr_read_generic, &spr_write_generic, |
|
| 934 |
0x00000000); |
|
| 935 |
} |
|
| 936 |
|
|
| 937 |
/* SPR specific to PowerPC 602 implementation */ |
|
| 938 |
static void gen_spr_602 (CPUPPCState *env) |
|
| 939 |
{
|
|
| 940 |
/* ESA registers */ |
|
| 941 |
/* XXX : not implemented */ |
|
| 942 |
spr_register(env, SPR_SER, "SER", |
|
| 943 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 944 |
&spr_read_generic, &spr_write_generic, |
|
| 945 |
0x00000000); |
|
| 946 |
/* XXX : not implemented */ |
|
| 947 |
spr_register(env, SPR_SEBR, "SEBR", |
|
| 948 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 949 |
&spr_read_generic, &spr_write_generic, |
|
| 950 |
0x00000000); |
|
| 951 |
/* XXX : not implemented */ |
|
| 952 |
spr_register(env, SPR_ESASR, "ESASR", |
|
| 953 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 954 |
&spr_read_generic, &spr_write_generic, |
|
| 955 |
0x00000000); |
|
| 956 |
/* Floating point status */ |
|
| 957 |
/* XXX : not implemented */ |
|
| 958 |
spr_register(env, SPR_SP, "SP", |
|
| 959 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 960 |
&spr_read_generic, &spr_write_generic, |
|
| 961 |
0x00000000); |
|
| 962 |
/* XXX : not implemented */ |
|
| 963 |
spr_register(env, SPR_LT, "LT", |
|
| 964 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 965 |
&spr_read_generic, &spr_write_generic, |
|
| 966 |
0x00000000); |
|
| 967 |
/* Watchdog timer */ |
|
| 968 |
/* XXX : not implemented */ |
|
| 969 |
spr_register(env, SPR_TCR, "TCR", |
|
| 970 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 971 |
&spr_read_generic, &spr_write_generic, |
|
| 972 |
0x00000000); |
|
| 973 |
/* Interrupt base */ |
|
| 974 |
spr_register(env, SPR_IBR, "IBR", |
|
| 975 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 976 |
&spr_read_generic, &spr_write_generic, |
|
| 977 |
0x00000000); |
|
| 978 |
} |
|
| 979 |
|
|
| 980 |
/* SPR specific to PowerPC 601 implementation */ |
|
| 981 |
static void gen_spr_601 (CPUPPCState *env) |
|
| 982 |
{
|
|
| 983 |
/* Multiplication/division register */ |
|
| 984 |
/* MQ */ |
|
| 985 |
spr_register(env, SPR_MQ, "MQ", |
|
| 986 |
&spr_read_generic, &spr_write_generic, |
|
| 987 |
&spr_read_generic, &spr_write_generic, |
|
| 988 |
0x00000000); |
|
| 989 |
/* RTC registers */ |
|
| 990 |
spr_register(env, SPR_601_RTCU, "RTCU", |
|
| 991 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 992 |
SPR_NOACCESS, &spr_write_601_rtcu, |
|
| 993 |
0x00000000); |
|
| 994 |
spr_register(env, SPR_601_VRTCU, "RTCU", |
|
| 995 |
&spr_read_601_rtcu, SPR_NOACCESS, |
|
| 996 |
&spr_read_601_rtcu, SPR_NOACCESS, |
|
| 997 |
0x00000000); |
|
| 998 |
spr_register(env, SPR_601_RTCL, "RTCL", |
|
| 999 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1000 |
SPR_NOACCESS, &spr_write_601_rtcl, |
|
| 1001 |
0x00000000); |
|
| 1002 |
spr_register(env, SPR_601_VRTCL, "RTCL", |
|
| 1003 |
&spr_read_601_rtcl, SPR_NOACCESS, |
|
| 1004 |
&spr_read_601_rtcl, SPR_NOACCESS, |
|
| 1005 |
0x00000000); |
|
| 1006 |
/* Timer */ |
|
| 1007 |
#if 0 /* ? */ |
|
| 1008 |
spr_register(env, SPR_601_UDECR, "UDECR", |
|
| 1009 |
&spr_read_decr, SPR_NOACCESS, |
|
| 1010 |
&spr_read_decr, SPR_NOACCESS, |
|
| 1011 |
0x00000000); |
|
| 1012 |
#endif |
|
| 1013 |
/* External access control */ |
|
| 1014 |
/* XXX : not implemented */ |
|
| 1015 |
spr_register(env, SPR_EAR, "EAR", |
|
| 1016 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1017 |
&spr_read_generic, &spr_write_generic, |
|
| 1018 |
0x00000000); |
|
| 1019 |
/* Memory management */ |
|
| 1020 |
spr_register(env, SPR_IBAT0U, "IBAT0U", |
|
| 1021 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1022 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
|
| 1023 |
0x00000000); |
|
| 1024 |
spr_register(env, SPR_IBAT0L, "IBAT0L", |
|
| 1025 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1026 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
|
| 1027 |
0x00000000); |
|
| 1028 |
spr_register(env, SPR_IBAT1U, "IBAT1U", |
|
| 1029 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1030 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
|
| 1031 |
0x00000000); |
|
| 1032 |
spr_register(env, SPR_IBAT1L, "IBAT1L", |
|
| 1033 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1034 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
|
| 1035 |
0x00000000); |
|
| 1036 |
spr_register(env, SPR_IBAT2U, "IBAT2U", |
|
| 1037 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1038 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
|
| 1039 |
0x00000000); |
|
| 1040 |
spr_register(env, SPR_IBAT2L, "IBAT2L", |
|
| 1041 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1042 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
|
| 1043 |
0x00000000); |
|
| 1044 |
spr_register(env, SPR_IBAT3U, "IBAT3U", |
|
| 1045 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1046 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
|
| 1047 |
0x00000000); |
|
| 1048 |
spr_register(env, SPR_IBAT3L, "IBAT3L", |
|
| 1049 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1050 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
|
| 1051 |
0x00000000); |
|
| 1052 |
} |
|
| 1053 |
|
|
| 1054 |
/* PowerPC BookE SPR */ |
|
| 1055 |
static void gen_spr_BookE (CPUPPCState *env) |
|
| 1056 |
{
|
|
| 1057 |
/* Processor identification */ |
|
| 1058 |
spr_register(env, SPR_BOOKE_PIR, "PIR", |
|
| 1059 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1060 |
&spr_read_generic, &spr_write_pir, |
|
| 1061 |
0x00000000); |
|
| 1062 |
/* Interrupt processing */ |
|
| 1063 |
spr_register(env, SPR_CSRR0, "CSRR0", |
|
| 1064 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1065 |
&spr_read_generic, &spr_write_generic, |
|
| 1066 |
0x00000000); |
|
| 1067 |
spr_register(env, SPR_CSRR1, "CSRR1", |
|
| 1068 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1069 |
&spr_read_generic, &spr_write_generic, |
|
| 1070 |
0x00000000); |
|
| 1071 |
/* Debug */ |
|
| 1072 |
/* XXX : not implemented */ |
|
| 1073 |
spr_register(env, SPR_BOOKE_IAC1, "IAC1", |
|
| 1074 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1075 |
&spr_read_generic, &spr_write_generic, |
|
| 1076 |
0x00000000); |
|
| 1077 |
/* XXX : not implemented */ |
|
| 1078 |
spr_register(env, SPR_BOOKE_IAC2, "IAC2", |
|
| 1079 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1080 |
&spr_read_generic, &spr_write_generic, |
|
| 1081 |
0x00000000); |
|
| 1082 |
/* XXX : not implemented */ |
|
| 1083 |
spr_register(env, SPR_BOOKE_IAC3, "IAC3", |
|
| 1084 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1085 |
&spr_read_generic, &spr_write_generic, |
|
| 1086 |
0x00000000); |
|
| 1087 |
/* XXX : not implemented */ |
|
| 1088 |
spr_register(env, SPR_BOOKE_IAC4, "IAC4", |
|
| 1089 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1090 |
&spr_read_generic, &spr_write_generic, |
|
| 1091 |
0x00000000); |
|
| 1092 |
/* XXX : not implemented */ |
|
| 1093 |
spr_register(env, SPR_BOOKE_DAC1, "DAC1", |
|
| 1094 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1095 |
&spr_read_generic, &spr_write_generic, |
|
| 1096 |
0x00000000); |
|
| 1097 |
/* XXX : not implemented */ |
|
| 1098 |
spr_register(env, SPR_BOOKE_DAC2, "DAC2", |
|
| 1099 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1100 |
&spr_read_generic, &spr_write_generic, |
|
| 1101 |
0x00000000); |
|
| 1102 |
/* XXX : not implemented */ |
|
| 1103 |
spr_register(env, SPR_BOOKE_DVC1, "DVC1", |
|
| 1104 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1105 |
&spr_read_generic, &spr_write_generic, |
|
| 1106 |
0x00000000); |
|
| 1107 |
/* XXX : not implemented */ |
|
| 1108 |
spr_register(env, SPR_BOOKE_DVC2, "DVC2", |
|
| 1109 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1110 |
&spr_read_generic, &spr_write_generic, |
|
| 1111 |
0x00000000); |
|
| 1112 |
/* XXX : not implemented */ |
|
| 1113 |
spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", |
|
| 1114 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1115 |
&spr_read_generic, &spr_write_generic, |
|
| 1116 |
0x00000000); |
|
| 1117 |
/* XXX : not implemented */ |
|
| 1118 |
spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", |
|
| 1119 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1120 |
&spr_read_generic, &spr_write_generic, |
|
| 1121 |
0x00000000); |
|
| 1122 |
/* XXX : not implemented */ |
|
| 1123 |
spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", |
|
| 1124 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1125 |
&spr_read_generic, &spr_write_generic, |
|
| 1126 |
0x00000000); |
|
| 1127 |
/* XXX : not implemented */ |
|
| 1128 |
spr_register(env, SPR_BOOKE_DBSR, "DBSR", |
|
| 1129 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1130 |
&spr_read_generic, &spr_write_generic, |
|
| 1131 |
0x00000000); |
|
| 1132 |
spr_register(env, SPR_BOOKE_DEAR, "DEAR", |
|
| 1133 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1134 |
&spr_read_generic, &spr_write_generic, |
|
| 1135 |
0x00000000); |
|
| 1136 |
spr_register(env, SPR_BOOKE_ESR, "ESR", |
|
| 1137 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1138 |
&spr_read_generic, &spr_write_generic, |
|
| 1139 |
0x00000000); |
|
| 1140 |
spr_register(env, SPR_BOOKE_EVPR, "EVPR", |
|
| 1141 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1142 |
&spr_read_generic, &spr_write_generic, |
|
| 1143 |
0x00000000); |
|
| 1144 |
spr_register(env, SPR_BOOKE_IVOR0, "IVOR0", |
|
| 1145 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1146 |
&spr_read_generic, &spr_write_generic, |
|
| 1147 |
0x00000000); |
|
| 1148 |
spr_register(env, SPR_BOOKE_IVOR1, "IVOR1", |
|
| 1149 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1150 |
&spr_read_generic, &spr_write_generic, |
|
| 1151 |
0x00000000); |
|
| 1152 |
spr_register(env, SPR_BOOKE_IVOR2, "IVOR2", |
|
| 1153 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1154 |
&spr_read_generic, &spr_write_generic, |
|
| 1155 |
0x00000000); |
|
| 1156 |
spr_register(env, SPR_BOOKE_IVOR3, "IVOR3", |
|
| 1157 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1158 |
&spr_read_generic, &spr_write_generic, |
|
| 1159 |
0x00000000); |
|
| 1160 |
spr_register(env, SPR_BOOKE_IVOR4, "IVOR4", |
|
| 1161 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1162 |
&spr_read_generic, &spr_write_generic, |
|
| 1163 |
0x00000000); |
|
| 1164 |
spr_register(env, SPR_BOOKE_IVOR5, "IVOR5", |
|
| 1165 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1166 |
&spr_read_generic, &spr_write_generic, |
|
| 1167 |
0x00000000); |
|
| 1168 |
spr_register(env, SPR_BOOKE_IVOR6, "IVOR6", |
|
| 1169 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1170 |
&spr_read_generic, &spr_write_generic, |
|
| 1171 |
0x00000000); |
|
| 1172 |
spr_register(env, SPR_BOOKE_IVOR7, "IVOR7", |
|
| 1173 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1174 |
&spr_read_generic, &spr_write_generic, |
|
| 1175 |
0x00000000); |
|
| 1176 |
spr_register(env, SPR_BOOKE_IVOR8, "IVOR8", |
|
| 1177 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1178 |
&spr_read_generic, &spr_write_generic, |
|
| 1179 |
0x00000000); |
|
| 1180 |
spr_register(env, SPR_BOOKE_IVOR9, "IVOR9", |
|
| 1181 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1182 |
&spr_read_generic, &spr_write_generic, |
|
| 1183 |
0x00000000); |
|
| 1184 |
spr_register(env, SPR_BOOKE_IVOR10, "IVOR10", |
|
| 1185 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1186 |
&spr_read_generic, &spr_write_generic, |
|
| 1187 |
0x00000000); |
|
| 1188 |
spr_register(env, SPR_BOOKE_IVOR11, "IVOR11", |
|
| 1189 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1190 |
&spr_read_generic, &spr_write_generic, |
|
| 1191 |
0x00000000); |
|
| 1192 |
spr_register(env, SPR_BOOKE_IVOR12, "IVOR12", |
|
| 1193 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1194 |
&spr_read_generic, &spr_write_generic, |
|
| 1195 |
0x00000000); |
|
| 1196 |
spr_register(env, SPR_BOOKE_IVOR13, "IVOR13", |
|
| 1197 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1198 |
&spr_read_generic, &spr_write_generic, |
|
| 1199 |
0x00000000); |
|
| 1200 |
spr_register(env, SPR_BOOKE_IVOR14, "IVOR14", |
|
| 1201 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1202 |
&spr_read_generic, &spr_write_generic, |
|
| 1203 |
0x00000000); |
|
| 1204 |
spr_register(env, SPR_BOOKE_IVOR15, "IVOR15", |
|
| 1205 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1206 |
&spr_read_generic, &spr_write_generic, |
|
| 1207 |
0x00000000); |
|
| 1208 |
spr_register(env, SPR_BOOKE_PID, "PID", |
|
| 1209 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1210 |
&spr_read_generic, &spr_write_generic, |
|
| 1211 |
0x00000000); |
|
| 1212 |
spr_register(env, SPR_BOOKE_TCR, "TCR", |
|
| 1213 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1214 |
&spr_read_generic, &spr_write_booke_tcr, |
|
| 1215 |
0x00000000); |
|
| 1216 |
spr_register(env, SPR_BOOKE_TSR, "TSR", |
|
| 1217 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1218 |
&spr_read_generic, &spr_write_booke_tsr, |
|
| 1219 |
0x00000000); |
|
| 1220 |
/* Timer */ |
|
| 1221 |
spr_register(env, SPR_DECR, "DECR", |
|
| 1222 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1223 |
&spr_read_decr, &spr_write_decr, |
|
| 1224 |
0x00000000); |
|
| 1225 |
spr_register(env, SPR_BOOKE_DECAR, "DECAR", |
|
| 1226 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1227 |
SPR_NOACCESS, &spr_write_generic, |
|
| 1228 |
0x00000000); |
|
| 1229 |
/* SPRGs */ |
|
| 1230 |
spr_register(env, SPR_USPRG0, "USPRG0", |
|
| 1231 |
&spr_read_generic, &spr_write_generic, |
|
| 1232 |
&spr_read_generic, &spr_write_generic, |
|
| 1233 |
0x00000000); |
|
| 1234 |
spr_register(env, SPR_SPRG4, "SPRG4", |
|
| 1235 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1236 |
&spr_read_generic, &spr_write_generic, |
|
| 1237 |
0x00000000); |
|
| 1238 |
spr_register(env, SPR_USPRG4, "USPRG4", |
|
| 1239 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1240 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1241 |
0x00000000); |
|
| 1242 |
spr_register(env, SPR_SPRG5, "SPRG5", |
|
| 1243 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1244 |
&spr_read_generic, &spr_write_generic, |
|
| 1245 |
0x00000000); |
|
| 1246 |
spr_register(env, SPR_USPRG5, "USPRG5", |
|
| 1247 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1248 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1249 |
0x00000000); |
|
| 1250 |
spr_register(env, SPR_SPRG6, "SPRG6", |
|
| 1251 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1252 |
&spr_read_generic, &spr_write_generic, |
|
| 1253 |
0x00000000); |
|
| 1254 |
spr_register(env, SPR_USPRG6, "USPRG6", |
|
| 1255 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1256 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1257 |
0x00000000); |
|
| 1258 |
spr_register(env, SPR_SPRG7, "SPRG7", |
|
| 1259 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1260 |
&spr_read_generic, &spr_write_generic, |
|
| 1261 |
0x00000000); |
|
| 1262 |
spr_register(env, SPR_USPRG7, "USPRG7", |
|
| 1263 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1264 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1265 |
0x00000000); |
|
| 1266 |
} |
|
| 1267 |
|
|
| 1268 |
/* SPR specific to PowerPC 440 implementation */ |
|
| 1269 |
static void gen_spr_440 (CPUPPCState *env) |
|
| 1270 |
{
|
|
| 1271 |
/* Cache control */ |
|
| 1272 |
/* XXX : not implemented */ |
|
| 1273 |
spr_register(env, SPR_440_DNV0, "DNV0", |
|
| 1274 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1275 |
&spr_read_generic, &spr_write_generic, |
|
| 1276 |
0x00000000); |
|
| 1277 |
/* XXX : not implemented */ |
|
| 1278 |
spr_register(env, SPR_440_DNV1, "DNV1", |
|
| 1279 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1280 |
&spr_read_generic, &spr_write_generic, |
|
| 1281 |
0x00000000); |
|
| 1282 |
/* XXX : not implemented */ |
|
| 1283 |
spr_register(env, SPR_440_DNV2, "DNV2", |
|
| 1284 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1285 |
&spr_read_generic, &spr_write_generic, |
|
| 1286 |
0x00000000); |
|
| 1287 |
/* XXX : not implemented */ |
|
| 1288 |
spr_register(env, SPR_440_DNV3, "DNV3", |
|
| 1289 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1290 |
&spr_read_generic, &spr_write_generic, |
|
| 1291 |
0x00000000); |
|
| 1292 |
/* XXX : not implemented */ |
|
| 1293 |
spr_register(env, SPR_440_DVT0, "DVT0", |
|
| 1294 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1295 |
&spr_read_generic, &spr_write_generic, |
|
| 1296 |
0x00000000); |
|
| 1297 |
/* XXX : not implemented */ |
|
| 1298 |
spr_register(env, SPR_440_DVT1, "DVT1", |
|
| 1299 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1300 |
&spr_read_generic, &spr_write_generic, |
|
| 1301 |
0x00000000); |
|
| 1302 |
/* XXX : not implemented */ |
|
| 1303 |
spr_register(env, SPR_440_DVT2, "DVT2", |
|
| 1304 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1305 |
&spr_read_generic, &spr_write_generic, |
|
| 1306 |
0x00000000); |
|
| 1307 |
/* XXX : not implemented */ |
|
| 1308 |
spr_register(env, SPR_440_DVT3, "DVT3", |
|
| 1309 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1310 |
&spr_read_generic, &spr_write_generic, |
|
| 1311 |
0x00000000); |
|
| 1312 |
/* XXX : not implemented */ |
|
| 1313 |
spr_register(env, SPR_440_DVLIM, "DVLIM", |
|
| 1314 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1315 |
&spr_read_generic, &spr_write_generic, |
|
| 1316 |
0x00000000); |
|
| 1317 |
/* XXX : not implemented */ |
|
| 1318 |
spr_register(env, SPR_440_INV0, "INV0", |
|
| 1319 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1320 |
&spr_read_generic, &spr_write_generic, |
|
| 1321 |
0x00000000); |
|
| 1322 |
/* XXX : not implemented */ |
|
| 1323 |
spr_register(env, SPR_440_INV1, "INV1", |
|
| 1324 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1325 |
&spr_read_generic, &spr_write_generic, |
|
| 1326 |
0x00000000); |
|
| 1327 |
/* XXX : not implemented */ |
|
| 1328 |
spr_register(env, SPR_440_INV2, "INV2", |
|
| 1329 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1330 |
&spr_read_generic, &spr_write_generic, |
|
| 1331 |
0x00000000); |
|
| 1332 |
/* XXX : not implemented */ |
|
| 1333 |
spr_register(env, SPR_440_INV3, "INV3", |
|
| 1334 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1335 |
&spr_read_generic, &spr_write_generic, |
|
| 1336 |
0x00000000); |
|
| 1337 |
/* XXX : not implemented */ |
|
| 1338 |
spr_register(env, SPR_440_IVT0, "IVT0", |
|
| 1339 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1340 |
&spr_read_generic, &spr_write_generic, |
|
| 1341 |
0x00000000); |
|
| 1342 |
/* XXX : not implemented */ |
|
| 1343 |
spr_register(env, SPR_440_IVT1, "IVT1", |
|
| 1344 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1345 |
&spr_read_generic, &spr_write_generic, |
|
| 1346 |
0x00000000); |
|
| 1347 |
/* XXX : not implemented */ |
|
| 1348 |
spr_register(env, SPR_440_IVT2, "IVT2", |
|
| 1349 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1350 |
&spr_read_generic, &spr_write_generic, |
|
| 1351 |
0x00000000); |
|
| 1352 |
/* XXX : not implemented */ |
|
| 1353 |
spr_register(env, SPR_440_IVT3, "IVT3", |
|
| 1354 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1355 |
&spr_read_generic, &spr_write_generic, |
|
| 1356 |
0x00000000); |
|
| 1357 |
/* XXX : not implemented */ |
|
| 1358 |
spr_register(env, SPR_440_IVLIM, "IVLIM", |
|
| 1359 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1360 |
&spr_read_generic, &spr_write_generic, |
|
| 1361 |
0x00000000); |
|
| 1362 |
/* Cache debug */ |
|
| 1363 |
/* XXX : not implemented */ |
|
| 1364 |
spr_register(env, SPR_440_DCBTRH, "DCBTRH", |
|
| 1365 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1366 |
&spr_read_generic, SPR_NOACCESS, |
|
| 1367 |
0x00000000); |
|
| 1368 |
/* XXX : not implemented */ |
|
| 1369 |
spr_register(env, SPR_440_DCBTRL, "DCBTRL", |
|
| 1370 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1371 |
&spr_read_generic, SPR_NOACCESS, |
|
| 1372 |
0x00000000); |
|
| 1373 |
/* XXX : not implemented */ |
|
| 1374 |
spr_register(env, SPR_4xx_ICDBDR, "ICDBDR", |
|
| 1375 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1376 |
&spr_read_generic, SPR_NOACCESS, |
|
| 1377 |
0x00000000); |
|
| 1378 |
/* XXX : not implemented */ |
|
| 1379 |
spr_register(env, SPR_440_ICBTRH, "ICBTRH", |
|
| 1380 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1381 |
&spr_read_generic, SPR_NOACCESS, |
|
| 1382 |
0x00000000); |
|
| 1383 |
/* XXX : not implemented */ |
|
| 1384 |
spr_register(env, SPR_440_ICBTRL, "ICBTRL", |
|
| 1385 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1386 |
&spr_read_generic, SPR_NOACCESS, |
|
| 1387 |
0x00000000); |
|
| 1388 |
/* XXX : not implemented */ |
|
| 1389 |
spr_register(env, SPR_440_DBDR, "DBDR", |
|
| 1390 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1391 |
&spr_read_generic, &spr_write_generic, |
|
| 1392 |
0x00000000); |
|
| 1393 |
/* Processor control */ |
|
| 1394 |
spr_register(env, SPR_4xx_CCR0, "CCR0", |
|
| 1395 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1396 |
&spr_read_generic, &spr_write_generic, |
|
| 1397 |
0x00000000); |
|
| 1398 |
spr_register(env, SPR_440_RSTCFG, "RSTCFG", |
|
| 1399 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1400 |
&spr_read_generic, SPR_NOACCESS, |
|
| 1401 |
0x00000000); |
|
| 1402 |
/* Storage control */ |
|
| 1403 |
spr_register(env, SPR_440_MMUCR, "MMUCR", |
|
| 1404 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1405 |
&spr_read_generic, &spr_write_generic, |
|
| 1406 |
0x00000000); |
|
| 1407 |
} |
|
| 1408 |
|
|
| 1409 |
/* SPR shared between PowerPC 40x implementations */ |
|
| 1410 |
static void gen_spr_40x (CPUPPCState *env) |
|
| 1411 |
{
|
|
| 1412 |
/* Cache */ |
|
| 1413 |
/* XXX : not implemented */ |
|
| 1414 |
spr_register(env, SPR_40x_DCCR, "DCCR", |
|
| 1415 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1416 |
&spr_read_generic, &spr_write_generic, |
|
| 1417 |
0x00000000); |
|
| 1418 |
/* XXX : not implemented */ |
|
| 1419 |
spr_register(env, SPR_40x_DCWR, "DCWR", |
|
| 1420 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1421 |
&spr_read_generic, &spr_write_generic, |
|
| 1422 |
0x00000000); |
|
| 1423 |
/* XXX : not implemented */ |
|
| 1424 |
spr_register(env, SPR_40x_ICCR, "ICCR", |
|
| 1425 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1426 |
&spr_read_generic, &spr_write_generic, |
|
| 1427 |
0x00000000); |
|
| 1428 |
/* XXX : not implemented */ |
|
| 1429 |
spr_register(env, SPR_4xx_ICDBDR, "ICDBDR", |
|
| 1430 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1431 |
&spr_read_generic, SPR_NOACCESS, |
|
| 1432 |
0x00000000); |
|
| 1433 |
/* Bus access control */ |
|
| 1434 |
spr_register(env, SPR_40x_SGR, "SGR", |
|
| 1435 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1436 |
&spr_read_generic, &spr_write_generic, |
|
| 1437 |
0xFFFFFFFF); |
|
| 1438 |
spr_register(env, SPR_40x_ZPR, "ZPR", |
|
| 1439 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1440 |
&spr_read_generic, &spr_write_generic, |
|
| 1441 |
0x00000000); |
|
| 1442 |
/* MMU */ |
|
| 1443 |
spr_register(env, SPR_40x_PID, "PID", |
|
| 1444 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1445 |
&spr_read_generic, &spr_write_generic, |
|
| 1446 |
0x00000000); |
|
| 1447 |
/* Exception */ |
|
| 1448 |
spr_register(env, SPR_40x_DEAR, "DEAR", |
|
| 1449 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1450 |
&spr_read_generic, &spr_write_generic, |
|
| 1451 |
0x00000000); |
|
| 1452 |
spr_register(env, SPR_40x_ESR, "ESR", |
|
| 1453 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1454 |
&spr_read_generic, &spr_write_generic, |
|
| 1455 |
0x00000000); |
|
| 1456 |
spr_register(env, SPR_40x_EVPR, "EVPR", |
|
| 1457 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1458 |
&spr_read_generic, &spr_write_generic, |
|
| 1459 |
0x00000000); |
|
| 1460 |
spr_register(env, SPR_40x_SRR2, "SRR2", |
|
| 1461 |
&spr_read_generic, &spr_write_generic, |
|
| 1462 |
&spr_read_generic, &spr_write_generic, |
|
| 1463 |
0x00000000); |
|
| 1464 |
spr_register(env, SPR_40x_SRR3, "SRR3", |
|
| 1465 |
&spr_read_generic, &spr_write_generic, |
|
| 1466 |
&spr_read_generic, &spr_write_generic, |
|
| 1467 |
0x00000000); |
|
| 1468 |
/* Timers */ |
|
| 1469 |
spr_register(env, SPR_40x_PIT, "PIT", |
|
| 1470 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1471 |
&spr_read_40x_pit, &spr_write_40x_pit, |
|
| 1472 |
0x00000000); |
|
| 1473 |
spr_register(env, SPR_40x_TCR, "TCR", |
|
| 1474 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1475 |
&spr_read_generic, &spr_write_booke_tcr, |
|
| 1476 |
0x00000000); |
|
| 1477 |
spr_register(env, SPR_40x_TSR, "TSR", |
|
| 1478 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1479 |
&spr_read_generic, &spr_write_booke_tsr, |
|
| 1480 |
0x00000000); |
|
| 1481 |
/* Debug interface */ |
|
| 1482 |
/* XXX : not implemented */ |
|
| 1483 |
spr_register(env, SPR_40x_DAC1, "DAC1", |
|
| 1484 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1485 |
&spr_read_generic, &spr_write_generic, |
|
| 1486 |
0x00000000); |
|
| 1487 |
spr_register(env, SPR_40x_DAC2, "DAC2", |
|
| 1488 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1489 |
&spr_read_generic, &spr_write_generic, |
|
| 1490 |
0x00000000); |
|
| 1491 |
/* XXX : not implemented */ |
|
| 1492 |
spr_register(env, SPR_40x_DBCR0, "DBCR0", |
|
| 1493 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1494 |
&spr_read_generic, &spr_write_generic, |
|
| 1495 |
0x00000000); |
|
| 1496 |
/* XXX : not implemented */ |
|
| 1497 |
spr_register(env, SPR_40x_DBSR, "DBSR", |
|
| 1498 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1499 |
&spr_read_generic, &spr_write_generic, |
|
| 1500 |
/* Last reset was system reset (system boot */ |
|
| 1501 |
0x00000300); |
|
| 1502 |
/* XXX : not implemented */ |
|
| 1503 |
spr_register(env, SPR_40x_IAC1, "IAC1", |
|
| 1504 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1505 |
&spr_read_generic, &spr_write_generic, |
|
| 1506 |
0x00000000); |
|
| 1507 |
spr_register(env, SPR_40x_IAC2, "IAC2", |
|
| 1508 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1509 |
&spr_read_generic, &spr_write_generic, |
|
| 1510 |
0x00000000); |
|
| 1511 |
} |
|
| 1512 |
|
|
| 1513 |
/* SPR specific to PowerPC 405 implementation */ |
|
| 1514 |
static void gen_spr_405 (CPUPPCState *env) |
|
| 1515 |
{
|
|
| 1516 |
spr_register(env, SPR_4xx_CCR0, "CCR0", |
|
| 1517 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1518 |
&spr_read_generic, &spr_write_generic, |
|
| 1519 |
0x00700000); |
|
| 1520 |
/* Debug */ |
|
| 1521 |
/* XXX : not implemented */ |
|
| 1522 |
spr_register(env, SPR_405_DBCR1, "DBCR1", |
|
| 1523 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1524 |
&spr_read_generic, &spr_write_generic, |
|
| 1525 |
0x00000000); |
|
| 1526 |
/* XXX : not implemented */ |
|
| 1527 |
spr_register(env, SPR_405_DVC1, "DVC1", |
|
| 1528 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1529 |
&spr_read_generic, &spr_write_generic, |
|
| 1530 |
0x00000000); |
|
| 1531 |
/* XXX : not implemented */ |
|
| 1532 |
spr_register(env, SPR_405_DVC2, "DVC2", |
|
| 1533 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1534 |
&spr_read_generic, &spr_write_generic, |
|
| 1535 |
0x00000000); |
|
| 1536 |
/* XXX : not implemented */ |
|
| 1537 |
spr_register(env, SPR_405_IAC3, "IAC3", |
|
| 1538 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1539 |
&spr_read_generic, &spr_write_generic, |
|
| 1540 |
0x00000000); |
|
| 1541 |
/* XXX : not implemented */ |
|
| 1542 |
spr_register(env, SPR_405_IAC4, "IAC4", |
|
| 1543 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1544 |
&spr_read_generic, &spr_write_generic, |
|
| 1545 |
0x00000000); |
|
| 1546 |
/* Storage control */ |
|
| 1547 |
/* XXX : not implemented */ |
|
| 1548 |
spr_register(env, SPR_405_SLER, "SLER", |
|
| 1549 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1550 |
&spr_read_generic, &spr_write_generic, |
|
| 1551 |
0x00000000); |
|
| 1552 |
/* XXX : not implemented */ |
|
| 1553 |
spr_register(env, SPR_405_SU0R, "SU0R", |
|
| 1554 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1555 |
&spr_read_generic, &spr_write_generic, |
|
| 1556 |
0x00000000); |
|
| 1557 |
/* SPRG */ |
|
| 1558 |
spr_register(env, SPR_USPRG0, "USPRG0", |
|
| 1559 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1560 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1561 |
0x00000000); |
|
| 1562 |
spr_register(env, SPR_SPRG4, "SPRG4", |
|
| 1563 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1564 |
SPR_NOACCESS, &spr_write_generic, |
|
| 1565 |
0x00000000); |
|
| 1566 |
spr_register(env, SPR_USPRG4, "USPRG4", |
|
| 1567 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1568 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1569 |
0x00000000); |
|
| 1570 |
spr_register(env, SPR_SPRG5, "SPRG5", |
|
| 1571 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1572 |
SPR_NOACCESS, &spr_write_generic, |
|
| 1573 |
0x00000000); |
|
| 1574 |
spr_register(env, SPR_USPRG5, "USPRG5", |
|
| 1575 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1576 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1577 |
0x00000000); |
|
| 1578 |
spr_register(env, SPR_SPRG6, "SPRG6", |
|
| 1579 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1580 |
SPR_NOACCESS, &spr_write_generic, |
|
| 1581 |
0x00000000); |
|
| 1582 |
spr_register(env, SPR_USPRG6, "USPRG6", |
|
| 1583 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1584 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1585 |
0x00000000); |
|
| 1586 |
spr_register(env, SPR_SPRG7, "SPRG7", |
|
| 1587 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1588 |
SPR_NOACCESS, &spr_write_generic, |
|
| 1589 |
0x00000000); |
|
| 1590 |
spr_register(env, SPR_USPRG7, "USPRG7", |
|
| 1591 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1592 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1593 |
0x00000000); |
|
| 1594 |
/* Debug */ |
|
| 1595 |
/* XXX : not implemented */ |
|
| 1596 |
spr_register(env, SPR_40x_DAC2, "DAC2", |
|
| 1597 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1598 |
&spr_read_generic, &spr_write_generic, |
|
| 1599 |
0x00000000); |
|
| 1600 |
/* XXX : not implemented */ |
|
| 1601 |
spr_register(env, SPR_40x_IAC2, "IAC2", |
|
| 1602 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1603 |
&spr_read_generic, &spr_write_generic, |
|
| 1604 |
0x00000000); |
|
| 1605 |
} |
|
| 1606 |
|
|
| 1607 |
/* SPR shared between PowerPC 401 & 403 implementations */ |
|
| 1608 |
static void gen_spr_401_403 (CPUPPCState *env) |
|
| 1609 |
{
|
|
| 1610 |
/* Time base */ |
|
| 1611 |
spr_register(env, SPR_403_VTBL, "TBL", |
|
| 1612 |
&spr_read_tbl, SPR_NOACCESS, |
|
| 1613 |
&spr_read_tbl, SPR_NOACCESS, |
|
| 1614 |
0x00000000); |
|
| 1615 |
spr_register(env, SPR_403_TBL, "TBL", |
|
| 1616 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1617 |
SPR_NOACCESS, &spr_write_tbl, |
|
| 1618 |
0x00000000); |
|
| 1619 |
spr_register(env, SPR_403_VTBU, "TBU", |
|
| 1620 |
&spr_read_tbu, SPR_NOACCESS, |
|
| 1621 |
&spr_read_tbu, SPR_NOACCESS, |
|
| 1622 |
0x00000000); |
|
| 1623 |
spr_register(env, SPR_403_TBU, "TBU", |
|
| 1624 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1625 |
SPR_NOACCESS, &spr_write_tbu, |
|
| 1626 |
0x00000000); |
|
| 1627 |
/* Debug */ |
|
| 1628 |
/* XXX: not implemented */ |
|
| 1629 |
spr_register(env, SPR_403_CDBCR, "CDBCR", |
|
| 1630 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1631 |
&spr_read_generic, &spr_write_generic, |
|
| 1632 |
0x00000000); |
|
| 1633 |
} |
|
| 1634 |
|
|
| 1635 |
/* SPR specific to PowerPC 403 implementation */ |
|
| 1636 |
static void gen_spr_403 (CPUPPCState *env) |
|
| 1637 |
{
|
|
| 1638 |
/* MMU */ |
|
| 1639 |
spr_register(env, SPR_403_PBL1, "PBL1", |
|
| 1640 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1641 |
&spr_read_403_pbr, &spr_write_403_pbr, |
|
| 1642 |
0x00000000); |
|
| 1643 |
spr_register(env, SPR_403_PBU1, "PBU1", |
|
| 1644 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1645 |
&spr_read_403_pbr, &spr_write_403_pbr, |
|
| 1646 |
0x00000000); |
|
| 1647 |
spr_register(env, SPR_403_PBL2, "PBL2", |
|
| 1648 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1649 |
&spr_read_403_pbr, &spr_write_403_pbr, |
|
| 1650 |
0x00000000); |
|
| 1651 |
spr_register(env, SPR_403_PBU2, "PBU2", |
|
| 1652 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1653 |
&spr_read_403_pbr, &spr_write_403_pbr, |
|
| 1654 |
0x00000000); |
|
| 1655 |
/* Debug */ |
|
| 1656 |
/* XXX : not implemented */ |
|
| 1657 |
spr_register(env, SPR_40x_DAC2, "DAC2", |
|
| 1658 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1659 |
&spr_read_generic, &spr_write_generic, |
|
| 1660 |
0x00000000); |
|
| 1661 |
/* XXX : not implemented */ |
|
| 1662 |
spr_register(env, SPR_40x_IAC2, "IAC2", |
|
| 1663 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1664 |
&spr_read_generic, &spr_write_generic, |
|
| 1665 |
0x00000000); |
|
| 1666 |
} |
|
| 1667 |
|
|
| 1668 |
/* SPR specific to PowerPC compression coprocessor extension */ |
|
| 1669 |
#if defined (TODO) |
|
| 1670 |
static void gen_spr_compress (CPUPPCState *env) |
|
| 1671 |
{
|
|
| 1672 |
spr_register(env, SPR_401_SKR, "SKR", |
|
| 1673 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1674 |
&spr_read_generic, &spr_write_generic, |
|
| 1675 |
0x00000000); |
|
| 1676 |
} |
|
| 1677 |
#endif |
|
| 1678 |
|
|
| 1679 |
// XXX: TODO (64 bits PowerPC SPRs) |
|
| 1680 |
/* |
|
| 1681 |
* ASR => SPR 280 (64 bits) |
|
| 1682 |
* FPECR => SPR 1022 (?) |
|
| 1683 |
* VRSAVE => SPR 256 (Altivec) |
|
| 1684 |
* SCOMC => SPR 276 (64 bits ?) |
|
| 1685 |
* SCOMD => SPR 277 (64 bits ?) |
|
| 1686 |
* HSPRG0 => SPR 304 (hypervisor) |
|
| 1687 |
* HSPRG1 => SPR 305 (hypervisor) |
|
| 1688 |
* HDEC => SPR 310 (hypervisor) |
|
| 1689 |
* HIOR => SPR 311 (hypervisor) |
|
| 1690 |
* RMOR => SPR 312 (970) |
|
| 1691 |
* HRMOR => SPR 313 (hypervisor) |
|
| 1692 |
* HSRR0 => SPR 314 (hypervisor) |
|
| 1693 |
* HSRR1 => SPR 315 (hypervisor) |
|
| 1694 |
* LPCR => SPR 316 (970) |
|
| 1695 |
* LPIDR => SPR 317 (970) |
|
| 1696 |
* ... and more (thermal management, performance counters, ...) |
|
| 1697 |
*/ |
|
| 1698 |
|
|
| 1699 |
static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) |
|
| 1700 |
{
|
|
| 1701 |
env->reserve = -1; |
|
| 1702 |
/* Default MMU definitions */ |
|
| 1703 |
env->nb_BATs = -1; |
|
| 1704 |
env->nb_tlb = 0; |
|
| 1705 |
env->nb_ways = 0; |
|
| 1706 |
/* XXX: missing: |
|
| 1707 |
* 32 bits PowerPC: |
|
| 1708 |
* - MPC5xx(x) |
|
| 1709 |
* - MPC8xx(x) |
|
| 1710 |
* - RCPU (same as MPC5xx ?) |
|
| 1711 |
*/ |
|
| 1712 |
spr_register(env, SPR_PVR, "PVR", |
|
| 1713 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1714 |
&spr_read_generic, SPR_NOACCESS, |
|
| 1715 |
def->pvr); |
|
| 1716 |
printf("%s: PVR %08x mask %08x => %08x\n", __func__,
|
|
| 1717 |
def->pvr, def->pvr_mask, def->pvr & def->pvr_mask); |
|
| 1718 |
switch (def->pvr & def->pvr_mask) {
|
|
| 1719 |
/* Embedded PowerPC from IBM */ |
|
| 1720 |
case CPU_PPC_401A1: /* 401 A1 family */ |
|
| 1721 |
case CPU_PPC_401B2: /* 401 B2 family */ |
|
| 1722 |
case CPU_PPC_401C2: /* 401 C2 family */ |
|
| 1723 |
case CPU_PPC_401D2: /* 401 D2 family */ |
|
| 1724 |
case CPU_PPC_401E2: /* 401 E2 family */ |
|
| 1725 |
case CPU_PPC_401F2: /* 401 F2 family */ |
|
| 1726 |
case CPU_PPC_401G2: /* 401 G2 family */ |
|
| 1727 |
case CPU_PPC_IOP480: /* IOP 480 family */ |
|
| 1728 |
case CPU_PPC_COBRA: /* IBM Processor for Network Resources */ |
|
| 1729 |
gen_spr_generic(env); |
|
| 1730 |
gen_spr_40x(env); |
|
| 1731 |
gen_spr_401_403(env); |
|
| 1732 |
#if defined (TODO) |
|
| 1733 |
/* XXX: optional ? */ |
|
| 1734 |
gen_spr_compress(env); |
|
| 1735 |
#endif |
|
| 1736 |
env->nb_BATs = 0; |
|
| 1737 |
env->nb_tlb = 64; |
|
| 1738 |
env->nb_ways = 1; |
|
| 1739 |
env->id_tlbs = 0; |
|
| 1740 |
break; |
|
| 1741 |
|
|
| 1742 |
case CPU_PPC_403GA: /* 403 GA family */ |
|
| 1743 |
case CPU_PPC_403GB: /* 403 GB family */ |
|
| 1744 |
case CPU_PPC_403GC: /* 403 GC family */ |
|
| 1745 |
case CPU_PPC_403GCX: /* 403 GCX family */ |
|
| 1746 |
gen_spr_generic(env); |
|
| 1747 |
gen_spr_40x(env); |
|
| 1748 |
gen_spr_401_403(env); |
|
| 1749 |
gen_spr_403(env); |
|
| 1750 |
env->nb_BATs = 0; |
|
| 1751 |
env->nb_tlb = 64; |
|
| 1752 |
env->nb_ways = 1; |
|
| 1753 |
env->id_tlbs = 0; |
|
| 1754 |
break; |
|
| 1755 |
|
|
| 1756 |
case CPU_PPC_405CR: /* 405 GP/CR family */ |
|
| 1757 |
case CPU_PPC_405EP: /* 405 EP family */ |
|
| 1758 |
case CPU_PPC_405GPR: /* 405 GPR family */ |
|
| 1759 |
case CPU_PPC_405D2: /* 405 D2 family */ |
|
| 1760 |
case CPU_PPC_405D4: /* 405 D4 family */ |
|
| 1761 |
gen_spr_generic(env); |
|
| 1762 |
/* Time base */ |
|
| 1763 |
gen_tbl(env); |
|
| 1764 |
gen_spr_40x(env); |
|
| 1765 |
gen_spr_405(env); |
|
| 1766 |
env->nb_BATs = 0; |
|
| 1767 |
env->nb_tlb = 64; |
|
| 1768 |
env->nb_ways = 1; |
|
| 1769 |
env->id_tlbs = 0; |
|
| 1770 |
break; |
|
| 1771 |
|
|
| 1772 |
case CPU_PPC_NPE405H: /* NPe405 H family */ |
|
| 1773 |
case CPU_PPC_NPE405H2: |
|
| 1774 |
case CPU_PPC_NPE405L: /* Npe405 L family */ |
|
| 1775 |
gen_spr_generic(env); |
|
| 1776 |
/* Time base */ |
|
| 1777 |
gen_tbl(env); |
|
| 1778 |
gen_spr_40x(env); |
|
| 1779 |
gen_spr_405(env); |
|
| 1780 |
env->nb_BATs = 0; |
|
| 1781 |
env->nb_tlb = 64; |
|
| 1782 |
env->nb_ways = 1; |
|
| 1783 |
env->id_tlbs = 0; |
|
| 1784 |
break; |
|
| 1785 |
|
|
| 1786 |
#if defined (TODO) |
|
| 1787 |
case CPU_PPC_STB01000: |
|
| 1788 |
#endif |
|
| 1789 |
#if defined (TODO) |
|
| 1790 |
case CPU_PPC_STB01010: |
|
| 1791 |
#endif |
|
| 1792 |
#if defined (TODO) |
|
| 1793 |
case CPU_PPC_STB0210: |
|
| 1794 |
#endif |
|
| 1795 |
case CPU_PPC_STB03: /* STB03 family */ |
|
| 1796 |
#if defined (TODO) |
|
| 1797 |
case CPU_PPC_STB043: /* STB043 family */ |
|
| 1798 |
#endif |
|
| 1799 |
#if defined (TODO) |
|
| 1800 |
case CPU_PPC_STB045: /* STB045 family */ |
|
| 1801 |
#endif |
|
| 1802 |
case CPU_PPC_STB25: /* STB25 family */ |
|
| 1803 |
#if defined (TODO) |
|
| 1804 |
case CPU_PPC_STB130: /* STB130 family */ |
|
| 1805 |
#endif |
|
| 1806 |
gen_spr_generic(env); |
|
| 1807 |
/* Time base */ |
|
| 1808 |
gen_tbl(env); |
|
| 1809 |
gen_spr_40x(env); |
|
| 1810 |
gen_spr_405(env); |
|
| 1811 |
env->nb_BATs = 0; |
|
| 1812 |
env->nb_tlb = 64; |
|
| 1813 |
env->nb_ways = 1; |
|
| 1814 |
env->id_tlbs = 0; |
|
| 1815 |
break; |
|
| 1816 |
|
|
| 1817 |
case CPU_PPC_440EP: /* 440 EP family */ |
|
| 1818 |
case CPU_PPC_440GP: /* 440 GP family */ |
|
| 1819 |
case CPU_PPC_440GX: /* 440 GX family */ |
|
| 1820 |
case CPU_PPC_440GXc: /* 440 GXc family */ |
|
| 1821 |
case CPU_PPC_440GXf: /* 440 GXf family */ |
|
| 1822 |
case CPU_PPC_440SP: /* 440 SP family */ |
|
| 1823 |
case CPU_PPC_440SP2: |
|
| 1824 |
case CPU_PPC_440SPE: /* 440 SPE family */ |
|
| 1825 |
gen_spr_generic(env); |
|
| 1826 |
/* Time base */ |
|
| 1827 |
gen_tbl(env); |
|
| 1828 |
gen_spr_BookE(env); |
|
| 1829 |
gen_spr_440(env); |
|
| 1830 |
env->nb_BATs = 0; |
|
| 1831 |
env->nb_tlb = 64; |
|
| 1832 |
env->nb_ways = 1; |
|
| 1833 |
env->id_tlbs = 0; |
|
| 1834 |
break; |
|
| 1835 |
|
|
| 1836 |
/* Embedded PowerPC from Freescale */ |
|
| 1837 |
#if defined (TODO) |
|
| 1838 |
case CPU_PPC_5xx: |
|
| 1839 |
break; |
|
| 1840 |
#endif |
|
| 1841 |
#if defined (TODO) |
|
| 1842 |
case CPU_PPC_8xx: /* MPC821 / 823 / 850 / 860 */ |
|
| 1843 |
break; |
|
| 1844 |
#endif |
|
| 1845 |
#if defined (TODO) |
|
| 1846 |
case CPU_PPC_82xx_HIP3: /* MPC8240 / 8260 */ |
|
| 1847 |
case CPU_PPC_82xx_HIP4: /* MPC8240 / 8260 */ |
|
| 1848 |
break; |
|
| 1849 |
#endif |
|
| 1850 |
#if defined (TODO) |
|
| 1851 |
case CPU_PPC_827x: /* MPC 827x / 828x */ |
|
| 1852 |
break; |
|
| 1853 |
#endif |
|
| 1854 |
|
|
| 1855 |
/* XXX: Use MPC8540 PVR to implement a test PowerPC BookE target */ |
|
| 1856 |
case CPU_PPC_e500v110: |
|
| 1857 |
case CPU_PPC_e500v120: |
|
| 1858 |
case CPU_PPC_e500v210: |
|
| 1859 |
case CPU_PPC_e500v220: |
|
| 1860 |
gen_spr_generic(env); |
|
| 1861 |
/* Time base */ |
|
| 1862 |
gen_tbl(env); |
|
| 1863 |
gen_spr_BookE(env); |
|
| 1864 |
env->nb_BATs = 0; |
|
| 1865 |
env->nb_tlb = 64; |
|
| 1866 |
env->nb_ways = 1; |
|
Also available in: Unified diff