root / target-ppc / op_mem.h @ 76a66253
History | View | Annotate | Download (11.1 kB)
1 |
/*
|
---|---|
2 |
* PowerPC emulation micro-operations for qemu.
|
3 |
*
|
4 |
* Copyright (c) 2003-2007 Jocelyn Mayer
|
5 |
*
|
6 |
* This library is free software; you can redistribute it and/or
|
7 |
* modify it under the terms of the GNU Lesser General Public
|
8 |
* License as published by the Free Software Foundation; either
|
9 |
* version 2 of the License, or (at your option) any later version.
|
10 |
*
|
11 |
* This library is distributed in the hope that it will be useful,
|
12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 |
* Lesser General Public License for more details.
|
15 |
*
|
16 |
* You should have received a copy of the GNU Lesser General Public
|
17 |
* License along with this library; if not, write to the Free Software
|
18 |
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 |
*/
|
20 |
|
21 |
static inline uint16_t glue(ld16r, MEMSUFFIX) (target_ulong EA) |
22 |
{ |
23 |
uint16_t tmp = glue(lduw, MEMSUFFIX)(EA); |
24 |
return ((tmp & 0xFF00) >> 8) | ((tmp & 0x00FF) << 8); |
25 |
} |
26 |
|
27 |
static inline int32_t glue(ld16rs, MEMSUFFIX) (target_ulong EA) |
28 |
{ |
29 |
int16_t tmp = glue(lduw, MEMSUFFIX)(EA); |
30 |
return (int16_t)((tmp & 0xFF00) >> 8) | ((tmp & 0x00FF) << 8); |
31 |
} |
32 |
|
33 |
static inline uint32_t glue(ld32r, MEMSUFFIX) (target_ulong EA) |
34 |
{ |
35 |
uint32_t tmp = glue(ldl, MEMSUFFIX)(EA); |
36 |
return ((tmp & 0xFF000000) >> 24) | ((tmp & 0x00FF0000) >> 8) | |
37 |
((tmp & 0x0000FF00) << 8) | ((tmp & 0x000000FF) << 24); |
38 |
} |
39 |
|
40 |
static inline void glue(st16r, MEMSUFFIX) (target_ulong EA, uint16_t data) |
41 |
{ |
42 |
uint16_t tmp = ((data & 0xFF00) >> 8) | ((data & 0x00FF) << 8); |
43 |
glue(stw, MEMSUFFIX)(EA, tmp); |
44 |
} |
45 |
|
46 |
static inline void glue(st32r, MEMSUFFIX) (target_ulong EA, uint32_t data) |
47 |
{ |
48 |
uint32_t tmp = ((data & 0xFF000000) >> 24) | ((data & 0x00FF0000) >> 8) | |
49 |
((data & 0x0000FF00) << 8) | ((data & 0x000000FF) << 24); |
50 |
glue(stl, MEMSUFFIX)(EA, tmp); |
51 |
} |
52 |
|
53 |
/*** Integer load ***/
|
54 |
#define PPC_LD_OP(name, op) \
|
55 |
PPC_OP(glue(glue(l, name), MEMSUFFIX)) \ |
56 |
{ \ |
57 |
T1 = glue(op, MEMSUFFIX)(T0); \ |
58 |
RETURN(); \ |
59 |
} |
60 |
|
61 |
#define PPC_ST_OP(name, op) \
|
62 |
PPC_OP(glue(glue(st, name), MEMSUFFIX)) \ |
63 |
{ \ |
64 |
glue(op, MEMSUFFIX)(T0, T1); \ |
65 |
RETURN(); \ |
66 |
} |
67 |
|
68 |
PPC_LD_OP(bz, ldub); |
69 |
PPC_LD_OP(ha, ldsw); |
70 |
PPC_LD_OP(hz, lduw); |
71 |
PPC_LD_OP(wz, ldl); |
72 |
|
73 |
PPC_LD_OP(ha_le, ld16rs); |
74 |
PPC_LD_OP(hz_le, ld16r); |
75 |
PPC_LD_OP(wz_le, ld32r); |
76 |
|
77 |
/*** Integer store ***/
|
78 |
PPC_ST_OP(b, stb); |
79 |
PPC_ST_OP(h, stw); |
80 |
PPC_ST_OP(w, stl); |
81 |
|
82 |
PPC_ST_OP(h_le, st16r); |
83 |
PPC_ST_OP(w_le, st32r); |
84 |
|
85 |
/*** Integer load and store with byte reverse ***/
|
86 |
PPC_LD_OP(hbr, ld16r); |
87 |
PPC_LD_OP(wbr, ld32r); |
88 |
PPC_ST_OP(hbr, st16r); |
89 |
PPC_ST_OP(wbr, st32r); |
90 |
|
91 |
PPC_LD_OP(hbr_le, lduw); |
92 |
PPC_LD_OP(wbr_le, ldl); |
93 |
PPC_ST_OP(hbr_le, stw); |
94 |
PPC_ST_OP(wbr_le, stl); |
95 |
|
96 |
/*** Integer load and store multiple ***/
|
97 |
PPC_OP(glue(lmw, MEMSUFFIX)) |
98 |
{ |
99 |
glue(do_lmw, MEMSUFFIX)(PARAM1); |
100 |
RETURN(); |
101 |
} |
102 |
|
103 |
PPC_OP(glue(lmw_le, MEMSUFFIX)) |
104 |
{ |
105 |
glue(do_lmw_le, MEMSUFFIX)(PARAM1); |
106 |
RETURN(); |
107 |
} |
108 |
|
109 |
PPC_OP(glue(stmw, MEMSUFFIX)) |
110 |
{ |
111 |
glue(do_stmw, MEMSUFFIX)(PARAM1); |
112 |
RETURN(); |
113 |
} |
114 |
|
115 |
PPC_OP(glue(stmw_le, MEMSUFFIX)) |
116 |
{ |
117 |
glue(do_stmw_le, MEMSUFFIX)(PARAM1); |
118 |
RETURN(); |
119 |
} |
120 |
|
121 |
/*** Integer load and store strings ***/
|
122 |
PPC_OP(glue(lswi, MEMSUFFIX)) |
123 |
{ |
124 |
glue(do_lsw, MEMSUFFIX)(PARAM(1));
|
125 |
RETURN(); |
126 |
} |
127 |
|
128 |
PPC_OP(glue(lswi_le, MEMSUFFIX)) |
129 |
{ |
130 |
glue(do_lsw_le, MEMSUFFIX)(PARAM(1));
|
131 |
RETURN(); |
132 |
} |
133 |
|
134 |
/* PPC32 specification says we must generate an exception if
|
135 |
* rA is in the range of registers to be loaded.
|
136 |
* In an other hand, IBM says this is valid, but rA won't be loaded.
|
137 |
* For now, I'll follow the spec...
|
138 |
*/
|
139 |
PPC_OP(glue(lswx, MEMSUFFIX)) |
140 |
{ |
141 |
if (unlikely(T1 > 0)) { |
142 |
if (unlikely((PARAM1 < PARAM2 && (PARAM1 + T1) > PARAM2) ||
|
143 |
(PARAM1 < PARAM3 && (PARAM1 + T1) > PARAM3))) { |
144 |
do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX); |
145 |
} else {
|
146 |
glue(do_lsw, MEMSUFFIX)(PARAM(1));
|
147 |
} |
148 |
} |
149 |
RETURN(); |
150 |
} |
151 |
|
152 |
PPC_OP(glue(lswx_le, MEMSUFFIX)) |
153 |
{ |
154 |
if (unlikely(T1 > 0)) { |
155 |
if (unlikely((PARAM1 < PARAM2 && (PARAM1 + T1) > PARAM2) ||
|
156 |
(PARAM1 < PARAM3 && (PARAM1 + T1) > PARAM3))) { |
157 |
do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX); |
158 |
} else {
|
159 |
glue(do_lsw_le, MEMSUFFIX)(PARAM(1));
|
160 |
} |
161 |
} |
162 |
RETURN(); |
163 |
} |
164 |
|
165 |
PPC_OP(glue(stsw, MEMSUFFIX)) |
166 |
{ |
167 |
glue(do_stsw, MEMSUFFIX)(PARAM(1));
|
168 |
RETURN(); |
169 |
} |
170 |
|
171 |
PPC_OP(glue(stsw_le, MEMSUFFIX)) |
172 |
{ |
173 |
glue(do_stsw_le, MEMSUFFIX)(PARAM(1));
|
174 |
RETURN(); |
175 |
} |
176 |
|
177 |
/*** Floating-point store ***/
|
178 |
#define PPC_STF_OP(name, op) \
|
179 |
PPC_OP(glue(glue(st, name), MEMSUFFIX)) \ |
180 |
{ \ |
181 |
glue(op, MEMSUFFIX)(T0, FT0); \ |
182 |
RETURN(); \ |
183 |
} |
184 |
|
185 |
PPC_STF_OP(fd, stfq); |
186 |
PPC_STF_OP(fs, stfl); |
187 |
|
188 |
static inline void glue(stfqr, MEMSUFFIX) (target_ulong EA, double d) |
189 |
{ |
190 |
union {
|
191 |
double d;
|
192 |
uint64_t u; |
193 |
} u; |
194 |
|
195 |
u.d = d; |
196 |
u.u = ((u.u & 0xFF00000000000000ULL) >> 56) | |
197 |
((u.u & 0x00FF000000000000ULL) >> 40) | |
198 |
((u.u & 0x0000FF0000000000ULL) >> 24) | |
199 |
((u.u & 0x000000FF00000000ULL) >> 8) | |
200 |
((u.u & 0x00000000FF000000ULL) << 8) | |
201 |
((u.u & 0x0000000000FF0000ULL) << 24) | |
202 |
((u.u & 0x000000000000FF00ULL) << 40) | |
203 |
((u.u & 0x00000000000000FFULL) << 56); |
204 |
glue(stfq, MEMSUFFIX)(EA, u.d); |
205 |
} |
206 |
|
207 |
static inline void glue(stflr, MEMSUFFIX) (target_ulong EA, float f) |
208 |
{ |
209 |
union {
|
210 |
float f;
|
211 |
uint32_t u; |
212 |
} u; |
213 |
|
214 |
u.f = f; |
215 |
u.u = ((u.u & 0xFF000000UL) >> 24) | |
216 |
((u.u & 0x00FF0000ULL) >> 8) | |
217 |
((u.u & 0x0000FF00UL) << 8) | |
218 |
((u.u & 0x000000FFULL) << 24); |
219 |
glue(stfl, MEMSUFFIX)(EA, u.f); |
220 |
} |
221 |
|
222 |
PPC_STF_OP(fd_le, stfqr); |
223 |
PPC_STF_OP(fs_le, stflr); |
224 |
|
225 |
/*** Floating-point load ***/
|
226 |
#define PPC_LDF_OP(name, op) \
|
227 |
PPC_OP(glue(glue(l, name), MEMSUFFIX)) \ |
228 |
{ \ |
229 |
FT0 = glue(op, MEMSUFFIX)(T0); \ |
230 |
RETURN(); \ |
231 |
} |
232 |
|
233 |
PPC_LDF_OP(fd, ldfq); |
234 |
PPC_LDF_OP(fs, ldfl); |
235 |
|
236 |
static inline double glue(ldfqr, MEMSUFFIX) (target_ulong EA) |
237 |
{ |
238 |
union {
|
239 |
double d;
|
240 |
uint64_t u; |
241 |
} u; |
242 |
|
243 |
u.d = glue(ldfq, MEMSUFFIX)(EA); |
244 |
u.u = ((u.u & 0xFF00000000000000ULL) >> 56) | |
245 |
((u.u & 0x00FF000000000000ULL) >> 40) | |
246 |
((u.u & 0x0000FF0000000000ULL) >> 24) | |
247 |
((u.u & 0x000000FF00000000ULL) >> 8) | |
248 |
((u.u & 0x00000000FF000000ULL) << 8) | |
249 |
((u.u & 0x0000000000FF0000ULL) << 24) | |
250 |
((u.u & 0x000000000000FF00ULL) << 40) | |
251 |
((u.u & 0x00000000000000FFULL) << 56); |
252 |
|
253 |
return u.d;
|
254 |
} |
255 |
|
256 |
static inline float glue(ldflr, MEMSUFFIX) (target_ulong EA) |
257 |
{ |
258 |
union {
|
259 |
float f;
|
260 |
uint32_t u; |
261 |
} u; |
262 |
|
263 |
u.f = glue(ldfl, MEMSUFFIX)(EA); |
264 |
u.u = ((u.u & 0xFF000000UL) >> 24) | |
265 |
((u.u & 0x00FF0000ULL) >> 8) | |
266 |
((u.u & 0x0000FF00UL) << 8) | |
267 |
((u.u & 0x000000FFULL) << 24); |
268 |
|
269 |
return u.f;
|
270 |
} |
271 |
|
272 |
PPC_LDF_OP(fd_le, ldfqr); |
273 |
PPC_LDF_OP(fs_le, ldflr); |
274 |
|
275 |
/* Load and set reservation */
|
276 |
PPC_OP(glue(lwarx, MEMSUFFIX)) |
277 |
{ |
278 |
if (unlikely(T0 & 0x03)) { |
279 |
do_raise_exception(EXCP_ALIGN); |
280 |
} else {
|
281 |
T1 = glue(ldl, MEMSUFFIX)(T0); |
282 |
regs->reserve = T0; |
283 |
} |
284 |
RETURN(); |
285 |
} |
286 |
|
287 |
PPC_OP(glue(lwarx_le, MEMSUFFIX)) |
288 |
{ |
289 |
if (unlikely(T0 & 0x03)) { |
290 |
do_raise_exception(EXCP_ALIGN); |
291 |
} else {
|
292 |
T1 = glue(ld32r, MEMSUFFIX)(T0); |
293 |
regs->reserve = T0; |
294 |
} |
295 |
RETURN(); |
296 |
} |
297 |
|
298 |
/* Store with reservation */
|
299 |
PPC_OP(glue(stwcx, MEMSUFFIX)) |
300 |
{ |
301 |
if (unlikely(T0 & 0x03)) { |
302 |
do_raise_exception(EXCP_ALIGN); |
303 |
} else {
|
304 |
if (unlikely(regs->reserve != T0)) {
|
305 |
env->crf[0] = xer_ov;
|
306 |
} else {
|
307 |
glue(stl, MEMSUFFIX)(T0, T1); |
308 |
env->crf[0] = xer_ov | 0x02; |
309 |
} |
310 |
} |
311 |
regs->reserve = -1;
|
312 |
RETURN(); |
313 |
} |
314 |
|
315 |
PPC_OP(glue(stwcx_le, MEMSUFFIX)) |
316 |
{ |
317 |
if (unlikely(T0 & 0x03)) { |
318 |
do_raise_exception(EXCP_ALIGN); |
319 |
} else {
|
320 |
if (unlikely(regs->reserve != T0)) {
|
321 |
env->crf[0] = xer_ov;
|
322 |
} else {
|
323 |
glue(st32r, MEMSUFFIX)(T0, T1); |
324 |
env->crf[0] = xer_ov | 0x02; |
325 |
} |
326 |
} |
327 |
regs->reserve = -1;
|
328 |
RETURN(); |
329 |
} |
330 |
|
331 |
PPC_OP(glue(dcbz, MEMSUFFIX)) |
332 |
{ |
333 |
glue(stl, MEMSUFFIX)(T0 + 0x00, 0); |
334 |
glue(stl, MEMSUFFIX)(T0 + 0x04, 0); |
335 |
glue(stl, MEMSUFFIX)(T0 + 0x08, 0); |
336 |
glue(stl, MEMSUFFIX)(T0 + 0x0C, 0); |
337 |
glue(stl, MEMSUFFIX)(T0 + 0x10, 0); |
338 |
glue(stl, MEMSUFFIX)(T0 + 0x14, 0); |
339 |
glue(stl, MEMSUFFIX)(T0 + 0x18, 0); |
340 |
glue(stl, MEMSUFFIX)(T0 + 0x1C, 0); |
341 |
#if DCACHE_LINE_SIZE == 64 |
342 |
/* XXX: cache line size should be 64 for POWER & PowerPC 601 */
|
343 |
glue(stl, MEMSUFFIX)(T0 + 0x20UL, 0); |
344 |
glue(stl, MEMSUFFIX)(T0 + 0x24UL, 0); |
345 |
glue(stl, MEMSUFFIX)(T0 + 0x28UL, 0); |
346 |
glue(stl, MEMSUFFIX)(T0 + 0x2CUL, 0); |
347 |
glue(stl, MEMSUFFIX)(T0 + 0x30UL, 0); |
348 |
glue(stl, MEMSUFFIX)(T0 + 0x34UL, 0); |
349 |
glue(stl, MEMSUFFIX)(T0 + 0x38UL, 0); |
350 |
glue(stl, MEMSUFFIX)(T0 + 0x3CUL, 0); |
351 |
#endif
|
352 |
RETURN(); |
353 |
} |
354 |
|
355 |
/* External access */
|
356 |
PPC_OP(glue(eciwx, MEMSUFFIX)) |
357 |
{ |
358 |
T1 = glue(ldl, MEMSUFFIX)(T0); |
359 |
RETURN(); |
360 |
} |
361 |
|
362 |
PPC_OP(glue(ecowx, MEMSUFFIX)) |
363 |
{ |
364 |
glue(stl, MEMSUFFIX)(T0, T1); |
365 |
RETURN(); |
366 |
} |
367 |
|
368 |
PPC_OP(glue(eciwx_le, MEMSUFFIX)) |
369 |
{ |
370 |
T1 = glue(ld32r, MEMSUFFIX)(T0); |
371 |
RETURN(); |
372 |
} |
373 |
|
374 |
PPC_OP(glue(ecowx_le, MEMSUFFIX)) |
375 |
{ |
376 |
glue(st32r, MEMSUFFIX)(T0, T1); |
377 |
RETURN(); |
378 |
} |
379 |
|
380 |
/* XXX: those micro-ops need tests ! */
|
381 |
/* PowerPC 601 specific instructions (POWER bridge) */
|
382 |
void OPPROTO glue(op_POWER_lscbx, MEMSUFFIX) (void) |
383 |
{ |
384 |
/* When byte count is 0, do nothing */
|
385 |
if (likely(T1 > 0)) { |
386 |
glue(do_POWER_lscbx, MEMSUFFIX)(PARAM1, PARAM2, PARAM3); |
387 |
} |
388 |
RETURN(); |
389 |
} |
390 |
|
391 |
/* POWER2 quad load and store */
|
392 |
/* XXX: TAGs are not managed */
|
393 |
void OPPROTO glue(op_POWER2_lfq, MEMSUFFIX) (void) |
394 |
{ |
395 |
glue(do_POWER2_lfq, MEMSUFFIX)(); |
396 |
RETURN(); |
397 |
} |
398 |
|
399 |
void glue(op_POWER2_lfq_le, MEMSUFFIX) (void) |
400 |
{ |
401 |
glue(do_POWER2_lfq_le, MEMSUFFIX)(); |
402 |
RETURN(); |
403 |
} |
404 |
|
405 |
void OPPROTO glue(op_POWER2_stfq, MEMSUFFIX) (void) |
406 |
{ |
407 |
glue(do_POWER2_stfq, MEMSUFFIX)(); |
408 |
RETURN(); |
409 |
} |
410 |
|
411 |
void OPPROTO glue(op_POWER2_stfq_le, MEMSUFFIX) (void) |
412 |
{ |
413 |
glue(do_POWER2_stfq_le, MEMSUFFIX)(); |
414 |
RETURN(); |
415 |
} |
416 |
|
417 |
#undef MEMSUFFIX
|