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Name Size
  core-dc232b
  core-dc233c
  core-fsf
Makefile.objs 172 Bytes
core-dc232b.c 2.1 kB
core-dc233c.c 2.1 kB
core-fsf.c 2 kB
cpu-qom.h 2.6 kB
cpu.c 3.2 kB
cpu.h 14 kB
helper.c 21 kB
helper.h 2.4 kB
machine.c 1.7 kB
op_helper.c 27.2 kB
overlay_tool.h 17.3 kB
translate.c 98.5 kB
xtensa-semi.c 9.7 kB

Latest revisions

# Date Author Comment
76cad711 12/19/2012 09:29 am Paolo Bonzini

build: kill libdis, move disassemblers to disas/

Signed-off-by: Paolo Bonzini <>
a8a826a3 12/16/2012 10:35 am Blue Swirl

exec: refactor cpu_restore_state

Refactor common code around calls to cpu_restore_state().

tb_find_pc() has now no external users, make it static.

Signed-off-by: Blue Swirl <>
659f807c 12/15/2012 10:39 am Max Filippov

target-xtensa: fix ITLB/DTLB page protection flags

With MMU option xtensa architecture has two TLBs: ITLB and DTLB. ITLB is
only used for code access, DTLB is only for data. However TLB entries in
both TLBs have attribute field controlling write and exec access. These...
fcc803d1 12/08/2012 08:48 pm Max Filippov

target-xtensa: implement ATOMCTL SR

ATOMCTL SR controls s32c1i opcode behavior depending on targeted memory
type. See ISA, 4.3.12.4 for details.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
4e41d2f5 12/08/2012 08:48 pm Max Filippov

target-xtensa: implement CACHEATTR SR

In XEA1, the Options for Memory Protection and Translation and the
corresponding TLB management instructions are not available. Instead,
functionality similar to the Region Protection Option is available
through the cache attribute register. See ISA, A.2.14 for details....
fe0bd475 12/08/2012 08:48 pm Max Filippov

target-xtensa: restrict available SRs by enabled options

Beginning with the RA-2004.1 release, SR access instructions (rsr, wsr,
xsr) are associated with their corresponding SR and raise illegal opcode
exception in case the register is not configured for the core....
53593e90 12/08/2012 08:48 pm Max Filippov

target-xtensa: better control rsr/wsr/xsr access to SRs

There are read-only (DEBUGCAUSE, PRID) and write-only (INTCLEAR) SRs,
and INTERRUPT/INTSET SR allows rsr/wsr, but not xsr. Raise illeagal
opcode exception on illegal access to these SRs.

Signed-off-by: Max Filippov <>...
b7909d81 12/08/2012 08:48 pm Max Filippov

target-xtensa: implement MISC SR

The Miscellaneous Special Registers Option provides zero to four scratch
registers within the processor readable and writable by RSR, WSR, and
XSR. These registers are privileged. They may be useful for some
application-specific exception and interrupt processing tasks in the...
f877d09e 12/08/2012 08:48 pm Max Filippov

target-xtensa: use movcond where possible

Use movcond for all sorts of conditional moves, ABS, CLAMPS, MIN/MAX
opcodes.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
ab1103de 12/08/2012 04:24 pm Evgeny Voevodin

TCG: Use gen_opc_instr_start from context instead of global variable.

Signed-off-by: Evgeny Voevodin <>
Signed-off-by: Blue Swirl <>

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