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root / target-cris @ 77d4f95e

Name Size
cpu.h 6.5 kB
crisv10-decode.h 3.4 kB
crisv32-decode.h 5.5 kB
exec.h 1.4 kB
helper.c 6.4 kB
helper.h 1 kB
machine.c 2.2 kB
mmu.c 8.5 kB
mmu.h 397 Bytes
op_helper.c 13.5 kB
opcode-cris.h 10 kB
translate.c 82.1 kB
translate_v10.c 38.3 kB

Latest revisions

# Date Author Comment
77d4f95e 06/10/2010 03:45 pm Edgar E. Iglesias

cris: Break out image loading to hw/cris-boot.c.

Signed-off-by: Edgar E. Iglesias <>
0bfcd599 05/22/2010 11:02 am Blue Swirl

Fix %lld or %llx printf format use

Signed-off-by: Blue Swirl <>
02021c3f 05/19/2010 08:29 pm Riccardo Magliocchetti

Fix VA__ARGS typo in cris mmu.c

Fix compilation with DEBUG defined

Signed-off-by: Riccardo Magliocchetti <>
Signed-off-by: Edgar E. Iglesias <>
0d84be5b 04/25/2010 10:46 pm Blue Swirl

cris: remove dead assignments, spotted by clang analyzer

Value stored is never read.

Signed-off-by: Blue Swirl <>
43dc2a64 03/18/2010 08:41 pm Blue Swirl

Replace assert(0) with abort() or cpu_abort()

When building with -DNDEBUG, assert(0) will not stop execution
so it must not be used for abnormal termination.

Use cpu_abort() when in CPU context, abort() otherwise.

Signed-off-by: Blue Swirl <>
d4c430a8 03/17/2010 04:44 am Paul Brook

Large page TLB flush

QEMU uses a fixed page size for the CPU TLB. If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.

When the guest invalidates the TLB by virtual address we must invalidate...
4fcc562b 03/12/2010 08:34 pm Paul Brook

Remove cpu_get_phys_page_debug from userspace emulation

cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.

Signed-off-by: Paul Brook <>
52705890 03/12/2010 06:28 pm Richard Henderson

Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.

Removes a set of ifdefs from exec.c.

Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other
than Alpha. This will be used for page_find_alloc, which is
supposed to be using virtual addresses in the first place....
70539e18 03/07/2010 05:48 pm Blue Swirl

Update to a hopefully more future proof FSF address

See also 8167ee883931cb20c6264fc19d040ce2dc6ceaaa,
530e7615ce3c01882e582c84dc6304ab98a3d5c5 and
fad6cb1a565bb73f83fc0e2654489457b489e436.

Signed-off-by: Blue Swirl <>
4ffb9ae2 02/20/2010 08:17 pm Edgar E. Iglesias

cris: Mask interrupts on dslots for CRISv10.

CRISv10 cores (unlike v32) do not take any interrupts while delayed
jumps are pending (delay slots).

Signed-off-by: Edgar E. Iglesias <>

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