Revision 77f193da target-sparc/op_helper.c
| b/target-sparc/op_helper.c | ||
|---|---|---|
| 795 | 795 |
GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1); |
| 796 | 796 |
#endif |
| 797 | 797 |
|
| 798 |
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && defined(DEBUG_MXCC) |
|
| 798 |
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \ |
|
| 799 |
defined(DEBUG_MXCC) |
|
| 799 | 800 |
static void dump_mxcc(CPUState *env) |
| 800 | 801 |
{
|
| 801 | 802 |
printf("mxccdata: %016llx %016llx %016llx %016llx\n",
|
| 802 |
env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]); |
|
| 803 |
env->mxccdata[0], env->mxccdata[1], |
|
| 804 |
env->mxccdata[2], env->mxccdata[3]); |
|
| 803 | 805 |
printf("mxccregs: %016llx %016llx %016llx %016llx\n"
|
| 804 | 806 |
" %016llx %016llx %016llx %016llx\n", |
| 805 |
env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3], |
|
| 806 |
env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]); |
|
| 807 |
env->mxccregs[0], env->mxccregs[1], |
|
| 808 |
env->mxccregs[2], env->mxccregs[3], |
|
| 809 |
env->mxccregs[4], env->mxccregs[5], |
|
| 810 |
env->mxccregs[6], env->mxccregs[7]); |
|
| 807 | 811 |
} |
| 808 | 812 |
#endif |
| 809 | 813 |
|
| ... | ... | |
| 851 | 855 |
if (size == 8) |
| 852 | 856 |
ret = env->mxccregs[3]; |
| 853 | 857 |
else |
| 854 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
|
| 858 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
|
| 859 |
size); |
|
| 855 | 860 |
break; |
| 856 | 861 |
case 0x01c00a04: /* MXCC control register */ |
| 857 | 862 |
if (size == 4) |
| 858 | 863 |
ret = env->mxccregs[3]; |
| 859 | 864 |
else |
| 860 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
|
| 865 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
|
| 866 |
size); |
|
| 861 | 867 |
break; |
| 862 | 868 |
case 0x01c00c00: /* Module reset register */ |
| 863 | 869 |
if (size == 8) {
|
| 864 | 870 |
ret = env->mxccregs[5]; |
| 865 | 871 |
// should we do something here? |
| 866 | 872 |
} else |
| 867 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
|
| 873 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
|
| 874 |
size); |
|
| 868 | 875 |
break; |
| 869 | 876 |
case 0x01c00f00: /* MBus port address register */ |
| 870 | 877 |
if (size == 8) |
| 871 | 878 |
ret = env->mxccregs[7]; |
| 872 | 879 |
else |
| 873 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
|
| 880 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
|
| 881 |
size); |
|
| 874 | 882 |
break; |
| 875 | 883 |
default: |
| 876 |
DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
|
|
| 884 |
DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
|
|
| 885 |
size); |
|
| 877 | 886 |
break; |
| 878 | 887 |
} |
| 879 |
DPRINTF_MXCC("asi = %d, size = %d, sign = %d, addr = %08x -> ret = %08x,"
|
|
| 888 |
DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
|
|
| 889 |
"addr = %08x -> ret = %08x," |
|
| 880 | 890 |
"addr = %08x\n", asi, size, sign, last_addr, ret, addr); |
| 881 | 891 |
#ifdef DEBUG_MXCC |
| 882 | 892 |
dump_mxcc(env); |
| ... | ... | |
| 1050 | 1060 |
if (size == 8) |
| 1051 | 1061 |
env->mxccdata[0] = val; |
| 1052 | 1062 |
else |
| 1053 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
|
| 1063 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
|
| 1064 |
size); |
|
| 1054 | 1065 |
break; |
| 1055 | 1066 |
case 0x01c00008: /* MXCC stream data register 1 */ |
| 1056 | 1067 |
if (size == 8) |
| 1057 | 1068 |
env->mxccdata[1] = val; |
| 1058 | 1069 |
else |
| 1059 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
|
| 1070 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
|
| 1071 |
size); |
|
| 1060 | 1072 |
break; |
| 1061 | 1073 |
case 0x01c00010: /* MXCC stream data register 2 */ |
| 1062 | 1074 |
if (size == 8) |
| 1063 | 1075 |
env->mxccdata[2] = val; |
| 1064 | 1076 |
else |
| 1065 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
|
| 1077 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
|
| 1078 |
size); |
|
| 1066 | 1079 |
break; |
| 1067 | 1080 |
case 0x01c00018: /* MXCC stream data register 3 */ |
| 1068 | 1081 |
if (size == 8) |
| 1069 | 1082 |
env->mxccdata[3] = val; |
| 1070 | 1083 |
else |
| 1071 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
|
| 1084 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
|
| 1085 |
size); |
|
| 1072 | 1086 |
break; |
| 1073 | 1087 |
case 0x01c00100: /* MXCC stream source */ |
| 1074 | 1088 |
if (size == 8) |
| 1075 | 1089 |
env->mxccregs[0] = val; |
| 1076 | 1090 |
else |
| 1077 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
|
| 1078 |
env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0); |
|
| 1079 |
env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8); |
|
| 1080 |
env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16); |
|
| 1081 |
env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24); |
|
| 1091 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
|
| 1092 |
size); |
|
| 1093 |
env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
|
| 1094 |
0); |
|
| 1095 |
env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
|
| 1096 |
8); |
|
| 1097 |
env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
|
| 1098 |
16); |
|
| 1099 |
env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
|
| 1100 |
24); |
|
| 1082 | 1101 |
break; |
| 1083 | 1102 |
case 0x01c00200: /* MXCC stream destination */ |
| 1084 | 1103 |
if (size == 8) |
| 1085 | 1104 |
env->mxccregs[1] = val; |
| 1086 | 1105 |
else |
| 1087 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
|
| 1088 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]); |
|
| 1089 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]); |
|
| 1090 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]); |
|
| 1091 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]); |
|
| 1106 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
|
| 1107 |
size); |
|
| 1108 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, |
|
| 1109 |
env->mxccdata[0]); |
|
| 1110 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, |
|
| 1111 |
env->mxccdata[1]); |
|
| 1112 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, |
|
| 1113 |
env->mxccdata[2]); |
|
| 1114 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, |
|
| 1115 |
env->mxccdata[3]); |
|
| 1092 | 1116 |
break; |
| 1093 | 1117 |
case 0x01c00a00: /* MXCC control register */ |
| 1094 | 1118 |
if (size == 8) |
| 1095 | 1119 |
env->mxccregs[3] = val; |
| 1096 | 1120 |
else |
| 1097 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
|
| 1121 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
|
| 1122 |
size); |
|
| 1098 | 1123 |
break; |
| 1099 | 1124 |
case 0x01c00a04: /* MXCC control register */ |
| 1100 | 1125 |
if (size == 4) |
| 1101 |
env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | val; |
|
| 1126 |
env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) |
|
| 1127 |
| val; |
|
| 1102 | 1128 |
else |
| 1103 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
|
| 1129 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
|
| 1130 |
size); |
|
| 1104 | 1131 |
break; |
| 1105 | 1132 |
case 0x01c00e00: /* MXCC error register */ |
| 1106 | 1133 |
// writing a 1 bit clears the error |
| 1107 | 1134 |
if (size == 8) |
| 1108 | 1135 |
env->mxccregs[6] &= ~val; |
| 1109 | 1136 |
else |
| 1110 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
|
| 1137 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
|
| 1138 |
size); |
|
| 1111 | 1139 |
break; |
| 1112 | 1140 |
case 0x01c00f00: /* MBus port address register */ |
| 1113 | 1141 |
if (size == 8) |
| 1114 | 1142 |
env->mxccregs[7] = val; |
| 1115 | 1143 |
else |
| 1116 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
|
| 1144 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
|
| 1145 |
size); |
|
| 1117 | 1146 |
break; |
| 1118 | 1147 |
default: |
| 1119 |
DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
|
|
| 1148 |
DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
|
|
| 1149 |
size); |
|
| 1120 | 1150 |
break; |
| 1121 | 1151 |
} |
| 1122 |
DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi, size, addr, val);
|
|
| 1152 |
DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi,
|
|
| 1153 |
size, addr, val); |
|
| 1123 | 1154 |
#ifdef DEBUG_MXCC |
| 1124 | 1155 |
dump_mxcc(env); |
| 1125 | 1156 |
#endif |
| ... | ... | |
| 1192 | 1223 |
break; |
| 1193 | 1224 |
} |
| 1194 | 1225 |
if (oldreg != env->mmuregs[reg]) {
|
| 1195 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
|
|
| 1226 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
|
|
| 1227 |
reg, oldreg, env->mmuregs[reg]); |
|
| 1196 | 1228 |
} |
| 1197 | 1229 |
#ifdef DEBUG_MMU |
| 1198 | 1230 |
dump_mmu(env); |
| ... | ... | |
| 1317 | 1349 |
case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic |
| 1318 | 1350 |
case 0x31: // store buffer data, Ross RT620 I-cache flush or |
| 1319 | 1351 |
// Turbosparc snoop RAM |
| 1320 |
case 0x32: // store buffer control or Turbosparc page table descriptor diagnostic |
|
| 1352 |
case 0x32: // store buffer control or Turbosparc page table |
|
| 1353 |
// descriptor diagnostic |
|
| 1321 | 1354 |
case 0x36: /* I-cache flash clear */ |
| 1322 | 1355 |
case 0x37: /* D-cache flash clear */ |
| 1323 | 1356 |
case 0x38: /* breakpoint diagnostics */ |
| ... | ... | |
| 1860 | 1893 |
// Mappings generated during D/I MMU disabled mode are |
| 1861 | 1894 |
// invalid in normal mode |
| 1862 | 1895 |
if (oldreg != env->lsu) {
|
| 1863 |
DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
|
|
| 1896 |
DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
|
|
| 1897 |
oldreg, env->lsu); |
|
| 1864 | 1898 |
#ifdef DEBUG_MMU |
| 1865 | 1899 |
dump_mmu(env); |
| 1866 | 1900 |
#endif |
| ... | ... | |
| 1894 | 1928 |
} |
| 1895 | 1929 |
env->immuregs[reg] = val; |
| 1896 | 1930 |
if (oldreg != env->immuregs[reg]) {
|
| 1897 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
|
|
| 1931 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
|
|
| 1932 |
PRIx64 "\n", reg, oldreg, env->immuregs[reg]); |
|
| 1898 | 1933 |
} |
| 1899 | 1934 |
#ifdef DEBUG_MMU |
| 1900 | 1935 |
dump_mmu(env); |
| ... | ... | |
| 1963 | 1998 |
} |
| 1964 | 1999 |
env->dmmuregs[reg] = val; |
| 1965 | 2000 |
if (oldreg != env->dmmuregs[reg]) {
|
| 1966 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
|
|
| 2001 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
|
|
| 2002 |
PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); |
|
| 1967 | 2003 |
} |
| 1968 | 2004 |
#ifdef DEBUG_MMU |
| 1969 | 2005 |
dump_mmu(env); |
| ... | ... | |
| 2042 | 2078 |
} |
| 2043 | 2079 |
helper_check_align(addr, 0x3f); |
| 2044 | 2080 |
for (i = 0; i < 16; i++) {
|
| 2045 |
*(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, 0); |
|
| 2081 |
*(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, |
|
| 2082 |
0); |
|
| 2046 | 2083 |
addr += 4; |
| 2047 | 2084 |
} |
| 2048 | 2085 |
|
| ... | ... | |
| 2697 | 2734 |
#endif |
| 2698 | 2735 |
#if !defined(CONFIG_USER_ONLY) |
| 2699 | 2736 |
if (env->tl == MAXTL) {
|
| 2700 |
cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index); |
|
| 2737 |
cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", |
|
| 2738 |
env->exception_index); |
|
| 2701 | 2739 |
return; |
| 2702 | 2740 |
} |
| 2703 | 2741 |
#endif |
| ... | ... | |
| 2807 | 2845 |
#endif |
| 2808 | 2846 |
#if !defined(CONFIG_USER_ONLY) |
| 2809 | 2847 |
if (env->psret == 0) {
|
| 2810 |
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index); |
|
| 2848 |
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", |
|
| 2849 |
env->exception_index); |
|
| 2811 | 2850 |
return; |
| 2812 | 2851 |
} |
| 2813 | 2852 |
#endif |
| ... | ... | |
| 2833 | 2872 |
#define MMUSUFFIX _mmu |
| 2834 | 2873 |
#define ALIGNED_ONLY |
| 2835 | 2874 |
#ifdef __s390__ |
| 2836 |
# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL)) |
|
| 2875 |
# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & \ |
|
| 2876 |
0x7fffffffUL)) |
|
| 2837 | 2877 |
#else |
| 2838 | 2878 |
# define GETPC() (__builtin_return_address(0)) |
| 2839 | 2879 |
#endif |
| ... | ... | |
| 2915 | 2955 |
env = cpu_single_env; |
| 2916 | 2956 |
#ifdef DEBUG_UNASSIGNED |
| 2917 | 2957 |
if (is_asi) |
| 2918 |
printf("Unassigned mem %s access to " TARGET_FMT_plx " asi 0x%02x from "
|
|
| 2919 |
TARGET_FMT_lx "\n", |
|
| 2958 |
printf("Unassigned mem %s access to " TARGET_FMT_plx
|
|
| 2959 |
" asi 0x%02x from " TARGET_FMT_lx "\n",
|
|
| 2920 | 2960 |
is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi, |
| 2921 | 2961 |
env->pc); |
| 2922 | 2962 |
else |
| ... | ... | |
| 2955 | 2995 |
generated code */ |
| 2956 | 2996 |
saved_env = env; |
| 2957 | 2997 |
env = cpu_single_env; |
| 2958 |
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n",
|
|
| 2959 |
addr, env->pc); |
|
| 2998 |
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
|
|
| 2999 |
"\n", addr, env->pc);
|
|
| 2960 | 3000 |
env = saved_env; |
| 2961 | 3001 |
#endif |
| 2962 | 3002 |
if (is_exec) |
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