root / target-ppc / op_template.h @ 7863667f
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| 1 | 28b6751f | bellard | /*
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| 2 | 3fc6c082 | bellard | * PowerPC emulation micro-operations for qemu.
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| 3 | 5fafdf24 | ths | *
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| 4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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| 5 | 28b6751f | bellard | *
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| 6 | 28b6751f | bellard | * This library is free software; you can redistribute it and/or
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| 7 | 28b6751f | bellard | * modify it under the terms of the GNU Lesser General Public
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| 8 | 28b6751f | bellard | * License as published by the Free Software Foundation; either
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| 9 | 28b6751f | bellard | * version 2 of the License, or (at your option) any later version.
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| 10 | 28b6751f | bellard | *
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| 11 | 28b6751f | bellard | * This library is distributed in the hope that it will be useful,
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| 12 | 28b6751f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | 28b6751f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 14 | 28b6751f | bellard | * Lesser General Public License for more details.
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| 15 | 28b6751f | bellard | *
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| 16 | 28b6751f | bellard | * You should have received a copy of the GNU Lesser General Public
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| 17 | 28b6751f | bellard | * License along with this library; if not, write to the Free Software
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| 18 | 28b6751f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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| 19 | 28b6751f | bellard | */
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| 20 | 28b6751f | bellard | |
| 21 | 9a64fbe4 | bellard | /* General purpose registers moves */
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| 22 | 76a66253 | j_mayer | void OPPROTO glue(op_load_gpr_T0_gpr, REG) (void) |
| 23 | 28b6751f | bellard | {
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| 24 | 36081602 | j_mayer | T0 = env->gpr[REG]; |
| 25 | 9a64fbe4 | bellard | RETURN(); |
| 26 | 28b6751f | bellard | } |
| 27 | 28b6751f | bellard | |
| 28 | 76a66253 | j_mayer | void OPPROTO glue(op_load_gpr_T1_gpr, REG) (void) |
| 29 | 28b6751f | bellard | {
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| 30 | 36081602 | j_mayer | T1 = env->gpr[REG]; |
| 31 | 9a64fbe4 | bellard | RETURN(); |
| 32 | 28b6751f | bellard | } |
| 33 | 28b6751f | bellard | |
| 34 | 76a66253 | j_mayer | void OPPROTO glue(op_load_gpr_T2_gpr, REG) (void) |
| 35 | 28b6751f | bellard | {
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| 36 | 36081602 | j_mayer | T2 = env->gpr[REG]; |
| 37 | 9a64fbe4 | bellard | RETURN(); |
| 38 | 28b6751f | bellard | } |
| 39 | 28b6751f | bellard | |
| 40 | 76a66253 | j_mayer | void OPPROTO glue(op_store_T0_gpr_gpr, REG) (void) |
| 41 | 28b6751f | bellard | {
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| 42 | 36081602 | j_mayer | env->gpr[REG] = T0; |
| 43 | 9a64fbe4 | bellard | RETURN(); |
| 44 | 28b6751f | bellard | } |
| 45 | 28b6751f | bellard | |
| 46 | 76a66253 | j_mayer | void OPPROTO glue(op_store_T1_gpr_gpr, REG) (void) |
| 47 | 28b6751f | bellard | {
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| 48 | 36081602 | j_mayer | env->gpr[REG] = T1; |
| 49 | 9a64fbe4 | bellard | RETURN(); |
| 50 | 28b6751f | bellard | } |
| 51 | 28b6751f | bellard | |
| 52 | 76a66253 | j_mayer | #if 0 // unused
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| 53 | 76a66253 | j_mayer | void OPPROTO glue(op_store_T2_gpr_gpr, REG) (void)
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| 54 | 28b6751f | bellard | {
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| 55 | 36081602 | j_mayer | env->gpr[REG] = T2;
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| 56 | 9a64fbe4 | bellard | RETURN();
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| 57 | 28b6751f | bellard | }
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| 58 | 76a66253 | j_mayer | #endif
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| 59 | 28b6751f | bellard | |
| 60 | a9d9eb8f | j_mayer | /* General purpose registers containing vector operands moves */
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| 61 | 65d6c0f3 | j_mayer | #if !defined(TARGET_PPC64)
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| 62 | 0487d6a8 | j_mayer | void OPPROTO glue(op_load_gpr64_T0_gpr, REG) (void) |
| 63 | 0487d6a8 | j_mayer | {
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| 64 | 3cd7d1dd | j_mayer | T0_64 = (uint64_t)env->gpr[REG] | ((uint64_t)env->gprh[REG] << 32);
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| 65 | 0487d6a8 | j_mayer | RETURN(); |
| 66 | 0487d6a8 | j_mayer | } |
| 67 | 0487d6a8 | j_mayer | |
| 68 | 0487d6a8 | j_mayer | void OPPROTO glue(op_load_gpr64_T1_gpr, REG) (void) |
| 69 | 0487d6a8 | j_mayer | {
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| 70 | 3cd7d1dd | j_mayer | T1_64 = (uint64_t)env->gpr[REG] | ((uint64_t)env->gprh[REG] << 32);
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| 71 | 0487d6a8 | j_mayer | RETURN(); |
| 72 | 0487d6a8 | j_mayer | } |
| 73 | 0487d6a8 | j_mayer | |
| 74 | 0487d6a8 | j_mayer | #if 0 // unused
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| 75 | 0487d6a8 | j_mayer | void OPPROTO glue(op_load_gpr64_T2_gpr, REG) (void)
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| 76 | 0487d6a8 | j_mayer | {
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| 77 | 3cd7d1dd | j_mayer | T2_64 = (uint64_t)env->gpr[REG] | ((uint64_t)env->gprh[REG] << 32);
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| 78 | 0487d6a8 | j_mayer | RETURN();
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| 79 | 0487d6a8 | j_mayer | }
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| 80 | 0487d6a8 | j_mayer | #endif
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| 81 | 0487d6a8 | j_mayer | |
| 82 | 0487d6a8 | j_mayer | void OPPROTO glue(op_store_T0_gpr64_gpr, REG) (void) |
| 83 | 0487d6a8 | j_mayer | {
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| 84 | 36081602 | j_mayer | env->gpr[REG] = T0_64; |
| 85 | 3cd7d1dd | j_mayer | env->gprh[REG] = T0_64 >> 32;
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| 86 | 0487d6a8 | j_mayer | RETURN(); |
| 87 | 0487d6a8 | j_mayer | } |
| 88 | 0487d6a8 | j_mayer | |
| 89 | 0487d6a8 | j_mayer | void OPPROTO glue(op_store_T1_gpr64_gpr, REG) (void) |
| 90 | 0487d6a8 | j_mayer | {
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| 91 | 36081602 | j_mayer | env->gpr[REG] = T1_64; |
| 92 | 3cd7d1dd | j_mayer | env->gprh[REG] = T1_64 >> 32;
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| 93 | 0487d6a8 | j_mayer | RETURN(); |
| 94 | 0487d6a8 | j_mayer | } |
| 95 | 0487d6a8 | j_mayer | |
| 96 | 0487d6a8 | j_mayer | #if 0 // unused
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| 97 | 0487d6a8 | j_mayer | void OPPROTO glue(op_store_T2_gpr64_gpr, REG) (void)
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| 98 | 0487d6a8 | j_mayer | {
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| 99 | 36081602 | j_mayer | env->gpr[REG] = T2_64;
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| 100 | 3cd7d1dd | j_mayer | env->gprh[REG] = T2_64 >> 32;
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| 101 | 0487d6a8 | j_mayer | RETURN();
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| 102 | 0487d6a8 | j_mayer | }
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| 103 | 0487d6a8 | j_mayer | #endif
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| 104 | 65d6c0f3 | j_mayer | #endif /* !defined(TARGET_PPC64) */ |
| 105 | 0487d6a8 | j_mayer | |
| 106 | a9d9eb8f | j_mayer | /* Altivec registers moves */
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| 107 | a9d9eb8f | j_mayer | void OPPROTO glue(op_load_avr_A0_avr, REG) (void) |
| 108 | a9d9eb8f | j_mayer | {
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| 109 | a9d9eb8f | j_mayer | AVR0 = env->avr[REG]; |
| 110 | a9d9eb8f | j_mayer | RETURN(); |
| 111 | a9d9eb8f | j_mayer | } |
| 112 | a9d9eb8f | j_mayer | |
| 113 | a9d9eb8f | j_mayer | void OPPROTO glue(op_load_avr_A1_avr, REG) (void) |
| 114 | a9d9eb8f | j_mayer | {
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| 115 | a9d9eb8f | j_mayer | AVR1 = env->avr[REG]; |
| 116 | a9d9eb8f | j_mayer | RETURN(); |
| 117 | a9d9eb8f | j_mayer | } |
| 118 | a9d9eb8f | j_mayer | |
| 119 | a9d9eb8f | j_mayer | void OPPROTO glue(op_load_avr_A2_avr, REG) (void) |
| 120 | a9d9eb8f | j_mayer | {
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| 121 | a9d9eb8f | j_mayer | AVR2 = env->avr[REG]; |
| 122 | a9d9eb8f | j_mayer | RETURN(); |
| 123 | a9d9eb8f | j_mayer | } |
| 124 | a9d9eb8f | j_mayer | |
| 125 | a9d9eb8f | j_mayer | void OPPROTO glue(op_store_A0_avr_avr, REG) (void) |
| 126 | a9d9eb8f | j_mayer | {
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| 127 | a9d9eb8f | j_mayer | env->avr[REG] = AVR0; |
| 128 | a9d9eb8f | j_mayer | RETURN(); |
| 129 | a9d9eb8f | j_mayer | } |
| 130 | a9d9eb8f | j_mayer | |
| 131 | a9d9eb8f | j_mayer | void OPPROTO glue(op_store_A1_avr_avr, REG) (void) |
| 132 | a9d9eb8f | j_mayer | {
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| 133 | a9d9eb8f | j_mayer | env->avr[REG] = AVR1; |
| 134 | a9d9eb8f | j_mayer | RETURN(); |
| 135 | a9d9eb8f | j_mayer | } |
| 136 | a9d9eb8f | j_mayer | |
| 137 | a9d9eb8f | j_mayer | #if 0 // unused
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| 138 | a9d9eb8f | j_mayer | void OPPROTO glue(op_store_A2_avr_avr, REG) (void)
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| 139 | a9d9eb8f | j_mayer | {
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| 140 | a9d9eb8f | j_mayer | env->avr[REG] = AVR2;
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| 141 | a9d9eb8f | j_mayer | RETURN();
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| 142 | a9d9eb8f | j_mayer | }
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| 143 | a9d9eb8f | j_mayer | #endif
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| 144 | a9d9eb8f | j_mayer | |
| 145 | 28b6751f | bellard | #if REG <= 7 |
| 146 | 9a64fbe4 | bellard | /* Condition register moves */
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| 147 | 76a66253 | j_mayer | void OPPROTO glue(op_load_crf_T0_crf, REG) (void) |
| 148 | 28b6751f | bellard | {
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| 149 | 36081602 | j_mayer | T0 = env->crf[REG]; |
| 150 | 9a64fbe4 | bellard | RETURN(); |
| 151 | 28b6751f | bellard | } |
| 152 | 28b6751f | bellard | |
| 153 | 76a66253 | j_mayer | void OPPROTO glue(op_load_crf_T1_crf, REG) (void) |
| 154 | 28b6751f | bellard | {
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| 155 | 36081602 | j_mayer | T1 = env->crf[REG]; |
| 156 | 9a64fbe4 | bellard | RETURN(); |
| 157 | 28b6751f | bellard | } |
| 158 | 28b6751f | bellard | |
| 159 | 76a66253 | j_mayer | void OPPROTO glue(op_store_T0_crf_crf, REG) (void) |
| 160 | 28b6751f | bellard | {
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| 161 | 36081602 | j_mayer | env->crf[REG] = T0; |
| 162 | 9a64fbe4 | bellard | RETURN(); |
| 163 | 28b6751f | bellard | } |
| 164 | 28b6751f | bellard | |
| 165 | fc0d441e | j_mayer | #if 0 // Unused
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| 166 | 76a66253 | j_mayer | void OPPROTO glue(op_store_T1_crf_crf, REG) (void)
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| 167 | 28b6751f | bellard | {
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| 168 | 36081602 | j_mayer | env->crf[REG] = T1;
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| 169 | 9a64fbe4 | bellard | RETURN();
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| 170 | 28b6751f | bellard | }
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| 171 | fc0d441e | j_mayer | #endif
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| 172 | 28b6751f | bellard | |
| 173 | 28b6751f | bellard | #endif /* REG <= 7 */ |
| 174 | 28b6751f | bellard | |
| 175 | fb0eaffc | bellard | /* floating point registers moves */
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| 176 | 76a66253 | j_mayer | void OPPROTO glue(op_load_fpr_FT0_fpr, REG) (void) |
| 177 | 28b6751f | bellard | {
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| 178 | 28b6751f | bellard | FT0 = env->fpr[REG]; |
| 179 | fb0eaffc | bellard | RETURN(); |
| 180 | 28b6751f | bellard | } |
| 181 | 28b6751f | bellard | |
| 182 | 76a66253 | j_mayer | void OPPROTO glue(op_store_FT0_fpr_fpr, REG) (void) |
| 183 | 28b6751f | bellard | {
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| 184 | 28b6751f | bellard | env->fpr[REG] = FT0; |
| 185 | fb0eaffc | bellard | RETURN(); |
| 186 | fb0eaffc | bellard | } |
| 187 | fb0eaffc | bellard | |
| 188 | 76a66253 | j_mayer | void OPPROTO glue(op_load_fpr_FT1_fpr, REG) (void) |
| 189 | fb0eaffc | bellard | {
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| 190 | fb0eaffc | bellard | FT1 = env->fpr[REG]; |
| 191 | fb0eaffc | bellard | RETURN(); |
| 192 | fb0eaffc | bellard | } |
| 193 | fb0eaffc | bellard | |
| 194 | 76a66253 | j_mayer | void OPPROTO glue(op_store_FT1_fpr_fpr, REG) (void) |
| 195 | fb0eaffc | bellard | {
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| 196 | fb0eaffc | bellard | env->fpr[REG] = FT1; |
| 197 | fb0eaffc | bellard | RETURN(); |
| 198 | fb0eaffc | bellard | } |
| 199 | fb0eaffc | bellard | |
| 200 | 76a66253 | j_mayer | void OPPROTO glue(op_load_fpr_FT2_fpr, REG) (void) |
| 201 | fb0eaffc | bellard | {
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| 202 | fb0eaffc | bellard | FT2 = env->fpr[REG]; |
| 203 | fb0eaffc | bellard | RETURN(); |
| 204 | fb0eaffc | bellard | } |
| 205 | fb0eaffc | bellard | |
| 206 | 76a66253 | j_mayer | #if 0 // unused
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| 207 | 76a66253 | j_mayer | void OPPROTO glue(op_store_FT2_fpr_fpr, REG) (void)
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| 208 | fb0eaffc | bellard | {
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| 209 | fb0eaffc | bellard | env->fpr[REG] = FT2;
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| 210 | fb0eaffc | bellard | RETURN();
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| 211 | 28b6751f | bellard | }
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| 212 | 9a64fbe4 | bellard | #endif
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| 213 | 9a64fbe4 | bellard | |
| 214 | 28b6751f | bellard | #undef REG |