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/*
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 *  PowerPC emulation cpu definitions for qemu.
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 *
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 *  Copyright (c) 2003-2007 Jocelyn Mayer
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#if !defined (__CPU_PPC_H__)
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#define __CPU_PPC_H__
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#include "config.h"
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#include <inttypes.h>
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#if defined (TARGET_PPC64)
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/* PowerPC 64 definitions */
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typedef uint64_t ppc_gpr_t;
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#define TARGET_GPR_BITS  64
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#define TARGET_LONG_BITS 64
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#define REGX "%016" PRIx64
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#define TARGET_PAGE_BITS 12
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#else /* defined (TARGET_PPC64) */
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/* PowerPC 32 definitions */
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#if (HOST_LONG_BITS >= 64)
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/* When using 64 bits temporary registers,
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 * we can use 64 bits GPR with no extra cost
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 * It's even an optimization as this will prevent
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 * the compiler to do unuseful masking in the micro-ops.
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 */
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typedef uint64_t ppc_gpr_t;
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#define TARGET_GPR_BITS  64
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#define REGX "%08" PRIx64
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#else /* (HOST_LONG_BITS >= 64) */
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typedef uint32_t ppc_gpr_t;
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#define TARGET_GPR_BITS  32
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#define REGX "%08" PRIx32
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#endif /* (HOST_LONG_BITS >= 64) */
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#define TARGET_LONG_BITS 32
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#if defined(TARGET_PPCEMB)
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/* Specific definitions for PowerPC embedded */
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/* BookE have 36 bits physical address space */
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#define TARGET_PHYS_ADDR_BITS 64
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#if defined(CONFIG_USER_ONLY)
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/* It looks like a lot of Linux programs assume page size
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 * is 4kB long. This is evil, but we have to deal with it...
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 */
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#define TARGET_PAGE_BITS 12
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#else /* defined(CONFIG_USER_ONLY) */
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/* Pages can be 1 kB small */
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#define TARGET_PAGE_BITS 10
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#endif /* defined(CONFIG_USER_ONLY) */
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#else /* defined(TARGET_PPCEMB) */
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/* "standard" PowerPC 32 definitions */
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#define TARGET_PAGE_BITS 12
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#endif /* defined(TARGET_PPCEMB) */
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#endif /* defined (TARGET_PPC64) */
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#include "cpu-defs.h"
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#define ADDRX TARGET_FMT_lx
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#define PADDRX TARGET_FMT_plx
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#include <setjmp.h>
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#include "softfloat.h"
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#define TARGET_HAS_ICE 1
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#if defined (TARGET_PPC64)
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#define ELF_MACHINE     EM_PPC64
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#else
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#define ELF_MACHINE     EM_PPC
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#endif
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/*****************************************************************************/
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/* MMU model                                                                 */
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enum {
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    POWERPC_MMU_UNKNOWN    = 0,
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    /* Standard 32 bits PowerPC MMU                            */
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    POWERPC_MMU_32B,
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    /* PowerPC 6xx MMU with software TLB                       */
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    POWERPC_MMU_SOFT_6xx,
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    /* PowerPC 74xx MMU with software TLB                      */
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    POWERPC_MMU_SOFT_74xx,
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    /* PowerPC 4xx MMU with software TLB                       */
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    POWERPC_MMU_SOFT_4xx,
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    /* PowerPC 4xx MMU with software TLB and zones protections */
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    POWERPC_MMU_SOFT_4xx_Z,
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    /* PowerPC 4xx MMU in real mode only                       */
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    POWERPC_MMU_REAL_4xx,
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    /* BookE MMU model                                         */
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    POWERPC_MMU_BOOKE,
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    /* BookE FSL MMU model                                     */
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    POWERPC_MMU_BOOKE_FSL,
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    /* PowerPC 601 MMU model (specific BATs format)            */
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    POWERPC_MMU_601,
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#if defined(TARGET_PPC64)
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    /* 64 bits PowerPC MMU                                     */
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    POWERPC_MMU_64B,
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#endif /* defined(TARGET_PPC64) */
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};
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/*****************************************************************************/
119
/* Exception model                                                           */
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enum {
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    POWERPC_EXCP_UNKNOWN   = 0,
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    /* Standard PowerPC exception model */
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    POWERPC_EXCP_STD,
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    /* PowerPC 40x exception model      */
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    POWERPC_EXCP_40x,
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    /* PowerPC 601 exception model      */
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    POWERPC_EXCP_601,
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    /* PowerPC 602 exception model      */
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    POWERPC_EXCP_602,
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    /* PowerPC 603 exception model      */
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    POWERPC_EXCP_603,
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    /* PowerPC 603e exception model     */
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    POWERPC_EXCP_603E,
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    /* PowerPC G2 exception model       */
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    POWERPC_EXCP_G2,
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    /* PowerPC 604 exception model      */
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    POWERPC_EXCP_604,
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    /* PowerPC 7x0 exception model      */
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    POWERPC_EXCP_7x0,
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    /* PowerPC 7x5 exception model      */
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    POWERPC_EXCP_7x5,
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    /* PowerPC 74xx exception model     */
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    POWERPC_EXCP_74xx,
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    /* BookE exception model            */
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    POWERPC_EXCP_BOOKE,
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#if defined(TARGET_PPC64)
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    /* PowerPC 970 exception model      */
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    POWERPC_EXCP_970,
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#endif /* defined(TARGET_PPC64) */
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};
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/*****************************************************************************/
153
/* Exception vectors definitions                                             */
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enum {
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    POWERPC_EXCP_NONE    = -1,
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    /* The 64 first entries are used by the PowerPC embedded specification   */
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    POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
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    POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
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    POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
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    POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
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    POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
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    POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
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    POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
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    POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
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    POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
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    POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
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    POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
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    POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
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    POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
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    POWERPC_EXCP_DTLB     = 13, /* Data TLB error                            */
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    POWERPC_EXCP_ITLB     = 14, /* Instruction TLB error                     */
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    POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
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    /* Vectors 16 to 31 are reserved                                         */
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    POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
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    POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
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    POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
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    POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
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    POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
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    POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
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    /* Vectors 38 to 63 are reserved                                         */
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    /* Exceptions defined in the PowerPC server specification                */
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    POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
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#if defined(TARGET_PPC64) /* PowerPC 64 */
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    POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
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    POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
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#endif /* defined(TARGET_PPC64) */
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#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
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    POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
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#endif /* defined(TARGET_PPC64H) */
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    POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
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#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
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    POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
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    POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
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    POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
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    POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
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#endif /* defined(TARGET_PPC64H) */
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    POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
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    /* 40x specific exceptions                                               */
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    POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
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    /* 601 specific exceptions                                               */
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    POWERPC_EXCP_IO       = 75, /* IO error exception                        */
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    POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
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    /* 602 specific exceptions                                               */
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    POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
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    /* 602/603 specific exceptions                                           */
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    POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB error               */
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    POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
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    POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
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    /* Exceptions available on most PowerPC                                  */
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    POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
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    POWERPC_EXCP_IABR     = 82, /* Instruction address breakpoint            */
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    POWERPC_EXCP_SMI      = 83, /* System management interrupt               */
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    POWERPC_EXCP_PERFM    = 84, /* Embedded performance monitor interrupt    */
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    /* 7xx/74xx specific exceptions                                          */
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    POWERPC_EXCP_THERM    = 85, /* Thermal interrupt                         */
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    /* 74xx specific exceptions                                              */
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    POWERPC_EXCP_VPUA     = 86, /* Vector assist exception                   */
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    /* 970FX specific exceptions                                             */
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    POWERPC_EXCP_SOFTP    = 87, /* Soft patch exception                      */
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    POWERPC_EXCP_MAINT    = 88, /* Maintenance exception                     */
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    /* EOL                                                                   */
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    POWERPC_EXCP_NB       = 96,
223
    /* Qemu exceptions: used internally during code translation              */
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    POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
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    POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
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    /* Qemu exceptions: special cases we want to stop translation            */
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    POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
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    POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
229
};
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/* Exceptions error codes                                                    */
232
enum {
233
    /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
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    POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
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    POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
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    POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
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    POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
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    POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
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    POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
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    /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
241
    /* FP exceptions                                                         */
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    POWERPC_EXCP_FP            = 0x10,
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    POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
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    POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
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    POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
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    POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
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    POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
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    POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
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    POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
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    POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
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    POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
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    POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
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    POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
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    POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
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    POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
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    /* Invalid instruction                                                   */
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    POWERPC_EXCP_INVAL         = 0x20,
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    POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
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    POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
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    POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
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    POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
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    /* Privileged instruction                                                */
263
    POWERPC_EXCP_PRIV          = 0x30,
264
    POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
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    POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
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    /* Trap                                                                  */
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    POWERPC_EXCP_TRAP          = 0x40,
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};
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/*****************************************************************************/
271
/* Input pins model                                                          */
272
enum {
273
    PPC_FLAGS_INPUT_UNKNOWN = 0,
274
    /* PowerPC 6xx bus                  */
275
    PPC_FLAGS_INPUT_6xx,
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    /* BookE bus                        */
277
    PPC_FLAGS_INPUT_BookE,
278
    /* PowerPC 405 bus                  */
279
    PPC_FLAGS_INPUT_405,
280
    /* PowerPC 970 bus                  */
281
    PPC_FLAGS_INPUT_970,
282
    /* PowerPC 401 bus                  */
283
    PPC_FLAGS_INPUT_401,
284
};
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286
#define PPC_INPUT(env) (env->bus_model)
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/*****************************************************************************/
289
typedef struct ppc_def_t ppc_def_t;
290
typedef struct opc_handler_t opc_handler_t;
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292
/*****************************************************************************/
293
/* Types used to describe some PowerPC registers */
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typedef struct CPUPPCState CPUPPCState;
295
typedef struct ppc_tb_t ppc_tb_t;
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typedef struct ppc_spr_t ppc_spr_t;
297
typedef struct ppc_dcr_t ppc_dcr_t;
298
typedef union ppc_avr_t ppc_avr_t;
299
typedef union ppc_tlb_t ppc_tlb_t;
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/* SPR access micro-ops generations callbacks */
302
struct ppc_spr_t {
303
    void (*uea_read)(void *opaque, int spr_num);
304
    void (*uea_write)(void *opaque, int spr_num);
305
#if !defined(CONFIG_USER_ONLY)
306
    void (*oea_read)(void *opaque, int spr_num);
307
    void (*oea_write)(void *opaque, int spr_num);
308
    void (*hea_read)(void *opaque, int spr_num);
309
    void (*hea_write)(void *opaque, int spr_num);
310
#endif
311
    const unsigned char *name;
312
};
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/* Altivec registers (128 bits) */
315
union ppc_avr_t {
316
    uint8_t u8[16];
317
    uint16_t u16[8];
318
    uint32_t u32[4];
319
    uint64_t u64[2];
320
};
321

    
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/* Software TLB cache */
323
typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
324
struct ppc6xx_tlb_t {
325
    target_ulong pte0;
326
    target_ulong pte1;
327
    target_ulong EPN;
328
};
329

    
330
typedef struct ppcemb_tlb_t ppcemb_tlb_t;
331
struct ppcemb_tlb_t {
332
    target_phys_addr_t RPN;
333
    target_ulong EPN;
334
    target_ulong PID;
335
    target_ulong size;
336
    uint32_t prot;
337
    uint32_t attr; /* Storage attributes */
338
};
339

    
340
union ppc_tlb_t {
341
    ppc6xx_tlb_t tlb6;
342
    ppcemb_tlb_t tlbe;
343
};
344

    
345
/*****************************************************************************/
346
/* Machine state register bits definition                                    */
347
#define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
348
#define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
349
#define MSR_HV   60 /* hypervisor state                               hflags */
350
#define MSR_CM   31 /* Computation mode for BookE                     hflags */
351
#define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
352
#define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
353
#define MSR_VR   25 /* altivec available                            x hflags */
354
#define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
355
#define MSR_AP   23 /* Access privilege state on 602                  hflags */
356
#define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
357
#define MSR_KEY  19 /* key bit on 603e                                       */
358
#define MSR_POW  18 /* Power management                                      */
359
#define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
360
#define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
361
#define MSR_ILE  16 /* Interrupt little-endian mode                          */
362
#define MSR_EE   15 /* External interrupt enable                             */
363
#define MSR_PR   14 /* Problem state                                  hflags */
364
#define MSR_FP   13 /* Floating point available                       hflags */
365
#define MSR_ME   12 /* Machine check interrupt enable                        */
366
#define MSR_FE0  11 /* Floating point exception mode 0                hflags */
367
#define MSR_SE   10 /* Single-step trace enable                     x hflags */
368
#define MSR_DWE  10 /* Debug wait enable on 405                     x        */
369
#define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
370
#define MSR_BE   9  /* Branch trace enable                          x hflags */
371
#define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
372
#define MSR_FE1  8  /* Floating point exception mode 1                hflags */
373
#define MSR_AL   7  /* AL bit on POWER                                       */
374
#define MSR_EP   6  /* Exception prefix on 601                               */
375
#define MSR_IR   5  /* Instruction relocate                                  */
376
#define MSR_DR   4  /* Data relocate                                         */
377
#define MSR_PE   3  /* Protection enable on 403                              */
378
#define MSR_PX   2  /* Protection exclusive on 403                  x        */
379
#define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
380
#define MSR_RI   1  /* Recoverable interrupt                        1        */
381
#define MSR_LE   0  /* Little-endian mode                           1 hflags */
382

    
383
#define msr_sf   ((env->msr >> MSR_SF)   & 1)
384
#define msr_isf  ((env->msr >> MSR_ISF)  & 1)
385
#define msr_hv   ((env->msr >> MSR_HV)   & 1)
386
#define msr_cm   ((env->msr >> MSR_CM)   & 1)
387
#define msr_icm  ((env->msr >> MSR_ICM)  & 1)
388
#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
389
#define msr_vr   ((env->msr >> MSR_VR)   & 1)
390
#define msr_spe  ((env->msr >> MSR_SE)   & 1)
391
#define msr_ap   ((env->msr >> MSR_AP)   & 1)
392
#define msr_sa   ((env->msr >> MSR_SA)   & 1)
393
#define msr_key  ((env->msr >> MSR_KEY)  & 1)
394
#define msr_pow  ((env->msr >> MSR_POW)  & 1)
395
#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
396
#define msr_ce   ((env->msr >> MSR_CE)   & 1)
397
#define msr_ile  ((env->msr >> MSR_ILE)  & 1)
398
#define msr_ee   ((env->msr >> MSR_EE)   & 1)
399
#define msr_pr   ((env->msr >> MSR_PR)   & 1)
400
#define msr_fp   ((env->msr >> MSR_FP)   & 1)
401
#define msr_me   ((env->msr >> MSR_ME)   & 1)
402
#define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
403
#define msr_se   ((env->msr >> MSR_SE)   & 1)
404
#define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
405
#define msr_uble ((env->msr >> MSR_UBLE) & 1)
406
#define msr_be   ((env->msr >> MSR_BE)   & 1)
407
#define msr_de   ((env->msr >> MSR_DE)   & 1)
408
#define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
409
#define msr_al   ((env->msr >> MSR_AL)   & 1)
410
#define msr_ep   ((env->msr >> MSR_EP)   & 1)
411
#define msr_ir   ((env->msr >> MSR_IR)   & 1)
412
#define msr_dr   ((env->msr >> MSR_DR)   & 1)
413
#define msr_pe   ((env->msr >> MSR_PE)   & 1)
414
#define msr_px   ((env->msr >> MSR_PX)   & 1)
415
#define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
416
#define msr_ri   ((env->msr >> MSR_RI)   & 1)
417
#define msr_le   ((env->msr >> MSR_LE)   & 1)
418

    
419
enum {
420
    POWERPC_FLAG_NONE = 0x00000000,
421
    /* Flag for MSR bit 25 signification (VRE/SPE)                           */
422
    POWERPC_FLAG_SPE  = 0x00000001,
423
    POWERPC_FLAG_VRE  = 0x00000002,
424
    /* Flag for MSR bit 17 signification (TGPR/CE)                           */
425
    POWERPC_FLAG_TGPR = 0x00000004,
426
    POWERPC_FLAG_CE   = 0x00000008,
427
    /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
428
    POWERPC_FLAG_SE   = 0x00000010,
429
    POWERPC_FLAG_DWE  = 0x00000020,
430
    POWERPC_FLAG_UBLE = 0x00000040,
431
    /* Flag for MSR bit 9 signification (BE/DE)                              */
432
    POWERPC_FLAG_BE   = 0x00000080,
433
    POWERPC_FLAG_DE   = 0x00000100,
434
    /* Flag for MSR but 2 signification (PX/PMM)                             */
435
    POWERPC_FLAG_PX   = 0x00000200,
436
    POWERPC_FLAG_PMM  = 0x00000400,
437
};
438

    
439
/*****************************************************************************/
440
/* Floating point status and control register                                */
441
#define FPSCR_FX     31 /* Floating-point exception summary                  */
442
#define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
443
#define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
444
#define FPSCR_OX     28 /* Floating-point overflow exception                 */
445
#define FPSCR_UX     27 /* Floating-point underflow exception                */
446
#define FPSCR_ZX     26 /* Floating-point zero divide exception              */
447
#define FPSCR_XX     25 /* Floating-point inexact exception                  */
448
#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
449
#define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
450
#define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
451
#define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
452
#define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
453
#define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
454
#define FPSCR_FR     18 /* Floating-point fraction rounded                   */
455
#define FPSCR_FI     17 /* Floating-point fraction inexact                   */
456
#define FPSCR_C      16 /* Floating-point result class descriptor            */
457
#define FPSCR_FL     15 /* Floating-point less than or negative              */
458
#define FPSCR_FG     14 /* Floating-point greater than or negative           */
459
#define FPSCR_FE     13 /* Floating-point equal or zero                      */
460
#define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
461
#define FPSCR_FPCC   12 /* Floating-point condition code                     */
462
#define FPSCR_FPRF   12 /* Floating-point result flags                       */
463
#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
464
#define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
465
#define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
466
#define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
467
#define FPSCR_OE     6  /* Floating-point overflow exception enable          */
468
#define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
469
#define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
470
#define FPSCR_XE     3  /* Floating-point inexact exception enable           */
471
#define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
472
#define FPSCR_RN1    1
473
#define FPSCR_RN     0  /* Floating-point rounding control                   */
474
#define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
475
#define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
476
#define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
477
#define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
478
#define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
479
#define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
480
#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
481
#define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
482
#define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
483
#define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
484
#define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
485
#define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
486
#define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
487
#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
488
#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
489
#define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
490
#define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
491
#define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
492
#define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
493
#define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
494
#define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
495
#define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
496
#define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)
497
/* Invalid operation exception summary */
498
#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
499
                                  (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
500
                                  (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
501
                                  (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
502
                                  (1 << FPSCR_VXCVI)))
503
/* exception summary */
504
#define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
505
/* enabled exception summary */
506
#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
507
                   0x1F)
508

    
509
/*****************************************************************************/
510
/* The whole PowerPC CPU context */
511
#define NB_MMU_MODES 3
512

    
513
struct CPUPPCState {
514
    /* First are the most commonly used resources
515
     * during translated code execution
516
     */
517
#if (HOST_LONG_BITS == 32)
518
    /* temporary fixed-point registers
519
     * used to emulate 64 bits registers on 32 bits hosts
520
     */
521
    uint64_t t0, t1, t2;
522
#endif
523
    ppc_avr_t avr0, avr1, avr2;
524

    
525
    /* general purpose registers */
526
    ppc_gpr_t gpr[32];
527
#if !defined(TARGET_PPC64)
528
    /* Storage for GPR MSB, used by the SPE extension */
529
    ppc_gpr_t gprh[32];
530
#endif
531
    /* LR */
532
    target_ulong lr;
533
    /* CTR */
534
    target_ulong ctr;
535
    /* condition register */
536
    uint8_t crf[8];
537
    /* XER */
538
    /* XXX: We use only 5 fields, but we want to keep the structure aligned */
539
    uint8_t xer[8];
540
    /* Reservation address */
541
    target_ulong reserve;
542

    
543
    /* Those ones are used in supervisor mode only */
544
    /* machine state register */
545
    target_ulong msr;
546
    /* temporary general purpose registers */
547
    ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
548

    
549
    /* Floating point execution context */
550
    /* temporary float registers */
551
    float64 ft0;
552
    float64 ft1;
553
    float64 ft2;
554
    float_status fp_status;
555
    /* floating point registers */
556
    float64 fpr[32];
557
    /* floating point status and control register */
558
    uint32_t fpscr;
559

    
560
    CPU_COMMON
561

    
562
    int halted; /* TRUE if the CPU is in suspend state */
563

    
564
    int access_type; /* when a memory exception occurs, the access
565
                        type is stored here */
566

    
567
    /* MMU context - only relevant for full system emulation */
568
#if !defined(CONFIG_USER_ONLY)
569
#if defined(TARGET_PPC64)
570
    /* Address space register */
571
    target_ulong asr;
572
    /* PowerPC 64 SLB area */
573
    int slb_nr;
574
#endif
575
    /* segment registers */
576
    target_ulong sdr1;
577
    target_ulong sr[16];
578
    /* BATs */
579
    int nb_BATs;
580
    target_ulong DBAT[2][8];
581
    target_ulong IBAT[2][8];
582
    /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
583
    int nb_tlb;      /* Total number of TLB                                  */
584
    int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
585
    int nb_ways;     /* Number of ways in the TLB set                        */
586
    int last_way;    /* Last used way used to allocate TLB in a LRU way      */
587
    int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
588
    int nb_pids;     /* Number of available PID registers                    */
589
    ppc_tlb_t *tlb;  /* TLB is optional. Allocate them only if needed        */
590
    /* 403 dedicated access protection registers */
591
    target_ulong pb[4];
592
#endif
593

    
594
    /* Other registers */
595
    /* Special purpose registers */
596
    target_ulong spr[1024];
597
    ppc_spr_t spr_cb[1024];
598
    /* Altivec registers */
599
    ppc_avr_t avr[32];
600
    uint32_t vscr;
601
    /* SPE registers */
602
    ppc_gpr_t spe_acc;
603
    float_status spe_status;
604
    uint32_t spe_fscr;
605

    
606
    /* Internal devices resources */
607
    /* Time base and decrementer */
608
    ppc_tb_t *tb_env;
609
    /* Device control registers */
610
    ppc_dcr_t *dcr_env;
611

    
612
    int dcache_line_size;
613
    int icache_line_size;
614

    
615
    /* Those resources are used during exception processing */
616
    /* CPU model definition */
617
    target_ulong msr_mask;
618
    uint8_t mmu_model;
619
    uint8_t excp_model;
620
    uint8_t bus_model;
621
    uint8_t pad;
622
    int bfd_mach;
623
    uint32_t flags;
624

    
625
    int exception_index;
626
    int error_code;
627
    int interrupt_request;
628
    uint32_t pending_interrupts;
629
#if !defined(CONFIG_USER_ONLY)
630
    /* This is the IRQ controller, which is implementation dependant
631
     * and only relevant when emulating a complete machine.
632
     */
633
    uint32_t irq_input_state;
634
    void **irq_inputs;
635
    /* Exception vectors */
636
    target_ulong excp_vectors[POWERPC_EXCP_NB];
637
    target_ulong excp_prefix;
638
    target_ulong ivor_mask;
639
    target_ulong ivpr_mask;
640
    target_ulong hreset_vector;
641
#endif
642

    
643
    /* Those resources are used only during code translation */
644
    /* Next instruction pointer */
645
    target_ulong nip;
646

    
647
    /* opcode handlers */
648
    opc_handler_t *opcodes[0x40];
649

    
650
    /* Those resources are used only in Qemu core */
651
    jmp_buf jmp_env;
652
    int user_mode_only; /* user mode only simulation */
653
    target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */
654
    target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
655
    int mmu_idx;         /* precomputed MMU index to speed up mem accesses */
656

    
657
    /* Power management */
658
    int power_mode;
659
    int (*check_pow)(CPUPPCState *env);
660

    
661
    /* temporary hack to handle OSI calls (only used if non NULL) */
662
    int (*osi_call)(struct CPUPPCState *env);
663
};
664

    
665
/* Context used internally during MMU translations */
666
typedef struct mmu_ctx_t mmu_ctx_t;
667
struct mmu_ctx_t {
668
    target_phys_addr_t raddr;      /* Real address              */
669
    int prot;                      /* Protection bits           */
670
    target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
671
    target_ulong ptem;             /* Virtual segment ID | API  */
672
    int key;                       /* Access key                */
673
    int nx;                        /* Non-execute area          */
674
};
675

    
676
/*****************************************************************************/
677
CPUPPCState *cpu_ppc_init (const char *cpu_model);
678
int cpu_ppc_exec (CPUPPCState *s);
679
void cpu_ppc_close (CPUPPCState *s);
680
/* you can call this signal handler from your SIGBUS and SIGSEGV
681
   signal handlers to inform the virtual CPU of exceptions. non zero
682
   is returned if the signal was handled by the virtual CPU.  */
683
int cpu_ppc_signal_handler (int host_signum, void *pinfo,
684
                            void *puc);
685

    
686
void do_interrupt (CPUPPCState *env);
687
void ppc_hw_interrupt (CPUPPCState *env);
688
void cpu_loop_exit (void);
689

    
690
void dump_stack (CPUPPCState *env);
691

    
692
#if !defined(CONFIG_USER_ONLY)
693
target_ulong do_load_ibatu (CPUPPCState *env, int nr);
694
target_ulong do_load_ibatl (CPUPPCState *env, int nr);
695
void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
696
void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
697
target_ulong do_load_dbatu (CPUPPCState *env, int nr);
698
target_ulong do_load_dbatl (CPUPPCState *env, int nr);
699
void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
700
void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
701
void do_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
702
void do_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
703
target_ulong do_load_sdr1 (CPUPPCState *env);
704
void do_store_sdr1 (CPUPPCState *env, target_ulong value);
705
#if defined(TARGET_PPC64)
706
target_ulong ppc_load_asr (CPUPPCState *env);
707
void ppc_store_asr (CPUPPCState *env, target_ulong value);
708
target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
709
void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs);
710
#endif /* defined(TARGET_PPC64) */
711
#if 0 // Unused
712
target_ulong do_load_sr (CPUPPCState *env, int srnum);
713
#endif
714
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
715
#endif /* !defined(CONFIG_USER_ONLY) */
716
target_ulong ppc_load_xer (CPUPPCState *env);
717
void ppc_store_xer (CPUPPCState *env, target_ulong value);
718
void ppc_store_msr (CPUPPCState *env, target_ulong value);
719

    
720
void cpu_ppc_reset (void *opaque);
721

    
722
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
723

    
724
const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name);
725
int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
726

    
727
/* Time-base and decrementer management */
728
#ifndef NO_CPU_IO_DEFS
729
uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
730
uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
731
void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
732
void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
733
uint32_t cpu_ppc_load_atbl (CPUPPCState *env);
734
uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
735
void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
736
void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
737
uint32_t cpu_ppc_load_decr (CPUPPCState *env);
738
void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
739
#if defined(TARGET_PPC64H)
740
uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
741
void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
742
uint64_t cpu_ppc_load_purr (CPUPPCState *env);
743
void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
744
#endif
745
uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
746
uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
747
#if !defined(CONFIG_USER_ONLY)
748
void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
749
void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
750
target_ulong load_40x_pit (CPUPPCState *env);
751
void store_40x_pit (CPUPPCState *env, target_ulong val);
752
void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
753
void store_40x_sler (CPUPPCState *env, uint32_t val);
754
void store_booke_tcr (CPUPPCState *env, target_ulong val);
755
void store_booke_tsr (CPUPPCState *env, target_ulong val);
756
void ppc_tlb_invalidate_all (CPUPPCState *env);
757
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
758
#if defined(TARGET_PPC64)
759
void ppc_slb_invalidate_all (CPUPPCState *env);
760
void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
761
#endif
762
int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
763
#endif
764
#endif
765

    
766
/* Device control registers */
767
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
768
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
769

    
770
#define CPUState CPUPPCState
771
#define cpu_init cpu_ppc_init
772
#define cpu_exec cpu_ppc_exec
773
#define cpu_gen_code cpu_ppc_gen_code
774
#define cpu_signal_handler cpu_ppc_signal_handler
775
#define cpu_list ppc_cpu_list
776

    
777
/* MMU modes definitions */
778
#define MMU_MODE0_SUFFIX _user
779
#define MMU_MODE1_SUFFIX _kernel
780
#define MMU_MODE2_SUFFIX _hypv
781
#define MMU_USER_IDX 0
782
static inline int cpu_mmu_index (CPUState *env)
783
{
784
    return env->mmu_idx;
785
}
786

    
787
#include "cpu-all.h"
788

    
789
/*****************************************************************************/
790
/* Registers definitions */
791
#define XER_SO 31
792
#define XER_OV 30
793
#define XER_CA 29
794
#define XER_CMP 8
795
#define XER_BC  0
796
#define xer_so  env->xer[4]
797
#define xer_ov  env->xer[6]
798
#define xer_ca  env->xer[2]
799
#define xer_cmp env->xer[1]
800
#define xer_bc  env->xer[0]
801

    
802
/* SPR definitions */
803
#define SPR_MQ           (0x000)
804
#define SPR_XER          (0x001)
805
#define SPR_601_VRTCU    (0x004)
806
#define SPR_601_VRTCL    (0x005)
807
#define SPR_601_UDECR    (0x006)
808
#define SPR_LR           (0x008)
809
#define SPR_CTR          (0x009)
810
#define SPR_DSISR        (0x012)
811
#define SPR_DAR          (0x013) /* DAE for PowerPC 601 */
812
#define SPR_601_RTCU     (0x014)
813
#define SPR_601_RTCL     (0x015)
814
#define SPR_DECR         (0x016)
815
#define SPR_SDR1         (0x019)
816
#define SPR_SRR0         (0x01A)
817
#define SPR_SRR1         (0x01B)
818
#define SPR_AMR          (0x01D)
819
#define SPR_BOOKE_PID    (0x030)
820
#define SPR_BOOKE_DECAR  (0x036)
821
#define SPR_BOOKE_CSRR0  (0x03A)
822
#define SPR_BOOKE_CSRR1  (0x03B)
823
#define SPR_BOOKE_DEAR   (0x03D)
824
#define SPR_BOOKE_ESR    (0x03E)
825
#define SPR_BOOKE_IVPR   (0x03F)
826
#define SPR_8xx_EIE      (0x050)
827
#define SPR_8xx_EID      (0x051)
828
#define SPR_8xx_NRE      (0x052)
829
#define SPR_CTRL         (0x088)
830
#define SPR_58x_CMPA     (0x090)
831
#define SPR_58x_CMPB     (0x091)
832
#define SPR_58x_CMPC     (0x092)
833
#define SPR_58x_CMPD     (0x093)
834
#define SPR_58x_ICR      (0x094)
835
#define SPR_58x_DER      (0x094)
836
#define SPR_58x_COUNTA   (0x096)
837
#define SPR_58x_COUNTB   (0x097)
838
#define SPR_UCTRL        (0x098)
839
#define SPR_58x_CMPE     (0x098)
840
#define SPR_58x_CMPF     (0x099)
841
#define SPR_58x_CMPG     (0x09A)
842
#define SPR_58x_CMPH     (0x09B)
843
#define SPR_58x_LCTRL1   (0x09C)
844
#define SPR_58x_LCTRL2   (0x09D)
845
#define SPR_58x_ICTRL    (0x09E)
846
#define SPR_58x_BAR      (0x09F)
847
#define SPR_VRSAVE       (0x100)
848
#define SPR_USPRG0       (0x100)
849
#define SPR_USPRG1       (0x101)
850
#define SPR_USPRG2       (0x102)
851
#define SPR_USPRG3       (0x103)
852
#define SPR_USPRG4       (0x104)
853
#define SPR_USPRG5       (0x105)
854
#define SPR_USPRG6       (0x106)
855
#define SPR_USPRG7       (0x107)
856
#define SPR_VTBL         (0x10C)
857
#define SPR_VTBU         (0x10D)
858
#define SPR_SPRG0        (0x110)
859
#define SPR_SPRG1        (0x111)
860
#define SPR_SPRG2        (0x112)
861
#define SPR_SPRG3        (0x113)
862
#define SPR_SPRG4        (0x114)
863
#define SPR_SCOMC        (0x114)
864
#define SPR_SPRG5        (0x115)
865
#define SPR_SCOMD        (0x115)
866
#define SPR_SPRG6        (0x116)
867
#define SPR_SPRG7        (0x117)
868
#define SPR_ASR          (0x118)
869
#define SPR_EAR          (0x11A)
870
#define SPR_TBL          (0x11C)
871
#define SPR_TBU          (0x11D)
872
#define SPR_TBU40        (0x11E)
873
#define SPR_SVR          (0x11E)
874
#define SPR_BOOKE_PIR    (0x11E)
875
#define SPR_PVR          (0x11F)
876
#define SPR_HSPRG0       (0x130)
877
#define SPR_BOOKE_DBSR   (0x130)
878
#define SPR_HSPRG1       (0x131)
879
#define SPR_HDSISR       (0x132)
880
#define SPR_HDAR         (0x133)
881
#define SPR_BOOKE_DBCR0  (0x134)
882
#define SPR_IBCR         (0x135)
883
#define SPR_PURR         (0x135)
884
#define SPR_BOOKE_DBCR1  (0x135)
885
#define SPR_DBCR         (0x136)
886
#define SPR_HDEC         (0x136)
887
#define SPR_BOOKE_DBCR2  (0x136)
888
#define SPR_HIOR         (0x137)
889
#define SPR_MBAR         (0x137)
890
#define SPR_RMOR         (0x138)
891
#define SPR_BOOKE_IAC1   (0x138)
892
#define SPR_HRMOR        (0x139)
893
#define SPR_BOOKE_IAC2   (0x139)
894
#define SPR_HSRR0        (0x13A)
895
#define SPR_BOOKE_IAC3   (0x13A)
896
#define SPR_HSRR1        (0x13B)
897
#define SPR_BOOKE_IAC4   (0x13B)
898
#define SPR_LPCR         (0x13C)
899
#define SPR_BOOKE_DAC1   (0x13C)
900
#define SPR_LPIDR        (0x13D)
901
#define SPR_DABR2        (0x13D)
902
#define SPR_BOOKE_DAC2   (0x13D)
903
#define SPR_BOOKE_DVC1   (0x13E)
904
#define SPR_BOOKE_DVC2   (0x13F)
905
#define SPR_BOOKE_TSR    (0x150)
906
#define SPR_BOOKE_TCR    (0x154)
907
#define SPR_BOOKE_IVOR0  (0x190)
908
#define SPR_BOOKE_IVOR1  (0x191)
909
#define SPR_BOOKE_IVOR2  (0x192)
910
#define SPR_BOOKE_IVOR3  (0x193)
911
#define SPR_BOOKE_IVOR4  (0x194)
912
#define SPR_BOOKE_IVOR5  (0x195)
913
#define SPR_BOOKE_IVOR6  (0x196)
914
#define SPR_BOOKE_IVOR7  (0x197)
915
#define SPR_BOOKE_IVOR8  (0x198)
916
#define SPR_BOOKE_IVOR9  (0x199)
917
#define SPR_BOOKE_IVOR10 (0x19A)
918
#define SPR_BOOKE_IVOR11 (0x19B)
919
#define SPR_BOOKE_IVOR12 (0x19C)
920
#define SPR_BOOKE_IVOR13 (0x19D)
921
#define SPR_BOOKE_IVOR14 (0x19E)
922
#define SPR_BOOKE_IVOR15 (0x19F)
923
#define SPR_BOOKE_SPEFSCR (0x200)
924
#define SPR_E500_BBEAR   (0x201)
925
#define SPR_E500_BBTAR   (0x202)
926
#define SPR_ATBL         (0x20E)
927
#define SPR_ATBU         (0x20F)
928
#define SPR_IBAT0U       (0x210)
929
#define SPR_BOOKE_IVOR32 (0x210)
930
#define SPR_IBAT0L       (0x211)
931
#define SPR_BOOKE_IVOR33 (0x211)
932
#define SPR_IBAT1U       (0x212)
933
#define SPR_BOOKE_IVOR34 (0x212)
934
#define SPR_IBAT1L       (0x213)
935
#define SPR_BOOKE_IVOR35 (0x213)
936
#define SPR_IBAT2U       (0x214)
937
#define SPR_BOOKE_IVOR36 (0x214)
938
#define SPR_IBAT2L       (0x215)
939
#define SPR_E500_L1CFG0  (0x215)
940
#define SPR_BOOKE_IVOR37 (0x215)
941
#define SPR_IBAT3U       (0x216)
942
#define SPR_E500_L1CFG1  (0x216)
943
#define SPR_IBAT3L       (0x217)
944
#define SPR_DBAT0U       (0x218)
945
#define SPR_DBAT0L       (0x219)
946
#define SPR_DBAT1U       (0x21A)
947
#define SPR_DBAT1L       (0x21B)
948
#define SPR_DBAT2U       (0x21C)
949
#define SPR_DBAT2L       (0x21D)
950
#define SPR_DBAT3U       (0x21E)
951
#define SPR_DBAT3L       (0x21F)
952
#define SPR_IBAT4U       (0x230)
953
#define SPR_IBAT4L       (0x231)
954
#define SPR_IBAT5U       (0x232)
955
#define SPR_IBAT5L       (0x233)
956
#define SPR_IBAT6U       (0x234)
957
#define SPR_IBAT6L       (0x235)
958
#define SPR_IBAT7U       (0x236)
959
#define SPR_IBAT7L       (0x237)
960
#define SPR_DBAT4U       (0x238)
961
#define SPR_DBAT4L       (0x239)
962
#define SPR_DBAT5U       (0x23A)
963
#define SPR_BOOKE_MCSRR0 (0x23A)
964
#define SPR_DBAT5L       (0x23B)
965
#define SPR_BOOKE_MCSRR1 (0x23B)
966
#define SPR_DBAT6U       (0x23C)
967
#define SPR_BOOKE_MCSR   (0x23C)
968
#define SPR_DBAT6L       (0x23D)
969
#define SPR_E500_MCAR    (0x23D)
970
#define SPR_DBAT7U       (0x23E)
971
#define SPR_BOOKE_DSRR0  (0x23E)
972
#define SPR_DBAT7L       (0x23F)
973
#define SPR_BOOKE_DSRR1  (0x23F)
974
#define SPR_BOOKE_SPRG8  (0x25C)
975
#define SPR_BOOKE_SPRG9  (0x25D)
976
#define SPR_BOOKE_MAS0   (0x270)
977
#define SPR_BOOKE_MAS1   (0x271)
978
#define SPR_BOOKE_MAS2   (0x272)
979
#define SPR_BOOKE_MAS3   (0x273)
980
#define SPR_BOOKE_MAS4   (0x274)
981
#define SPR_BOOKE_MAS6   (0x276)
982
#define SPR_BOOKE_PID1   (0x279)
983
#define SPR_BOOKE_PID2   (0x27A)
984
#define SPR_BOOKE_TLB0CFG (0x2B0)
985
#define SPR_BOOKE_TLB1CFG (0x2B1)
986
#define SPR_BOOKE_TLB2CFG (0x2B2)
987
#define SPR_BOOKE_TLB3CFG (0x2B3)
988
#define SPR_BOOKE_EPR    (0x2BE)
989
#define SPR_PERF0        (0x300)
990
#define SPR_PERF1        (0x301)
991
#define SPR_PERF2        (0x302)
992
#define SPR_PERF3        (0x303)
993
#define SPR_PERF4        (0x304)
994
#define SPR_PERF5        (0x305)
995
#define SPR_PERF6        (0x306)
996
#define SPR_PERF7        (0x307)
997
#define SPR_PERF8        (0x308)
998
#define SPR_PERF9        (0x309)
999
#define SPR_PERFA        (0x30A)
1000
#define SPR_PERFB        (0x30B)
1001
#define SPR_PERFC        (0x30C)
1002
#define SPR_PERFD        (0x30D)
1003
#define SPR_PERFE        (0x30E)
1004
#define SPR_PERFF        (0x30F)
1005
#define SPR_UPERF0       (0x310)
1006
#define SPR_UPERF1       (0x311)
1007
#define SPR_UPERF2       (0x312)
1008
#define SPR_UPERF3       (0x313)
1009
#define SPR_UPERF4       (0x314)
1010
#define SPR_UPERF5       (0x315)
1011
#define SPR_UPERF6       (0x316)
1012
#define SPR_UPERF7       (0x317)
1013
#define SPR_UPERF8       (0x318)
1014
#define SPR_UPERF9       (0x319)
1015
#define SPR_UPERFA       (0x31A)
1016
#define SPR_UPERFB       (0x31B)
1017
#define SPR_UPERFC       (0x31C)
1018
#define SPR_UPERFD       (0x31D)
1019
#define SPR_UPERFE       (0x31E)
1020
#define SPR_UPERFF       (0x31F)
1021
#define SPR_440_INV0     (0x370)
1022
#define SPR_440_INV1     (0x371)
1023
#define SPR_440_INV2     (0x372)
1024
#define SPR_440_INV3     (0x373)
1025
#define SPR_440_ITV0     (0x374)
1026
#define SPR_440_ITV1     (0x375)
1027
#define SPR_440_ITV2     (0x376)
1028
#define SPR_440_ITV3     (0x377)
1029
#define SPR_440_CCR1     (0x378)
1030
#define SPR_DCRIPR       (0x37B)
1031
#define SPR_PPR          (0x380)
1032
#define SPR_440_DNV0     (0x390)
1033
#define SPR_440_DNV1     (0x391)
1034
#define SPR_440_DNV2     (0x392)
1035
#define SPR_440_DNV3     (0x393)
1036
#define SPR_440_DTV0     (0x394)
1037
#define SPR_440_DTV1     (0x395)
1038
#define SPR_440_DTV2     (0x396)
1039
#define SPR_440_DTV3     (0x397)
1040
#define SPR_440_DVLIM    (0x398)
1041
#define SPR_440_IVLIM    (0x399)
1042
#define SPR_440_RSTCFG   (0x39B)
1043
#define SPR_BOOKE_DCDBTRL (0x39C)
1044
#define SPR_BOOKE_DCDBTRH (0x39D)
1045
#define SPR_BOOKE_ICDBTRL (0x39E)
1046
#define SPR_BOOKE_ICDBTRH (0x39F)
1047
#define SPR_UMMCR2       (0x3A0)
1048
#define SPR_UPMC5        (0x3A1)
1049
#define SPR_UPMC6        (0x3A2)
1050
#define SPR_UBAMR        (0x3A7)
1051
#define SPR_UMMCR0       (0x3A8)
1052
#define SPR_UPMC1        (0x3A9)
1053
#define SPR_UPMC2        (0x3AA)
1054
#define SPR_USIAR        (0x3AB)
1055
#define SPR_UMMCR1       (0x3AC)
1056
#define SPR_UPMC3        (0x3AD)
1057
#define SPR_UPMC4        (0x3AE)
1058
#define SPR_USDA         (0x3AF)
1059
#define SPR_40x_ZPR      (0x3B0)
1060
#define SPR_BOOKE_MAS7   (0x3B0)
1061
#define SPR_620_PMR0     (0x3B0)
1062
#define SPR_MMCR2        (0x3B0)
1063
#define SPR_PMC5         (0x3B1)
1064
#define SPR_40x_PID      (0x3B1)
1065
#define SPR_620_PMR1     (0x3B1)
1066
#define SPR_PMC6         (0x3B2)
1067
#define SPR_440_MMUCR    (0x3B2)
1068
#define SPR_620_PMR2     (0x3B2)
1069
#define SPR_4xx_CCR0     (0x3B3)
1070
#define SPR_BOOKE_EPLC   (0x3B3)
1071
#define SPR_620_PMR3     (0x3B3)
1072
#define SPR_405_IAC3     (0x3B4)
1073
#define SPR_BOOKE_EPSC   (0x3B4)
1074
#define SPR_620_PMR4     (0x3B4)
1075
#define SPR_405_IAC4     (0x3B5)
1076
#define SPR_620_PMR5     (0x3B5)
1077
#define SPR_405_DVC1     (0x3B6)
1078
#define SPR_620_PMR6     (0x3B6)
1079
#define SPR_405_DVC2     (0x3B7)
1080
#define SPR_620_PMR7     (0x3B7)
1081
#define SPR_BAMR         (0x3B7)
1082
#define SPR_MMCR0        (0x3B8)
1083
#define SPR_620_PMR8     (0x3B8)
1084
#define SPR_PMC1         (0x3B9)
1085
#define SPR_40x_SGR      (0x3B9)
1086
#define SPR_620_PMR9     (0x3B9)
1087
#define SPR_PMC2         (0x3BA)
1088
#define SPR_40x_DCWR     (0x3BA)
1089
#define SPR_620_PMRA     (0x3BA)
1090
#define SPR_SIAR         (0x3BB)
1091
#define SPR_405_SLER     (0x3BB)
1092
#define SPR_620_PMRB     (0x3BB)
1093
#define SPR_MMCR1        (0x3BC)
1094
#define SPR_405_SU0R     (0x3BC)
1095
#define SPR_620_PMRC     (0x3BC)
1096
#define SPR_401_SKR      (0x3BC)
1097
#define SPR_PMC3         (0x3BD)
1098
#define SPR_405_DBCR1    (0x3BD)
1099
#define SPR_620_PMRD     (0x3BD)
1100
#define SPR_PMC4         (0x3BE)
1101
#define SPR_620_PMRE     (0x3BE)
1102
#define SPR_SDA          (0x3BF)
1103
#define SPR_620_PMRF     (0x3BF)
1104
#define SPR_403_VTBL     (0x3CC)
1105
#define SPR_403_VTBU     (0x3CD)
1106
#define SPR_DMISS        (0x3D0)
1107
#define SPR_DCMP         (0x3D1)
1108
#define SPR_HASH1        (0x3D2)
1109
#define SPR_HASH2        (0x3D3)
1110
#define SPR_BOOKE_ICDBDR (0x3D3)
1111
#define SPR_TLBMISS      (0x3D4)
1112
#define SPR_IMISS        (0x3D4)
1113
#define SPR_40x_ESR      (0x3D4)
1114
#define SPR_PTEHI        (0x3D5)
1115
#define SPR_ICMP         (0x3D5)
1116
#define SPR_40x_DEAR     (0x3D5)
1117
#define SPR_PTELO        (0x3D6)
1118
#define SPR_RPA          (0x3D6)
1119
#define SPR_40x_EVPR     (0x3D6)
1120
#define SPR_L3PM         (0x3D7)
1121
#define SPR_403_CDBCR    (0x3D7)
1122
#define SPR_L3OHCR       (0x3D8)
1123
#define SPR_TCR          (0x3D8)
1124
#define SPR_40x_TSR      (0x3D8)
1125
#define SPR_IBR          (0x3DA)
1126
#define SPR_40x_TCR      (0x3DA)
1127
#define SPR_ESASRR       (0x3DB)
1128
#define SPR_40x_PIT      (0x3DB)
1129
#define SPR_403_TBL      (0x3DC)
1130
#define SPR_403_TBU      (0x3DD)
1131
#define SPR_SEBR         (0x3DE)
1132
#define SPR_40x_SRR2     (0x3DE)
1133
#define SPR_SER          (0x3DF)
1134
#define SPR_40x_SRR3     (0x3DF)
1135
#define SPR_L3ITCR0      (0x3E8)
1136
#define SPR_L3ITCR1      (0x3E9)
1137
#define SPR_L3ITCR2      (0x3EA)
1138
#define SPR_L3ITCR3      (0x3EB)
1139
#define SPR_HID0         (0x3F0)
1140
#define SPR_40x_DBSR     (0x3F0)
1141
#define SPR_HID1         (0x3F1)
1142
#define SPR_IABR         (0x3F2)
1143
#define SPR_40x_DBCR0    (0x3F2)
1144
#define SPR_601_HID2     (0x3F2)
1145
#define SPR_E500_L1CSR0  (0x3F2)
1146
#define SPR_ICTRL        (0x3F3)
1147
#define SPR_HID2         (0x3F3)
1148
#define SPR_E500_L1CSR1  (0x3F3)
1149
#define SPR_440_DBDR     (0x3F3)
1150
#define SPR_LDSTDB       (0x3F4)
1151
#define SPR_40x_IAC1     (0x3F4)
1152
#define SPR_MMUCSR0      (0x3F4)
1153
#define SPR_DABR         (0x3F5)
1154
#define DABR_MASK (~(target_ulong)0x7)
1155
#define SPR_E500_BUCSR   (0x3F5)
1156
#define SPR_40x_IAC2     (0x3F5)
1157
#define SPR_601_HID5     (0x3F5)
1158
#define SPR_40x_DAC1     (0x3F6)
1159
#define SPR_MSSCR0       (0x3F6)
1160
#define SPR_970_HID5     (0x3F6)
1161
#define SPR_MSSSR0       (0x3F7)
1162
#define SPR_DABRX        (0x3F7)
1163
#define SPR_40x_DAC2     (0x3F7)
1164
#define SPR_MMUCFG       (0x3F7)
1165
#define SPR_LDSTCR       (0x3F8)
1166
#define SPR_L2PMCR       (0x3F8)
1167
#define SPR_750_HID2     (0x3F8)
1168
#define SPR_620_HID8     (0x3F8)
1169
#define SPR_L2CR         (0x3F9)
1170
#define SPR_620_HID9     (0x3F9)
1171
#define SPR_L3CR         (0x3FA)
1172
#define SPR_IABR2        (0x3FA)
1173
#define SPR_40x_DCCR     (0x3FA)
1174
#define SPR_ICTC         (0x3FB)
1175
#define SPR_40x_ICCR     (0x3FB)
1176
#define SPR_THRM1        (0x3FC)
1177
#define SPR_403_PBL1     (0x3FC)
1178
#define SPR_SP           (0x3FD)
1179
#define SPR_THRM2        (0x3FD)
1180
#define SPR_403_PBU1     (0x3FD)
1181
#define SPR_604_HID13    (0x3FD)
1182
#define SPR_LT           (0x3FE)
1183
#define SPR_THRM3        (0x3FE)
1184
#define SPR_FPECR        (0x3FE)
1185
#define SPR_403_PBL2     (0x3FE)
1186
#define SPR_PIR          (0x3FF)
1187
#define SPR_403_PBU2     (0x3FF)
1188
#define SPR_601_HID15    (0x3FF)
1189
#define SPR_604_HID15    (0x3FF)
1190
#define SPR_E500_SVR     (0x3FF)
1191

    
1192
/*****************************************************************************/
1193
/* Memory access type :
1194
 * may be needed for precise access rights control and precise exceptions.
1195
 */
1196
enum {
1197
    /* 1 bit to define user level / supervisor access */
1198
    ACCESS_USER  = 0x00,
1199
    ACCESS_SUPER = 0x01,
1200
    /* Type of instruction that generated the access */
1201
    ACCESS_CODE  = 0x10, /* Code fetch access                */
1202
    ACCESS_INT   = 0x20, /* Integer load/store access        */
1203
    ACCESS_FLOAT = 0x30, /* floating point load/store access */
1204
    ACCESS_RES   = 0x40, /* load/store with reservation      */
1205
    ACCESS_EXT   = 0x50, /* external access                  */
1206
    ACCESS_CACHE = 0x60, /* Cache manipulation               */
1207
};
1208

    
1209
/* Hardware interruption sources:
1210
 * all those exception can be raised simulteaneously
1211
 */
1212
/* Input pins definitions */
1213
enum {
1214
    /* 6xx bus input pins */
1215
    PPC6xx_INPUT_HRESET     = 0,
1216
    PPC6xx_INPUT_SRESET     = 1,
1217
    PPC6xx_INPUT_CKSTP_IN   = 2,
1218
    PPC6xx_INPUT_MCP        = 3,
1219
    PPC6xx_INPUT_SMI        = 4,
1220
    PPC6xx_INPUT_INT        = 5,
1221
    PPC6xx_INPUT_TBEN       = 6,
1222
    PPC6xx_INPUT_WAKEUP     = 7,
1223
    PPC6xx_INPUT_NB,
1224
};
1225

    
1226
enum {
1227
    /* Embedded PowerPC input pins */
1228
    PPCBookE_INPUT_HRESET     = 0,
1229
    PPCBookE_INPUT_SRESET     = 1,
1230
    PPCBookE_INPUT_CKSTP_IN   = 2,
1231
    PPCBookE_INPUT_MCP        = 3,
1232
    PPCBookE_INPUT_SMI        = 4,
1233
    PPCBookE_INPUT_INT        = 5,
1234
    PPCBookE_INPUT_CINT       = 6,
1235
    PPCBookE_INPUT_NB,
1236
};
1237

    
1238
enum {
1239
    /* PowerPC 40x input pins */
1240
    PPC40x_INPUT_RESET_CORE = 0,
1241
    PPC40x_INPUT_RESET_CHIP = 1,
1242
    PPC40x_INPUT_RESET_SYS  = 2,
1243
    PPC40x_INPUT_CINT       = 3,
1244
    PPC40x_INPUT_INT        = 4,
1245
    PPC40x_INPUT_HALT       = 5,
1246
    PPC40x_INPUT_DEBUG      = 6,
1247
    PPC40x_INPUT_NB,
1248
};
1249

    
1250
#if defined(TARGET_PPC64)
1251
enum {
1252
    /* PowerPC 970 input pins */
1253
    PPC970_INPUT_HRESET     = 0,
1254
    PPC970_INPUT_SRESET     = 1,
1255
    PPC970_INPUT_CKSTP      = 2,
1256
    PPC970_INPUT_TBEN       = 3,
1257
    PPC970_INPUT_MCP        = 4,
1258
    PPC970_INPUT_INT        = 5,
1259
    PPC970_INPUT_THINT      = 6,
1260
};
1261
#endif
1262

    
1263
/* Hardware exceptions definitions */
1264
enum {
1265
    /* External hardware exception sources */
1266
    PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
1267
    PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
1268
    PPC_INTERRUPT_MCK,            /* Machine check exception              */
1269
    PPC_INTERRUPT_EXT,            /* External interrupt                   */
1270
    PPC_INTERRUPT_SMI,            /* System management interrupt          */
1271
    PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
1272
    PPC_INTERRUPT_DEBUG,          /* External debug exception             */
1273
    PPC_INTERRUPT_THERM,          /* Thermal exception                    */
1274
    /* Internal hardware exception sources */
1275
    PPC_INTERRUPT_DECR,           /* Decrementer exception                */
1276
    PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
1277
    PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
1278
    PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
1279
    PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
1280
    PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
1281
    PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
1282
    PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
1283
};
1284

    
1285
/*****************************************************************************/
1286

    
1287
#endif /* !defined (__CPU_PPC_H__) */