Revision 786c02f1 target-cris/op.c
| b/target-cris/op.c | ||
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void OPPROTO op_break_im(void) |
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{
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env->trapnr = PARAM1;
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env->trap_vector = PARAM1;
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env->exception_index = EXCP_BREAK; |
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cpu_loop_exit(); |
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} |
| ... | ... | |
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/* Apply the ccs shift. */ |
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ccs = env->pregs[PR_CCS]; |
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ccs = (ccs & 0xc0000000) | (ccs >> 10);
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ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
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env->pregs[PR_CCS] = ccs; |
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RETURN(); |
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} |
| ... | ... | |
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RETURN(); |
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} |
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void OPPROTO op_movl_tlb_hi_T0 (void) |
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{
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uint32_t srs; |
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srs = env->pregs[PR_SRS]; |
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if (srs == 1 || srs == 2) |
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{
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/* Writes to tlb-hi write to mm_cause as a side effect. */ |
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env->sregs[SFR_RW_MM_TLB_HI] = T0; |
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env->sregs[SFR_R_MM_CAUSE] = T0; |
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} |
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RETURN(); |
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} |
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void OPPROTO op_movl_tlb_lo_T0 (void) |
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{
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int srs;
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uint32_t srs;
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srs = env->pregs[PR_SRS]; |
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if (srs == 1 || srs == 2) |
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{
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int set;
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int idx;
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uint32_t set;
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uint32_t idx;
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uint32_t lo, hi; |
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|
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idx = set = env->sregs[SFR_RW_MM_TLB_SEL]; |
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set >>= 4; |
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set &= 3; |
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idx &= 31;
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idx &= 15;
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/* We've just made a write to tlb_lo. */ |
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lo = env->sregs[SFR_RW_MM_TLB_LO]; |
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hi = env->sregs[SFR_RW_MM_TLB_HI]; |
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/* Writes are done via r_mm_cause. */ |
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hi = env->sregs[SFR_R_MM_CAUSE]; |
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env->tlbsets[srs - 1][set][idx].lo = lo; |
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env->tlbsets[srs - 1][set][idx].hi = hi; |
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} |
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RETURN(); |
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} |
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