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# Date Author Comment
5dc5d9f0 07/25/2010 05:54 pm Aurelien Jarno

mips: more fixes to the MIPS interrupt glue logic

Commit 36388314febad3d7675ab919287f03733a560ff6 moved most of the
interrupt logic to cpu-exec.c. Remove the remaining useless code
and fix software interrupts.

Signed-off-by: Aurelien Jarno <>...

36388314 07/24/2010 02:40 pm Edgar E. Iglesias

mips: Correct MIPS interrupt glue logic for icount

When hw interrupt pending bits in CP0_Cause are set, the CPU should
see the hw interrupt line as active. The CPU may or may not take the
interrupt based on internal state (global irq mask etc) but the glue...

b970ea8f 03/27/2010 09:26 am Blue Swirl

Compile some MIPS devices only once

Move CPU specific declarations to a separate file.

Signed-off-by: Blue Swirl <>

7b9cbadb 03/15/2010 12:30 am Aurelien Jarno

mips: add header to mips_int.c and mips_timer.c

Signed-off-by: Aurelien Jarno <>

87ecb68b 11/17/2007 07:14 pm pbrook

Break up vl.h.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3674 c046a42c-6fe2-441c-8c8c-71466251a162

d537cf6c 04/07/2007 09:14 pm pbrook

Unify IRQ handling.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2635 c046a42c-6fe2-441c-8c8c-71466251a162

a4bc3afc 03/31/2007 07:54 pm ths

Malta CBUS UART support.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2557 c046a42c-6fe2-441c-8c8c-71466251a162

24c7b0e3 03/30/2007 07:44 pm ths

Sanitize mips exception handling.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2546 c046a42c-6fe2-441c-8c8c-71466251a162

39d51eb8 03/18/2007 02:43 pm ths

Fix BD flag handling, cause register contents, implement some more bits
for R2 interrupt handling.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2493 c046a42c-6fe2-441c-8c8c-71466251a162

4de9b249 01/24/2007 03:47 am ths

Reworking MIPS interrupt handling, by Aurelien Jarno.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2350 c046a42c-6fe2-441c-8c8c-71466251a162