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/* PowerPC hardware exceptions management helpers */
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typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
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typedef struct clk_setup_t clk_setup_t;
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struct clk_setup_t {
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    clk_setup_cb cb;
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    void *opaque;
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};
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static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
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{
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    if (clk->cb != NULL)
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        (*clk->cb)(clk->opaque, freq);
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}
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clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
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/* Embedded PowerPC DCR management */
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typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
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typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
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int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
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                  int (*dcr_write_error)(int dcrn));
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int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
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                      dcr_read_cb drc_read, dcr_write_cb dcr_write);
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clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq,
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                                  unsigned int decr_excp);
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/* Embedded PowerPC reset */
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void ppc40x_core_reset (CPUState *env);
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void ppc40x_chip_reset (CPUState *env);
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void ppc40x_system_reset (CPUState *env);
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void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
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extern CPUWriteMemoryFunc * const PPC_io_write[];
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extern CPUReadMemoryFunc * const PPC_io_read[];
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void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
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void ppc40x_irq_init (CPUState *env);
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void ppce500_irq_init (CPUState *env);
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void ppc6xx_irq_init (CPUState *env);
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void ppc970_irq_init (CPUState *env);
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/* PPC machines for OpenBIOS */
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enum {
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    ARCH_PREP = 0,
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    ARCH_MAC99,
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    ARCH_HEATHROW,
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    ARCH_MAC99_U3,
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};
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#define FW_CFG_PPC_WIDTH        (FW_CFG_ARCH_LOCAL + 0x00)
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#define FW_CFG_PPC_HEIGHT        (FW_CFG_ARCH_LOCAL + 0x01)
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#define FW_CFG_PPC_DEPTH        (FW_CFG_ARCH_LOCAL + 0x02)
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#define FW_CFG_PPC_TBFREQ        (FW_CFG_ARCH_LOCAL + 0x03)
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#define FW_CFG_PPC_IS_KVM       (FW_CFG_ARCH_LOCAL + 0x05)
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#define FW_CFG_PPC_KVM_HC       (FW_CFG_ARCH_LOCAL + 0x06)
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#define FW_CFG_PPC_KVM_PID      (FW_CFG_ARCH_LOCAL + 0x07)
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#define PPC_SERIAL_MM_BAUDBASE 399193