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/*
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* QEMU PC System Emulator
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <stdarg.h> |
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#include <string.h> |
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#include <getopt.h> |
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#include <inttypes.h> |
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#include <unistd.h> |
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#include <sys/mman.h> |
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#include <fcntl.h> |
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#include <signal.h> |
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#include <time.h> |
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#include <sys/time.h> |
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#include <malloc.h> |
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#include <termios.h> |
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#include <sys/poll.h> |
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#include <errno.h> |
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#include <sys/wait.h> |
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#include <sys/ioctl.h> |
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#include <sys/socket.h> |
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#include <linux/if.h> |
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#include <linux/if_tun.h> |
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|
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#include "cpu-i386.h" |
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#include "disas.h" |
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#include "thunk.h" |
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#include "vl.h" |
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|
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#define DEBUG_LOGFILE "/tmp/vl.log" |
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#define DEFAULT_NETWORK_SCRIPT "/etc/vl-ifup" |
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|
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//#define DEBUG_UNUSED_IOPORT
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//#define DEBUG_IRQ_LATENCY
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|
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#define PHYS_RAM_BASE 0xac000000 |
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#define PHYS_RAM_MAX_SIZE (256 * 1024 * 1024) |
61 |
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#define KERNEL_LOAD_ADDR 0x00100000 |
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#define INITRD_LOAD_ADDR 0x00400000 |
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#define KERNEL_PARAMS_ADDR 0x00090000 |
65 |
|
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/* from plex86 (BSD license) */
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struct __attribute__ ((packed)) linux_params {
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// For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
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// I just padded out the VESA parts, rather than define them.
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/* 0x000 */ uint8_t orig_x;
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/* 0x001 */ uint8_t orig_y;
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/* 0x002 */ uint16_t ext_mem_k;
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/* 0x004 */ uint16_t orig_video_page;
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/* 0x006 */ uint8_t orig_video_mode;
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/* 0x007 */ uint8_t orig_video_cols;
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/* 0x008 */ uint16_t unused1;
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/* 0x00a */ uint16_t orig_video_ega_bx;
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/* 0x00c */ uint16_t unused2;
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/* 0x00e */ uint8_t orig_video_lines;
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/* 0x00f */ uint8_t orig_video_isVGA;
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/* 0x010 */ uint16_t orig_video_points;
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/* 0x012 */ uint8_t pad0[0x20 - 0x12]; // VESA info. |
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/* 0x020 */ uint16_t cl_magic; // Commandline magic number (0xA33F) |
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/* 0x022 */ uint16_t cl_offset; // Commandline offset. Address of commandline |
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// is calculated as 0x90000 + cl_offset, bu
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// only if cl_magic == 0xA33F.
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/* 0x024 */ uint8_t pad1[0x40 - 0x24]; // VESA info. |
89 |
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/* 0x040 */ uint8_t apm_bios_info[20]; // struct apm_bios_info |
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/* 0x054 */ uint8_t pad2[0x80 - 0x54]; |
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// Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h.
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// Might be truncated?
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/* 0x080 */ uint8_t hd0_info[16]; // hd0-disk-parameter from intvector 0x41 |
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/* 0x090 */ uint8_t hd1_info[16]; // hd1-disk-parameter from intvector 0x46 |
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// System description table truncated to 16 bytes
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// From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c.
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/* 0x0a0 */ uint16_t sys_description_len;
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/* 0x0a2 */ uint8_t sys_description_table[14]; |
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// [0] machine id
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// [1] machine submodel id
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// [2] BIOS revision
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// [3] bit1: MCA bus
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/* 0x0b0 */ uint8_t pad3[0x1e0 - 0xb0]; |
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/* 0x1e0 */ uint32_t alt_mem_k;
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/* 0x1e4 */ uint8_t pad4[4]; |
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/* 0x1e8 */ uint8_t e820map_entries;
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/* 0x1e9 */ uint8_t eddbuf_entries; // EDD_NR |
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/* 0x1ea */ uint8_t pad5[0x1f1 - 0x1ea]; |
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/* 0x1f1 */ uint8_t setup_sects; // size of setup.S, number of sectors |
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/* 0x1f2 */ uint16_t mount_root_rdonly; // MOUNT_ROOT_RDONLY (if !=0) |
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/* 0x1f4 */ uint16_t sys_size; // size of compressed kernel-part in the |
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// (b)zImage-file (in 16 byte units, rounded up)
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/* 0x1f6 */ uint16_t swap_dev; // (unused AFAIK) |
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/* 0x1f8 */ uint16_t ramdisk_flags;
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/* 0x1fa */ uint16_t vga_mode; // (old one) |
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/* 0x1fc */ uint16_t orig_root_dev; // (high=Major, low=minor) |
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/* 0x1fe */ uint8_t pad6[1]; |
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/* 0x1ff */ uint8_t aux_device_info;
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/* 0x200 */ uint16_t jump_setup; // Jump to start of setup code, |
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// aka "reserved" field.
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/* 0x202 */ uint8_t setup_signature[4]; // Signature for SETUP-header, ="HdrS" |
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/* 0x206 */ uint16_t header_format_version; // Version number of header format; |
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/* 0x208 */ uint8_t setup_S_temp0[8]; // Used by setup.S for communication with |
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// boot loaders, look there.
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/* 0x210 */ uint8_t loader_type;
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// 0 for old one.
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// else 0xTV:
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// T=0: LILO
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// T=1: Loadlin
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// T=2: bootsect-loader
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// T=3: SYSLINUX
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// T=4: ETHERBOOT
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// V=version
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/* 0x211 */ uint8_t loadflags;
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// bit0 = 1: kernel is loaded high (bzImage)
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// bit7 = 1: Heap and pointer (see below) set by boot
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// loader.
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/* 0x212 */ uint16_t setup_S_temp1;
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/* 0x214 */ uint32_t kernel_start;
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/* 0x218 */ uint32_t initrd_start;
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/* 0x21c */ uint32_t initrd_size;
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/* 0x220 */ uint8_t setup_S_temp2[4]; |
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/* 0x224 */ uint16_t setup_S_heap_end_pointer;
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/* 0x226 */ uint8_t pad7[0x2d0 - 0x226]; |
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/* 0x2d0 : Int 15, ax=e820 memory map. */
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// (linux/include/asm-i386/e820.h, 'struct e820entry')
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#define E820MAX 32 |
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#define E820_RAM 1 |
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#define E820_RESERVED 2 |
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#define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */ |
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#define E820_NVS 4 |
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struct {
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uint64_t addr; |
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uint64_t size; |
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uint32_t type; |
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} e820map[E820MAX]; |
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/* 0x550 */ uint8_t pad8[0x600 - 0x550]; |
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// BIOS Enhanced Disk Drive Services.
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// (From linux/include/asm-i386/edd.h, 'struct edd_info')
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// Each 'struct edd_info is 78 bytes, times a max of 6 structs in array.
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/* 0x600 */ uint8_t eddbuf[0x7d4 - 0x600]; |
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/* 0x7d4 */ uint8_t pad9[0x800 - 0x7d4]; |
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/* 0x800 */ uint8_t commandline[0x800]; |
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/* 0x1000 */
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uint64_t gdt_table[256];
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uint64_t idt_table[48];
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}; |
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#define KERNEL_CS 0x10 |
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#define KERNEL_DS 0x18 |
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typedef void (IOPortWriteFunc)(CPUX86State *env, uint32_t address, uint32_t data); |
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typedef uint32_t (IOPortReadFunc)(CPUX86State *env, uint32_t address);
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#define MAX_IOPORTS 4096 |
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char phys_ram_file[1024]; |
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CPUX86State *global_env; |
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CPUX86State *cpu_single_env; |
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FILE *logfile = NULL;
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int loglevel;
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IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
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IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
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/***********************************************************/
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/* x86 io ports */
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uint32_t default_ioport_readb(CPUX86State *env, uint32_t address) |
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{ |
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#ifdef DEBUG_UNUSED_IOPORT
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fprintf(stderr, "inb: port=0x%04x\n", address);
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#endif
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return 0xff; |
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} |
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void default_ioport_writeb(CPUX86State *env, uint32_t address, uint32_t data)
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{ |
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#ifdef DEBUG_UNUSED_IOPORT
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fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data);
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#endif
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} |
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/* default is to make two byte accesses */
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uint32_t default_ioport_readw(CPUX86State *env, uint32_t address) |
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{ |
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uint32_t data; |
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data = ioport_read_table[0][address](env, address);
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data |= ioport_read_table[0][address + 1](env, address + 1) << 8; |
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return data;
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} |
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void default_ioport_writew(CPUX86State *env, uint32_t address, uint32_t data)
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{ |
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ioport_write_table[0][address](env, address, data & 0xff); |
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ioport_write_table[0][address + 1](env, address + 1, (data >> 8) & 0xff); |
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} |
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uint32_t default_ioport_readl(CPUX86State *env, uint32_t address) |
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{ |
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#ifdef DEBUG_UNUSED_IOPORT
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fprintf(stderr, "inl: port=0x%04x\n", address);
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#endif
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return 0xffffffff; |
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} |
234 |
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void default_ioport_writel(CPUX86State *env, uint32_t address, uint32_t data)
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{ |
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#ifdef DEBUG_UNUSED_IOPORT
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fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data);
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#endif
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} |
241 |
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void init_ioports(void) |
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{ |
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int i;
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for(i = 0; i < MAX_IOPORTS; i++) { |
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ioport_read_table[0][i] = default_ioport_readb;
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ioport_write_table[0][i] = default_ioport_writeb;
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ioport_read_table[1][i] = default_ioport_readw;
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ioport_write_table[1][i] = default_ioport_writew;
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ioport_read_table[2][i] = default_ioport_readl;
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ioport_write_table[2][i] = default_ioport_writel;
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} |
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} |
255 |
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/* size is the word size in byte */
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int register_ioport_read(int start, int length, IOPortReadFunc *func, int size) |
258 |
{ |
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int i, bsize;
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260 |
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if (size == 1) |
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bsize = 0;
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else if (size == 2) |
264 |
bsize = 1;
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else if (size == 4) |
266 |
bsize = 2;
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else
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return -1; |
269 |
for(i = start; i < start + length; i += size)
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ioport_read_table[bsize][i] = func; |
271 |
return 0; |
272 |
} |
273 |
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/* size is the word size in byte */
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int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size) |
276 |
{ |
277 |
int i, bsize;
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278 |
|
279 |
if (size == 1) |
280 |
bsize = 0;
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else if (size == 2) |
282 |
bsize = 1;
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283 |
else if (size == 4) |
284 |
bsize = 2;
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285 |
else
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286 |
return -1; |
287 |
for(i = start; i < start + length; i += size)
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ioport_write_table[bsize][i] = func; |
289 |
return 0; |
290 |
} |
291 |
|
292 |
void pstrcpy(char *buf, int buf_size, const char *str) |
293 |
{ |
294 |
int c;
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295 |
char *q = buf;
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296 |
|
297 |
if (buf_size <= 0) |
298 |
return;
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299 |
|
300 |
for(;;) {
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301 |
c = *str++; |
302 |
if (c == 0 || q >= buf + buf_size - 1) |
303 |
break;
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304 |
*q++ = c; |
305 |
} |
306 |
*q = '\0';
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} |
308 |
|
309 |
/* strcat and truncate. */
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310 |
char *pstrcat(char *buf, int buf_size, const char *s) |
311 |
{ |
312 |
int len;
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len = strlen(buf); |
314 |
if (len < buf_size)
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pstrcpy(buf + len, buf_size - len, s); |
316 |
return buf;
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317 |
} |
318 |
|
319 |
int load_kernel(const char *filename, uint8_t *addr) |
320 |
{ |
321 |
int fd, size, setup_sects;
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322 |
uint8_t bootsect[512];
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323 |
|
324 |
fd = open(filename, O_RDONLY); |
325 |
if (fd < 0) |
326 |
return -1; |
327 |
if (read(fd, bootsect, 512) != 512) |
328 |
goto fail;
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329 |
setup_sects = bootsect[0x1F1];
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330 |
if (!setup_sects)
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setup_sects = 4;
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332 |
/* skip 16 bit setup code */
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lseek(fd, (setup_sects + 1) * 512, SEEK_SET); |
334 |
size = read(fd, addr, 16 * 1024 * 1024); |
335 |
if (size < 0) |
336 |
goto fail;
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337 |
close(fd); |
338 |
return size;
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339 |
fail:
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340 |
close(fd); |
341 |
return -1; |
342 |
} |
343 |
|
344 |
/* return the size or -1 if error */
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345 |
int load_image(const char *filename, uint8_t *addr) |
346 |
{ |
347 |
int fd, size;
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348 |
fd = open(filename, O_RDONLY); |
349 |
if (fd < 0) |
350 |
return -1; |
351 |
size = lseek(fd, 0, SEEK_END);
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352 |
lseek(fd, 0, SEEK_SET);
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353 |
if (read(fd, addr, size) != size) {
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354 |
close(fd); |
355 |
return -1; |
356 |
} |
357 |
close(fd); |
358 |
return size;
|
359 |
} |
360 |
|
361 |
void cpu_x86_outb(CPUX86State *env, int addr, int val) |
362 |
{ |
363 |
ioport_write_table[0][addr & (MAX_IOPORTS - 1)](env, addr, val); |
364 |
} |
365 |
|
366 |
void cpu_x86_outw(CPUX86State *env, int addr, int val) |
367 |
{ |
368 |
ioport_write_table[1][addr & (MAX_IOPORTS - 1)](env, addr, val); |
369 |
} |
370 |
|
371 |
void cpu_x86_outl(CPUX86State *env, int addr, int val) |
372 |
{ |
373 |
ioport_write_table[2][addr & (MAX_IOPORTS - 1)](env, addr, val); |
374 |
} |
375 |
|
376 |
int cpu_x86_inb(CPUX86State *env, int addr) |
377 |
{ |
378 |
return ioport_read_table[0][addr & (MAX_IOPORTS - 1)](env, addr); |
379 |
} |
380 |
|
381 |
int cpu_x86_inw(CPUX86State *env, int addr) |
382 |
{ |
383 |
return ioport_read_table[1][addr & (MAX_IOPORTS - 1)](env, addr); |
384 |
} |
385 |
|
386 |
int cpu_x86_inl(CPUX86State *env, int addr) |
387 |
{ |
388 |
return ioport_read_table[2][addr & (MAX_IOPORTS - 1)](env, addr); |
389 |
} |
390 |
|
391 |
/***********************************************************/
|
392 |
void ioport80_write(CPUX86State *env, uint32_t addr, uint32_t data)
|
393 |
{ |
394 |
} |
395 |
|
396 |
void hw_error(const char *fmt, ...) |
397 |
{ |
398 |
va_list ap; |
399 |
|
400 |
va_start(ap, fmt); |
401 |
fprintf(stderr, "qemu: hardware error: ");
|
402 |
vfprintf(stderr, fmt, ap); |
403 |
fprintf(stderr, "\n");
|
404 |
#ifdef TARGET_I386
|
405 |
cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP); |
406 |
#endif
|
407 |
va_end(ap); |
408 |
abort(); |
409 |
} |
410 |
|
411 |
/***********************************************************/
|
412 |
/* vga emulation */
|
413 |
static uint8_t vga_index;
|
414 |
static uint8_t vga_regs[256]; |
415 |
static int last_cursor_pos; |
416 |
|
417 |
void update_console_messages(void) |
418 |
{ |
419 |
int c, i, cursor_pos, eol;
|
420 |
|
421 |
cursor_pos = vga_regs[0x0f] | (vga_regs[0x0e] << 8); |
422 |
eol = 0;
|
423 |
for(i = last_cursor_pos; i < cursor_pos; i++) {
|
424 |
c = phys_ram_base[0xb8000 + (i) * 2]; |
425 |
if (c >= ' ') { |
426 |
putchar(c); |
427 |
eol = 0;
|
428 |
} else {
|
429 |
if (!eol)
|
430 |
putchar('\n');
|
431 |
eol = 1;
|
432 |
} |
433 |
} |
434 |
fflush(stdout); |
435 |
last_cursor_pos = cursor_pos; |
436 |
} |
437 |
|
438 |
/* just to see first Linux console messages, we intercept cursor position */
|
439 |
void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
|
440 |
{ |
441 |
switch(addr) {
|
442 |
case 0x3d4: |
443 |
vga_index = data; |
444 |
break;
|
445 |
case 0x3d5: |
446 |
vga_regs[vga_index] = data; |
447 |
if (vga_index == 0x0f) |
448 |
update_console_messages(); |
449 |
break;
|
450 |
} |
451 |
|
452 |
} |
453 |
|
454 |
/***********************************************************/
|
455 |
/* cmos emulation */
|
456 |
|
457 |
#define RTC_SECONDS 0 |
458 |
#define RTC_SECONDS_ALARM 1 |
459 |
#define RTC_MINUTES 2 |
460 |
#define RTC_MINUTES_ALARM 3 |
461 |
#define RTC_HOURS 4 |
462 |
#define RTC_HOURS_ALARM 5 |
463 |
#define RTC_ALARM_DONT_CARE 0xC0 |
464 |
|
465 |
#define RTC_DAY_OF_WEEK 6 |
466 |
#define RTC_DAY_OF_MONTH 7 |
467 |
#define RTC_MONTH 8 |
468 |
#define RTC_YEAR 9 |
469 |
|
470 |
#define RTC_REG_A 10 |
471 |
#define RTC_REG_B 11 |
472 |
#define RTC_REG_C 12 |
473 |
#define RTC_REG_D 13 |
474 |
|
475 |
/* PC cmos mappings */
|
476 |
#define REG_EQUIPMENT_BYTE 0x14 |
477 |
|
478 |
uint8_t cmos_data[128];
|
479 |
uint8_t cmos_index; |
480 |
|
481 |
void cmos_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
|
482 |
{ |
483 |
if (addr == 0x70) { |
484 |
cmos_index = data & 0x7f;
|
485 |
} |
486 |
} |
487 |
|
488 |
uint32_t cmos_ioport_read(CPUX86State *env, uint32_t addr) |
489 |
{ |
490 |
int ret;
|
491 |
|
492 |
if (addr == 0x70) { |
493 |
return 0xff; |
494 |
} else {
|
495 |
/* toggle update-in-progress bit for Linux (same hack as
|
496 |
plex86) */
|
497 |
ret = cmos_data[cmos_index]; |
498 |
if (cmos_index == RTC_REG_A)
|
499 |
cmos_data[RTC_REG_A] ^= 0x80;
|
500 |
else if (cmos_index == RTC_REG_C) |
501 |
cmos_data[RTC_REG_C] = 0x00;
|
502 |
return ret;
|
503 |
} |
504 |
} |
505 |
|
506 |
|
507 |
static inline int to_bcd(int a) |
508 |
{ |
509 |
return ((a / 10) << 4) | (a % 10); |
510 |
} |
511 |
|
512 |
void cmos_init(void) |
513 |
{ |
514 |
struct tm *tm;
|
515 |
time_t ti; |
516 |
|
517 |
ti = time(NULL);
|
518 |
tm = gmtime(&ti); |
519 |
cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec); |
520 |
cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min); |
521 |
cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour); |
522 |
cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday); |
523 |
cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday); |
524 |
cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon + 1);
|
525 |
cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100);
|
526 |
|
527 |
cmos_data[RTC_REG_A] = 0x26;
|
528 |
cmos_data[RTC_REG_B] = 0x02;
|
529 |
cmos_data[RTC_REG_C] = 0x00;
|
530 |
cmos_data[RTC_REG_D] = 0x80;
|
531 |
|
532 |
cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */ |
533 |
|
534 |
register_ioport_write(0x70, 2, cmos_ioport_write, 1); |
535 |
register_ioport_read(0x70, 2, cmos_ioport_read, 1); |
536 |
} |
537 |
|
538 |
/***********************************************************/
|
539 |
/* 8259 pic emulation */
|
540 |
|
541 |
//#define DEBUG_PIC
|
542 |
|
543 |
typedef struct PicState { |
544 |
uint8_t last_irr; /* edge detection */
|
545 |
uint8_t irr; /* interrupt request register */
|
546 |
uint8_t imr; /* interrupt mask register */
|
547 |
uint8_t isr; /* interrupt service register */
|
548 |
uint8_t priority_add; /* used to compute irq priority */
|
549 |
uint8_t irq_base; |
550 |
uint8_t read_reg_select; |
551 |
uint8_t special_mask; |
552 |
uint8_t init_state; |
553 |
uint8_t auto_eoi; |
554 |
uint8_t rotate_on_autoeoi; |
555 |
uint8_t init4; /* true if 4 byte init */
|
556 |
} PicState; |
557 |
|
558 |
/* 0 is master pic, 1 is slave pic */
|
559 |
PicState pics[2];
|
560 |
int pic_irq_requested;
|
561 |
|
562 |
/* set irq level. If an edge is detected, then the IRR is set to 1 */
|
563 |
static inline void pic_set_irq1(PicState *s, int irq, int level) |
564 |
{ |
565 |
int mask;
|
566 |
mask = 1 << irq;
|
567 |
if (level) {
|
568 |
if ((s->last_irr & mask) == 0) |
569 |
s->irr |= mask; |
570 |
s->last_irr |= mask; |
571 |
} else {
|
572 |
s->last_irr &= ~mask; |
573 |
} |
574 |
} |
575 |
|
576 |
static inline int get_priority(PicState *s, int mask) |
577 |
{ |
578 |
int priority;
|
579 |
if (mask == 0) |
580 |
return -1; |
581 |
priority = 7;
|
582 |
while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) |
583 |
priority--; |
584 |
return priority;
|
585 |
} |
586 |
|
587 |
/* return the pic wanted interrupt. return -1 if none */
|
588 |
static int pic_get_irq(PicState *s) |
589 |
{ |
590 |
int mask, cur_priority, priority;
|
591 |
|
592 |
mask = s->irr & ~s->imr; |
593 |
priority = get_priority(s, mask); |
594 |
if (priority < 0) |
595 |
return -1; |
596 |
/* compute current priority */
|
597 |
cur_priority = get_priority(s, s->isr); |
598 |
if (priority > cur_priority) {
|
599 |
/* higher priority found: an irq should be generated */
|
600 |
return priority;
|
601 |
} else {
|
602 |
return -1; |
603 |
} |
604 |
} |
605 |
|
606 |
/* raise irq to CPU if necessary. must be called every time the active
|
607 |
irq may change */
|
608 |
static void pic_update_irq(void) |
609 |
{ |
610 |
int irq2, irq;
|
611 |
|
612 |
/* first look at slave pic */
|
613 |
irq2 = pic_get_irq(&pics[1]);
|
614 |
if (irq2 >= 0) { |
615 |
/* if irq request by slave pic, signal master PIC */
|
616 |
pic_set_irq1(&pics[0], 2, 1); |
617 |
pic_set_irq1(&pics[0], 2, 0); |
618 |
} |
619 |
/* look at requested irq */
|
620 |
irq = pic_get_irq(&pics[0]);
|
621 |
if (irq >= 0) { |
622 |
if (irq == 2) { |
623 |
/* from slave pic */
|
624 |
pic_irq_requested = 8 + irq2;
|
625 |
} else {
|
626 |
/* from master pic */
|
627 |
pic_irq_requested = irq; |
628 |
} |
629 |
cpu_x86_interrupt(global_env, CPU_INTERRUPT_HARD); |
630 |
} |
631 |
} |
632 |
|
633 |
#ifdef DEBUG_IRQ_LATENCY
|
634 |
int64_t irq_time[16];
|
635 |
int64_t cpu_get_ticks(void);
|
636 |
#endif
|
637 |
#ifdef DEBUG_PIC
|
638 |
int irq_level[16]; |
639 |
#endif
|
640 |
|
641 |
void pic_set_irq(int irq, int level) |
642 |
{ |
643 |
#ifdef DEBUG_PIC
|
644 |
if (level != irq_level[irq]) {
|
645 |
printf("pic_set_irq: irq=%d level=%d\n", irq, level);
|
646 |
irq_level[irq] = level; |
647 |
} |
648 |
#endif
|
649 |
#ifdef DEBUG_IRQ_LATENCY
|
650 |
if (level) {
|
651 |
irq_time[irq] = cpu_get_ticks(); |
652 |
} |
653 |
#endif
|
654 |
pic_set_irq1(&pics[irq >> 3], irq & 7, level); |
655 |
pic_update_irq(); |
656 |
} |
657 |
|
658 |
int cpu_x86_get_pic_interrupt(CPUX86State *env)
|
659 |
{ |
660 |
int irq, irq2, intno;
|
661 |
|
662 |
/* signal the pic that the irq was acked by the CPU */
|
663 |
irq = pic_irq_requested; |
664 |
#ifdef DEBUG_IRQ_LATENCY
|
665 |
printf("IRQ%d latency=%Ld\n", irq, cpu_get_ticks() - irq_time[irq]);
|
666 |
#endif
|
667 |
#ifdef DEBUG_PIC
|
668 |
printf("pic_interrupt: irq=%d\n", irq);
|
669 |
#endif
|
670 |
|
671 |
if (irq >= 8) { |
672 |
irq2 = irq & 7;
|
673 |
pics[1].isr |= (1 << irq2); |
674 |
pics[1].irr &= ~(1 << irq2); |
675 |
irq = 2;
|
676 |
intno = pics[1].irq_base + irq2;
|
677 |
} else {
|
678 |
intno = pics[0].irq_base + irq;
|
679 |
} |
680 |
pics[0].isr |= (1 << irq); |
681 |
pics[0].irr &= ~(1 << irq); |
682 |
return intno;
|
683 |
} |
684 |
|
685 |
void pic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
686 |
{ |
687 |
PicState *s; |
688 |
int priority;
|
689 |
|
690 |
#ifdef DEBUG_PIC
|
691 |
printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
|
692 |
#endif
|
693 |
s = &pics[addr >> 7];
|
694 |
addr &= 1;
|
695 |
if (addr == 0) { |
696 |
if (val & 0x10) { |
697 |
/* init */
|
698 |
memset(s, 0, sizeof(PicState)); |
699 |
s->init_state = 1;
|
700 |
s->init4 = val & 1;
|
701 |
if (val & 0x02) |
702 |
hw_error("single mode not supported");
|
703 |
if (val & 0x08) |
704 |
hw_error("level sensitive irq not supported");
|
705 |
} else if (val & 0x08) { |
706 |
if (val & 0x02) |
707 |
s->read_reg_select = val & 1;
|
708 |
if (val & 0x40) |
709 |
s->special_mask = (val >> 5) & 1; |
710 |
} else {
|
711 |
switch(val) {
|
712 |
case 0x00: |
713 |
case 0x80: |
714 |
s->rotate_on_autoeoi = val >> 7;
|
715 |
break;
|
716 |
case 0x20: /* end of interrupt */ |
717 |
case 0xa0: |
718 |
priority = get_priority(s, s->isr); |
719 |
if (priority >= 0) { |
720 |
s->isr &= ~(1 << ((priority + s->priority_add) & 7)); |
721 |
} |
722 |
if (val == 0xa0) |
723 |
s->priority_add = (s->priority_add + 1) & 7; |
724 |
break;
|
725 |
case 0x60 ... 0x67: |
726 |
priority = val & 7;
|
727 |
s->isr &= ~(1 << priority);
|
728 |
break;
|
729 |
case 0xc0 ... 0xc7: |
730 |
s->priority_add = (val + 1) & 7; |
731 |
break;
|
732 |
case 0xe0 ... 0xe7: |
733 |
priority = val & 7;
|
734 |
s->isr &= ~(1 << priority);
|
735 |
s->priority_add = (priority + 1) & 7; |
736 |
break;
|
737 |
} |
738 |
} |
739 |
} else {
|
740 |
switch(s->init_state) {
|
741 |
case 0: |
742 |
/* normal mode */
|
743 |
s->imr = val; |
744 |
pic_update_irq(); |
745 |
break;
|
746 |
case 1: |
747 |
s->irq_base = val & 0xf8;
|
748 |
s->init_state = 2;
|
749 |
break;
|
750 |
case 2: |
751 |
if (s->init4) {
|
752 |
s->init_state = 3;
|
753 |
} else {
|
754 |
s->init_state = 0;
|
755 |
} |
756 |
break;
|
757 |
case 3: |
758 |
s->auto_eoi = (val >> 1) & 1; |
759 |
s->init_state = 0;
|
760 |
break;
|
761 |
} |
762 |
} |
763 |
} |
764 |
|
765 |
uint32_t pic_ioport_read(CPUX86State *env, uint32_t addr1) |
766 |
{ |
767 |
PicState *s; |
768 |
unsigned int addr; |
769 |
int ret;
|
770 |
|
771 |
addr = addr1; |
772 |
s = &pics[addr >> 7];
|
773 |
addr &= 1;
|
774 |
if (addr == 0) { |
775 |
if (s->read_reg_select)
|
776 |
ret = s->isr; |
777 |
else
|
778 |
ret = s->irr; |
779 |
} else {
|
780 |
ret = s->imr; |
781 |
} |
782 |
#ifdef DEBUG_PIC
|
783 |
printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
|
784 |
#endif
|
785 |
return ret;
|
786 |
} |
787 |
|
788 |
void pic_init(void) |
789 |
{ |
790 |
register_ioport_write(0x20, 2, pic_ioport_write, 1); |
791 |
register_ioport_read(0x20, 2, pic_ioport_read, 1); |
792 |
register_ioport_write(0xa0, 2, pic_ioport_write, 1); |
793 |
register_ioport_read(0xa0, 2, pic_ioport_read, 1); |
794 |
} |
795 |
|
796 |
/***********************************************************/
|
797 |
/* 8253 PIT emulation */
|
798 |
|
799 |
#define PIT_FREQ 1193182 |
800 |
|
801 |
#define RW_STATE_LSB 0 |
802 |
#define RW_STATE_MSB 1 |
803 |
#define RW_STATE_WORD0 2 |
804 |
#define RW_STATE_WORD1 3 |
805 |
#define RW_STATE_LATCHED_WORD0 4 |
806 |
#define RW_STATE_LATCHED_WORD1 5 |
807 |
|
808 |
typedef struct PITChannelState { |
809 |
int count; /* can be 65536 */ |
810 |
uint16_t latched_count; |
811 |
uint8_t rw_state; |
812 |
uint8_t mode; |
813 |
uint8_t bcd; /* not supported */
|
814 |
uint8_t gate; /* timer start */
|
815 |
int64_t count_load_time; |
816 |
int64_t count_last_edge_check_time; |
817 |
} PITChannelState; |
818 |
|
819 |
PITChannelState pit_channels[3];
|
820 |
int speaker_data_on;
|
821 |
int pit_min_timer_count = 0; |
822 |
|
823 |
int64_t ticks_per_sec; |
824 |
|
825 |
int64_t get_clock(void)
|
826 |
{ |
827 |
struct timeval tv;
|
828 |
gettimeofday(&tv, NULL);
|
829 |
return tv.tv_sec * 1000000LL + tv.tv_usec; |
830 |
} |
831 |
|
832 |
int64_t cpu_get_ticks(void)
|
833 |
{ |
834 |
int64_t val; |
835 |
asm("rdtsc" : "=A" (val)); |
836 |
return val;
|
837 |
} |
838 |
|
839 |
void cpu_calibrate_ticks(void) |
840 |
{ |
841 |
int64_t usec, ticks; |
842 |
|
843 |
usec = get_clock(); |
844 |
ticks = cpu_get_ticks(); |
845 |
usleep(50 * 1000); |
846 |
usec = get_clock() - usec; |
847 |
ticks = cpu_get_ticks() - ticks; |
848 |
ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec; |
849 |
} |
850 |
|
851 |
/* compute with 96 bit intermediate result: (a*b)/c */
|
852 |
static uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
|
853 |
{ |
854 |
union {
|
855 |
uint64_t ll; |
856 |
struct {
|
857 |
#ifdef WORDS_BIGENDIAN
|
858 |
uint32_t high, low; |
859 |
#else
|
860 |
uint32_t low, high; |
861 |
#endif
|
862 |
} l; |
863 |
} u, res; |
864 |
uint64_t rl, rh; |
865 |
|
866 |
u.ll = a; |
867 |
rl = (uint64_t)u.l.low * (uint64_t)b; |
868 |
rh = (uint64_t)u.l.high * (uint64_t)b; |
869 |
rh += (rl >> 32);
|
870 |
res.l.high = rh / c; |
871 |
res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c; |
872 |
return res.ll;
|
873 |
} |
874 |
|
875 |
static int pit_get_count(PITChannelState *s) |
876 |
{ |
877 |
uint64_t d; |
878 |
int counter;
|
879 |
|
880 |
d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec); |
881 |
switch(s->mode) {
|
882 |
case 0: |
883 |
case 1: |
884 |
case 4: |
885 |
case 5: |
886 |
counter = (s->count - d) & 0xffff;
|
887 |
break;
|
888 |
default:
|
889 |
counter = s->count - (d % s->count); |
890 |
break;
|
891 |
} |
892 |
return counter;
|
893 |
} |
894 |
|
895 |
/* get pit output bit */
|
896 |
static int pit_get_out(PITChannelState *s) |
897 |
{ |
898 |
uint64_t d; |
899 |
int out;
|
900 |
|
901 |
d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec); |
902 |
switch(s->mode) {
|
903 |
default:
|
904 |
case 0: |
905 |
out = (d >= s->count); |
906 |
break;
|
907 |
case 1: |
908 |
out = (d < s->count); |
909 |
break;
|
910 |
case 2: |
911 |
if ((d % s->count) == 0 && d != 0) |
912 |
out = 1;
|
913 |
else
|
914 |
out = 0;
|
915 |
break;
|
916 |
case 3: |
917 |
out = (d % s->count) < (s->count >> 1);
|
918 |
break;
|
919 |
case 4: |
920 |
case 5: |
921 |
out = (d == s->count); |
922 |
break;
|
923 |
} |
924 |
return out;
|
925 |
} |
926 |
|
927 |
/* get the number of 0 to 1 transitions we had since we call this
|
928 |
function */
|
929 |
/* XXX: maybe better to use ticks precision to avoid getting edges
|
930 |
twice if checks are done at very small intervals */
|
931 |
static int pit_get_out_edges(PITChannelState *s) |
932 |
{ |
933 |
uint64_t d1, d2; |
934 |
int64_t ticks; |
935 |
int ret, v;
|
936 |
|
937 |
ticks = cpu_get_ticks(); |
938 |
d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time, |
939 |
PIT_FREQ, ticks_per_sec); |
940 |
d2 = muldiv64(ticks - s->count_load_time, |
941 |
PIT_FREQ, ticks_per_sec); |
942 |
s->count_last_edge_check_time = ticks; |
943 |
switch(s->mode) {
|
944 |
default:
|
945 |
case 0: |
946 |
if (d1 < s->count && d2 >= s->count)
|
947 |
ret = 1;
|
948 |
else
|
949 |
ret = 0;
|
950 |
break;
|
951 |
case 1: |
952 |
ret = 0;
|
953 |
break;
|
954 |
case 2: |
955 |
d1 /= s->count; |
956 |
d2 /= s->count; |
957 |
ret = d2 - d1; |
958 |
break;
|
959 |
case 3: |
960 |
v = s->count - (s->count >> 1);
|
961 |
d1 = (d1 + v) / s->count; |
962 |
d2 = (d2 + v) / s->count; |
963 |
ret = d2 - d1; |
964 |
break;
|
965 |
case 4: |
966 |
case 5: |
967 |
if (d1 < s->count && d2 >= s->count)
|
968 |
ret = 1;
|
969 |
else
|
970 |
ret = 0;
|
971 |
break;
|
972 |
} |
973 |
return ret;
|
974 |
} |
975 |
|
976 |
static inline void pit_load_count(PITChannelState *s, int val) |
977 |
{ |
978 |
if (val == 0) |
979 |
val = 0x10000;
|
980 |
s->count_load_time = cpu_get_ticks(); |
981 |
s->count_last_edge_check_time = s->count_load_time; |
982 |
s->count = val; |
983 |
if (s == &pit_channels[0] && val <= pit_min_timer_count) { |
984 |
fprintf(stderr, |
985 |
"\nWARNING: vl: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
|
986 |
PIT_FREQ / pit_min_timer_count); |
987 |
} |
988 |
} |
989 |
|
990 |
void pit_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
991 |
{ |
992 |
int channel, access;
|
993 |
PITChannelState *s; |
994 |
|
995 |
addr &= 3;
|
996 |
if (addr == 3) { |
997 |
channel = val >> 6;
|
998 |
if (channel == 3) |
999 |
return;
|
1000 |
s = &pit_channels[channel]; |
1001 |
access = (val >> 4) & 3; |
1002 |
switch(access) {
|
1003 |
case 0: |
1004 |
s->latched_count = pit_get_count(s); |
1005 |
s->rw_state = RW_STATE_LATCHED_WORD0; |
1006 |
break;
|
1007 |
default:
|
1008 |
s->mode = (val >> 1) & 7; |
1009 |
s->bcd = val & 1;
|
1010 |
s->rw_state = access - 1 + RW_STATE_LSB;
|
1011 |
break;
|
1012 |
} |
1013 |
} else {
|
1014 |
s = &pit_channels[addr]; |
1015 |
switch(s->rw_state) {
|
1016 |
case RW_STATE_LSB:
|
1017 |
pit_load_count(s, val); |
1018 |
break;
|
1019 |
case RW_STATE_MSB:
|
1020 |
pit_load_count(s, val << 8);
|
1021 |
break;
|
1022 |
case RW_STATE_WORD0:
|
1023 |
case RW_STATE_WORD1:
|
1024 |
if (s->rw_state & 1) { |
1025 |
pit_load_count(s, (s->latched_count & 0xff) | (val << 8)); |
1026 |
} else {
|
1027 |
s->latched_count = val; |
1028 |
} |
1029 |
s->rw_state ^= 1;
|
1030 |
break;
|
1031 |
} |
1032 |
} |
1033 |
} |
1034 |
|
1035 |
uint32_t pit_ioport_read(CPUX86State *env, uint32_t addr) |
1036 |
{ |
1037 |
int ret, count;
|
1038 |
PITChannelState *s; |
1039 |
|
1040 |
addr &= 3;
|
1041 |
s = &pit_channels[addr]; |
1042 |
switch(s->rw_state) {
|
1043 |
case RW_STATE_LSB:
|
1044 |
case RW_STATE_MSB:
|
1045 |
case RW_STATE_WORD0:
|
1046 |
case RW_STATE_WORD1:
|
1047 |
count = pit_get_count(s); |
1048 |
if (s->rw_state & 1) |
1049 |
ret = (count >> 8) & 0xff; |
1050 |
else
|
1051 |
ret = count & 0xff;
|
1052 |
if (s->rw_state & 2) |
1053 |
s->rw_state ^= 1;
|
1054 |
break;
|
1055 |
default:
|
1056 |
case RW_STATE_LATCHED_WORD0:
|
1057 |
case RW_STATE_LATCHED_WORD1:
|
1058 |
if (s->rw_state & 1) |
1059 |
ret = s->latched_count >> 8;
|
1060 |
else
|
1061 |
ret = s->latched_count & 0xff;
|
1062 |
s->rw_state ^= 1;
|
1063 |
break;
|
1064 |
} |
1065 |
return ret;
|
1066 |
} |
1067 |
|
1068 |
void speaker_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1069 |
{ |
1070 |
speaker_data_on = (val >> 1) & 1; |
1071 |
pit_channels[2].gate = val & 1; |
1072 |
} |
1073 |
|
1074 |
uint32_t speaker_ioport_read(CPUX86State *env, uint32_t addr) |
1075 |
{ |
1076 |
int out;
|
1077 |
out = pit_get_out(&pit_channels[2]);
|
1078 |
return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5); |
1079 |
} |
1080 |
|
1081 |
void pit_init(void) |
1082 |
{ |
1083 |
PITChannelState *s; |
1084 |
int i;
|
1085 |
|
1086 |
cpu_calibrate_ticks(); |
1087 |
|
1088 |
for(i = 0;i < 3; i++) { |
1089 |
s = &pit_channels[i]; |
1090 |
s->mode = 3;
|
1091 |
s->gate = (i != 2);
|
1092 |
pit_load_count(s, 0);
|
1093 |
} |
1094 |
|
1095 |
register_ioport_write(0x40, 4, pit_ioport_write, 1); |
1096 |
register_ioport_read(0x40, 3, pit_ioport_read, 1); |
1097 |
|
1098 |
register_ioport_read(0x61, 1, speaker_ioport_read, 1); |
1099 |
register_ioport_write(0x61, 1, speaker_ioport_write, 1); |
1100 |
} |
1101 |
|
1102 |
/***********************************************************/
|
1103 |
/* serial port emulation */
|
1104 |
|
1105 |
#define UART_IRQ 4 |
1106 |
|
1107 |
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
1108 |
|
1109 |
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
1110 |
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
1111 |
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
1112 |
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
1113 |
|
1114 |
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
1115 |
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
1116 |
|
1117 |
#define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
1118 |
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
1119 |
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
1120 |
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
1121 |
|
1122 |
#define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
1123 |
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
1124 |
#define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
1125 |
#define UART_LSR_FE 0x08 /* Frame error indicator */ |
1126 |
#define UART_LSR_PE 0x04 /* Parity error indicator */ |
1127 |
#define UART_LSR_OE 0x02 /* Overrun error indicator */ |
1128 |
#define UART_LSR_DR 0x01 /* Receiver data ready */ |
1129 |
|
1130 |
typedef struct SerialState { |
1131 |
uint8_t divider; |
1132 |
uint8_t rbr; /* receive register */
|
1133 |
uint8_t ier; |
1134 |
uint8_t iir; /* read only */
|
1135 |
uint8_t lcr; |
1136 |
uint8_t mcr; |
1137 |
uint8_t lsr; /* read only */
|
1138 |
uint8_t msr; |
1139 |
uint8_t scr; |
1140 |
} SerialState; |
1141 |
|
1142 |
SerialState serial_ports[1];
|
1143 |
|
1144 |
void serial_update_irq(void) |
1145 |
{ |
1146 |
SerialState *s = &serial_ports[0];
|
1147 |
|
1148 |
if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
|
1149 |
s->iir = UART_IIR_RDI; |
1150 |
} else if ((s->lsr & UART_LSR_THRE) && (s->ier & UART_IER_THRI)) { |
1151 |
s->iir = UART_IIR_THRI; |
1152 |
} else {
|
1153 |
s->iir = UART_IIR_NO_INT; |
1154 |
} |
1155 |
if (s->iir != UART_IIR_NO_INT) {
|
1156 |
pic_set_irq(UART_IRQ, 1);
|
1157 |
} else {
|
1158 |
pic_set_irq(UART_IRQ, 0);
|
1159 |
} |
1160 |
} |
1161 |
|
1162 |
void serial_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1163 |
{ |
1164 |
SerialState *s = &serial_ports[0];
|
1165 |
unsigned char ch; |
1166 |
int ret;
|
1167 |
|
1168 |
addr &= 7;
|
1169 |
switch(addr) {
|
1170 |
default:
|
1171 |
case 0: |
1172 |
if (s->lcr & UART_LCR_DLAB) {
|
1173 |
s->divider = (s->divider & 0xff00) | val;
|
1174 |
} else {
|
1175 |
s->lsr &= ~UART_LSR_THRE; |
1176 |
serial_update_irq(); |
1177 |
|
1178 |
ch = val; |
1179 |
do {
|
1180 |
ret = write(1, &ch, 1); |
1181 |
} while (ret != 1); |
1182 |
s->lsr |= UART_LSR_THRE; |
1183 |
s->lsr |= UART_LSR_TEMT; |
1184 |
serial_update_irq(); |
1185 |
} |
1186 |
break;
|
1187 |
case 1: |
1188 |
if (s->lcr & UART_LCR_DLAB) {
|
1189 |
s->divider = (s->divider & 0x00ff) | (val << 8); |
1190 |
} else {
|
1191 |
s->ier = val; |
1192 |
serial_update_irq(); |
1193 |
} |
1194 |
break;
|
1195 |
case 2: |
1196 |
break;
|
1197 |
case 3: |
1198 |
s->lcr = val; |
1199 |
break;
|
1200 |
case 4: |
1201 |
s->mcr = val; |
1202 |
break;
|
1203 |
case 5: |
1204 |
break;
|
1205 |
case 6: |
1206 |
s->msr = val; |
1207 |
break;
|
1208 |
case 7: |
1209 |
s->scr = val; |
1210 |
break;
|
1211 |
} |
1212 |
} |
1213 |
|
1214 |
uint32_t serial_ioport_read(CPUX86State *env, uint32_t addr) |
1215 |
{ |
1216 |
SerialState *s = &serial_ports[0];
|
1217 |
uint32_t ret; |
1218 |
|
1219 |
addr &= 7;
|
1220 |
switch(addr) {
|
1221 |
default:
|
1222 |
case 0: |
1223 |
if (s->lcr & UART_LCR_DLAB) {
|
1224 |
ret = s->divider & 0xff;
|
1225 |
} else {
|
1226 |
ret = s->rbr; |
1227 |
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
1228 |
serial_update_irq(); |
1229 |
} |
1230 |
break;
|
1231 |
case 1: |
1232 |
if (s->lcr & UART_LCR_DLAB) {
|
1233 |
ret = (s->divider >> 8) & 0xff; |
1234 |
} else {
|
1235 |
ret = s->ier; |
1236 |
} |
1237 |
break;
|
1238 |
case 2: |
1239 |
ret = s->iir; |
1240 |
break;
|
1241 |
case 3: |
1242 |
ret = s->lcr; |
1243 |
break;
|
1244 |
case 4: |
1245 |
ret = s->mcr; |
1246 |
break;
|
1247 |
case 5: |
1248 |
ret = s->lsr; |
1249 |
break;
|
1250 |
case 6: |
1251 |
ret = s->msr; |
1252 |
break;
|
1253 |
case 7: |
1254 |
ret = s->scr; |
1255 |
break;
|
1256 |
} |
1257 |
return ret;
|
1258 |
} |
1259 |
|
1260 |
#define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */ |
1261 |
static int term_got_escape; |
1262 |
|
1263 |
void term_print_help(void) |
1264 |
{ |
1265 |
printf("\n"
|
1266 |
"C-a h print this help\n"
|
1267 |
"C-a x exit emulatior\n"
|
1268 |
"C-a b send break (magic sysrq)\n"
|
1269 |
"C-a C-a send C-a\n"
|
1270 |
); |
1271 |
} |
1272 |
|
1273 |
/* called when a char is received */
|
1274 |
void serial_received_byte(SerialState *s, int ch) |
1275 |
{ |
1276 |
if (term_got_escape) {
|
1277 |
term_got_escape = 0;
|
1278 |
switch(ch) {
|
1279 |
case 'h': |
1280 |
term_print_help(); |
1281 |
break;
|
1282 |
case 'x': |
1283 |
exit(0);
|
1284 |
break;
|
1285 |
case 'b': |
1286 |
/* send break */
|
1287 |
s->rbr = 0;
|
1288 |
s->lsr |= UART_LSR_BI | UART_LSR_DR; |
1289 |
serial_update_irq(); |
1290 |
break;
|
1291 |
case TERM_ESCAPE:
|
1292 |
goto send_char;
|
1293 |
} |
1294 |
} else if (ch == TERM_ESCAPE) { |
1295 |
term_got_escape = 1;
|
1296 |
} else {
|
1297 |
send_char:
|
1298 |
s->rbr = ch; |
1299 |
s->lsr |= UART_LSR_DR; |
1300 |
serial_update_irq(); |
1301 |
} |
1302 |
} |
1303 |
|
1304 |
/* init terminal so that we can grab keys */
|
1305 |
static struct termios oldtty; |
1306 |
|
1307 |
static void term_exit(void) |
1308 |
{ |
1309 |
tcsetattr (0, TCSANOW, &oldtty);
|
1310 |
} |
1311 |
|
1312 |
static void term_init(void) |
1313 |
{ |
1314 |
struct termios tty;
|
1315 |
|
1316 |
tcgetattr (0, &tty);
|
1317 |
oldtty = tty; |
1318 |
|
1319 |
tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP |
1320 |
|INLCR|IGNCR|ICRNL|IXON); |
1321 |
tty.c_oflag |= OPOST; |
1322 |
tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN|ISIG); |
1323 |
tty.c_cflag &= ~(CSIZE|PARENB); |
1324 |
tty.c_cflag |= CS8; |
1325 |
tty.c_cc[VMIN] = 1;
|
1326 |
tty.c_cc[VTIME] = 0;
|
1327 |
|
1328 |
tcsetattr (0, TCSANOW, &tty);
|
1329 |
|
1330 |
atexit(term_exit); |
1331 |
|
1332 |
fcntl(0, F_SETFL, O_NONBLOCK);
|
1333 |
} |
1334 |
|
1335 |
void serial_init(void) |
1336 |
{ |
1337 |
SerialState *s = &serial_ports[0];
|
1338 |
|
1339 |
s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
1340 |
|
1341 |
register_ioport_write(0x3f8, 8, serial_ioport_write, 1); |
1342 |
register_ioport_read(0x3f8, 8, serial_ioport_read, 1); |
1343 |
|
1344 |
term_init(); |
1345 |
} |
1346 |
|
1347 |
/***********************************************************/
|
1348 |
/* ne2000 emulation */
|
1349 |
|
1350 |
//#define DEBUG_NE2000
|
1351 |
|
1352 |
#define NE2000_IOPORT 0x300 |
1353 |
#define NE2000_IRQ 9 |
1354 |
|
1355 |
#define MAX_ETH_FRAME_SIZE 1514 |
1356 |
|
1357 |
#define E8390_CMD 0x00 /* The command register (for all pages) */ |
1358 |
/* Page 0 register offsets. */
|
1359 |
#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ |
1360 |
#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ |
1361 |
#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ |
1362 |
#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ |
1363 |
#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ |
1364 |
#define EN0_TSR 0x04 /* Transmit status reg RD */ |
1365 |
#define EN0_TPSR 0x04 /* Transmit starting page WR */ |
1366 |
#define EN0_NCR 0x05 /* Number of collision reg RD */ |
1367 |
#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ |
1368 |
#define EN0_FIFO 0x06 /* FIFO RD */ |
1369 |
#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ |
1370 |
#define EN0_ISR 0x07 /* Interrupt status reg RD WR */ |
1371 |
#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ |
1372 |
#define EN0_RSARLO 0x08 /* Remote start address reg 0 */ |
1373 |
#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ |
1374 |
#define EN0_RSARHI 0x09 /* Remote start address reg 1 */ |
1375 |
#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ |
1376 |
#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ |
1377 |
#define EN0_RSR 0x0c /* rx status reg RD */ |
1378 |
#define EN0_RXCR 0x0c /* RX configuration reg WR */ |
1379 |
#define EN0_TXCR 0x0d /* TX configuration reg WR */ |
1380 |
#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ |
1381 |
#define EN0_DCFG 0x0e /* Data configuration reg WR */ |
1382 |
#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ |
1383 |
#define EN0_IMR 0x0f /* Interrupt mask reg WR */ |
1384 |
#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ |
1385 |
|
1386 |
#define EN1_PHYS 0x11 |
1387 |
#define EN1_CURPAG 0x17 |
1388 |
#define EN1_MULT 0x18 |
1389 |
|
1390 |
/* Register accessed at EN_CMD, the 8390 base addr. */
|
1391 |
#define E8390_STOP 0x01 /* Stop and reset the chip */ |
1392 |
#define E8390_START 0x02 /* Start the chip, clear reset */ |
1393 |
#define E8390_TRANS 0x04 /* Transmit a frame */ |
1394 |
#define E8390_RREAD 0x08 /* Remote read */ |
1395 |
#define E8390_RWRITE 0x10 /* Remote write */ |
1396 |
#define E8390_NODMA 0x20 /* Remote DMA */ |
1397 |
#define E8390_PAGE0 0x00 /* Select page chip registers */ |
1398 |
#define E8390_PAGE1 0x40 /* using the two high-order bits */ |
1399 |
#define E8390_PAGE2 0x80 /* Page 3 is invalid. */ |
1400 |
|
1401 |
/* Bits in EN0_ISR - Interrupt status register */
|
1402 |
#define ENISR_RX 0x01 /* Receiver, no error */ |
1403 |
#define ENISR_TX 0x02 /* Transmitter, no error */ |
1404 |
#define ENISR_RX_ERR 0x04 /* Receiver, with error */ |
1405 |
#define ENISR_TX_ERR 0x08 /* Transmitter, with error */ |
1406 |
#define ENISR_OVER 0x10 /* Receiver overwrote the ring */ |
1407 |
#define ENISR_COUNTERS 0x20 /* Counters need emptying */ |
1408 |
#define ENISR_RDC 0x40 /* remote dma complete */ |
1409 |
#define ENISR_RESET 0x80 /* Reset completed */ |
1410 |
#define ENISR_ALL 0x3f /* Interrupts we will enable */ |
1411 |
|
1412 |
/* Bits in received packet status byte and EN0_RSR*/
|
1413 |
#define ENRSR_RXOK 0x01 /* Received a good packet */ |
1414 |
#define ENRSR_CRC 0x02 /* CRC error */ |
1415 |
#define ENRSR_FAE 0x04 /* frame alignment error */ |
1416 |
#define ENRSR_FO 0x08 /* FIFO overrun */ |
1417 |
#define ENRSR_MPA 0x10 /* missed pkt */ |
1418 |
#define ENRSR_PHY 0x20 /* physical/multicast address */ |
1419 |
#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ |
1420 |
#define ENRSR_DEF 0x80 /* deferring */ |
1421 |
|
1422 |
/* Transmitted packet status, EN0_TSR. */
|
1423 |
#define ENTSR_PTX 0x01 /* Packet transmitted without error */ |
1424 |
#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ |
1425 |
#define ENTSR_COL 0x04 /* The transmit collided at least once. */ |
1426 |
#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ |
1427 |
#define ENTSR_CRS 0x10 /* The carrier sense was lost. */ |
1428 |
#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ |
1429 |
#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ |
1430 |
#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ |
1431 |
|
1432 |
#define NE2000_MEM_SIZE 32768 |
1433 |
|
1434 |
typedef struct NE2000State { |
1435 |
uint8_t cmd; |
1436 |
uint32_t start; |
1437 |
uint32_t stop; |
1438 |
uint8_t boundary; |
1439 |
uint8_t tsr; |
1440 |
uint8_t tpsr; |
1441 |
uint16_t tcnt; |
1442 |
uint16_t rcnt; |
1443 |
uint32_t rsar; |
1444 |
uint8_t isr; |
1445 |
uint8_t dcfg; |
1446 |
uint8_t imr; |
1447 |
uint8_t phys[6]; /* mac address */ |
1448 |
uint8_t curpag; |
1449 |
uint8_t mult[8]; /* multicast mask array */ |
1450 |
uint8_t mem[NE2000_MEM_SIZE]; |
1451 |
} NE2000State; |
1452 |
|
1453 |
NE2000State ne2000_state; |
1454 |
int net_fd = -1; |
1455 |
char network_script[1024]; |
1456 |
|
1457 |
void ne2000_reset(void) |
1458 |
{ |
1459 |
NE2000State *s = &ne2000_state; |
1460 |
int i;
|
1461 |
|
1462 |
s->isr = ENISR_RESET; |
1463 |
s->mem[0] = 0x52; |
1464 |
s->mem[1] = 0x54; |
1465 |
s->mem[2] = 0x00; |
1466 |
s->mem[3] = 0x12; |
1467 |
s->mem[4] = 0x34; |
1468 |
s->mem[5] = 0x56; |
1469 |
s->mem[14] = 0x57; |
1470 |
s->mem[15] = 0x57; |
1471 |
|
1472 |
/* duplicate prom data */
|
1473 |
for(i = 15;i >= 0; i--) { |
1474 |
s->mem[2 * i] = s->mem[i];
|
1475 |
s->mem[2 * i + 1] = s->mem[i]; |
1476 |
} |
1477 |
} |
1478 |
|
1479 |
void ne2000_update_irq(NE2000State *s)
|
1480 |
{ |
1481 |
int isr;
|
1482 |
isr = s->isr & s->imr; |
1483 |
if (isr)
|
1484 |
pic_set_irq(NE2000_IRQ, 1);
|
1485 |
else
|
1486 |
pic_set_irq(NE2000_IRQ, 0);
|
1487 |
} |
1488 |
|
1489 |
int net_init(void) |
1490 |
{ |
1491 |
struct ifreq ifr;
|
1492 |
int fd, ret, pid, status;
|
1493 |
|
1494 |
fd = open("/dev/net/tun", O_RDWR);
|
1495 |
if (fd < 0) { |
1496 |
fprintf(stderr, "warning: could not open /dev/net/tun: no virtual network emulation\n");
|
1497 |
return -1; |
1498 |
} |
1499 |
memset(&ifr, 0, sizeof(ifr)); |
1500 |
ifr.ifr_flags = IFF_TAP | IFF_NO_PI; |
1501 |
pstrcpy(ifr.ifr_name, IFNAMSIZ, "tun%d");
|
1502 |
ret = ioctl(fd, TUNSETIFF, (void *) &ifr);
|
1503 |
if (ret != 0) { |
1504 |
fprintf(stderr, "warning: could not configure /dev/net/tun: no virtual network emulation\n");
|
1505 |
close(fd); |
1506 |
return -1; |
1507 |
} |
1508 |
printf("Connected to host network interface: %s\n", ifr.ifr_name);
|
1509 |
fcntl(fd, F_SETFL, O_NONBLOCK); |
1510 |
net_fd = fd; |
1511 |
|
1512 |
/* try to launch network init script */
|
1513 |
pid = fork(); |
1514 |
if (pid >= 0) { |
1515 |
if (pid == 0) { |
1516 |
execl(network_script, network_script, ifr.ifr_name, NULL);
|
1517 |
exit(1);
|
1518 |
} |
1519 |
while (waitpid(pid, &status, 0) != pid); |
1520 |
if (!WIFEXITED(status) ||
|
1521 |
WEXITSTATUS(status) != 0) {
|
1522 |
fprintf(stderr, "%s: could not launch network script for '%s'\n",
|
1523 |
network_script, ifr.ifr_name); |
1524 |
} |
1525 |
} |
1526 |
return 0; |
1527 |
} |
1528 |
|
1529 |
void net_send_packet(NE2000State *s, const uint8_t *buf, int size) |
1530 |
{ |
1531 |
#ifdef DEBUG_NE2000
|
1532 |
printf("NE2000: sending packet size=%d\n", size);
|
1533 |
#endif
|
1534 |
write(net_fd, buf, size); |
1535 |
} |
1536 |
|
1537 |
/* return true if the NE2000 can receive more data */
|
1538 |
int ne2000_can_receive(NE2000State *s)
|
1539 |
{ |
1540 |
int avail, index, boundary;
|
1541 |
|
1542 |
if (s->cmd & E8390_STOP)
|
1543 |
return 0; |
1544 |
index = s->curpag << 8;
|
1545 |
boundary = s->boundary << 8;
|
1546 |
if (index < boundary)
|
1547 |
avail = boundary - index; |
1548 |
else
|
1549 |
avail = (s->stop - s->start) - (index - boundary); |
1550 |
if (avail < (MAX_ETH_FRAME_SIZE + 4)) |
1551 |
return 0; |
1552 |
return 1; |
1553 |
} |
1554 |
|
1555 |
void ne2000_receive(NE2000State *s, uint8_t *buf, int size) |
1556 |
{ |
1557 |
uint8_t *p; |
1558 |
int total_len, next, avail, len, index;
|
1559 |
|
1560 |
#if defined(DEBUG_NE2000)
|
1561 |
printf("NE2000: received len=%d\n", size);
|
1562 |
#endif
|
1563 |
|
1564 |
index = s->curpag << 8;
|
1565 |
/* 4 bytes for header */
|
1566 |
total_len = size + 4;
|
1567 |
/* address for next packet (4 bytes for CRC) */
|
1568 |
next = index + ((total_len + 4 + 255) & ~0xff); |
1569 |
if (next >= s->stop)
|
1570 |
next -= (s->stop - s->start); |
1571 |
/* prepare packet header */
|
1572 |
p = s->mem + index; |
1573 |
p[0] = ENRSR_RXOK; /* receive status */ |
1574 |
p[1] = next >> 8; |
1575 |
p[2] = total_len;
|
1576 |
p[3] = total_len >> 8; |
1577 |
index += 4;
|
1578 |
|
1579 |
/* write packet data */
|
1580 |
while (size > 0) { |
1581 |
avail = s->stop - index; |
1582 |
len = size; |
1583 |
if (len > avail)
|
1584 |
len = avail; |
1585 |
memcpy(s->mem + index, buf, len); |
1586 |
buf += len; |
1587 |
index += len; |
1588 |
if (index == s->stop)
|
1589 |
index = s->start; |
1590 |
size -= len; |
1591 |
} |
1592 |
s->curpag = next >> 8;
|
1593 |
|
1594 |
/* now we can signal we have receive something */
|
1595 |
s->isr |= ENISR_RX; |
1596 |
ne2000_update_irq(s); |
1597 |
} |
1598 |
|
1599 |
void ne2000_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1600 |
{ |
1601 |
NE2000State *s = &ne2000_state; |
1602 |
int offset, page;
|
1603 |
|
1604 |
addr &= 0xf;
|
1605 |
#ifdef DEBUG_NE2000
|
1606 |
printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
|
1607 |
#endif
|
1608 |
if (addr == E8390_CMD) {
|
1609 |
/* control register */
|
1610 |
s->cmd = val; |
1611 |
if (val & E8390_START) {
|
1612 |
/* test specific case: zero length transfert */
|
1613 |
if ((val & (E8390_RREAD | E8390_RWRITE)) &&
|
1614 |
s->rcnt == 0) {
|
1615 |
s->isr |= ENISR_RDC; |
1616 |
ne2000_update_irq(s); |
1617 |
} |
1618 |
if (val & E8390_TRANS) {
|
1619 |
net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt);
|
1620 |
/* signal end of transfert */
|
1621 |
s->tsr = ENTSR_PTX; |
1622 |
s->isr |= ENISR_TX; |
1623 |
ne2000_update_irq(s); |
1624 |
} |
1625 |
} |
1626 |
} else {
|
1627 |
page = s->cmd >> 6;
|
1628 |
offset = addr | (page << 4);
|
1629 |
switch(offset) {
|
1630 |
case EN0_STARTPG:
|
1631 |
s->start = val << 8;
|
1632 |
break;
|
1633 |
case EN0_STOPPG:
|
1634 |
s->stop = val << 8;
|
1635 |
break;
|
1636 |
case EN0_BOUNDARY:
|
1637 |
s->boundary = val; |
1638 |
break;
|
1639 |
case EN0_IMR:
|
1640 |
s->imr = val; |
1641 |
ne2000_update_irq(s); |
1642 |
break;
|
1643 |
case EN0_TPSR:
|
1644 |
s->tpsr = val; |
1645 |
break;
|
1646 |
case EN0_TCNTLO:
|
1647 |
s->tcnt = (s->tcnt & 0xff00) | val;
|
1648 |
break;
|
1649 |
case EN0_TCNTHI:
|
1650 |
s->tcnt = (s->tcnt & 0x00ff) | (val << 8); |
1651 |
break;
|
1652 |
case EN0_RSARLO:
|
1653 |
s->rsar = (s->rsar & 0xff00) | val;
|
1654 |
break;
|
1655 |
case EN0_RSARHI:
|
1656 |
s->rsar = (s->rsar & 0x00ff) | (val << 8); |
1657 |
break;
|
1658 |
case EN0_RCNTLO:
|
1659 |
s->rcnt = (s->rcnt & 0xff00) | val;
|
1660 |
break;
|
1661 |
case EN0_RCNTHI:
|
1662 |
s->rcnt = (s->rcnt & 0x00ff) | (val << 8); |
1663 |
break;
|
1664 |
case EN0_DCFG:
|
1665 |
s->dcfg = val; |
1666 |
break;
|
1667 |
case EN0_ISR:
|
1668 |
s->isr &= ~val; |
1669 |
ne2000_update_irq(s); |
1670 |
break;
|
1671 |
case EN1_PHYS ... EN1_PHYS + 5: |
1672 |
s->phys[offset - EN1_PHYS] = val; |
1673 |
break;
|
1674 |
case EN1_CURPAG:
|
1675 |
s->curpag = val; |
1676 |
break;
|
1677 |
case EN1_MULT ... EN1_MULT + 7: |
1678 |
s->mult[offset - EN1_MULT] = val; |
1679 |
break;
|
1680 |
} |
1681 |
} |
1682 |
} |
1683 |
|
1684 |
uint32_t ne2000_ioport_read(CPUX86State *env, uint32_t addr) |
1685 |
{ |
1686 |
NE2000State *s = &ne2000_state; |
1687 |
int offset, page, ret;
|
1688 |
|
1689 |
addr &= 0xf;
|
1690 |
if (addr == E8390_CMD) {
|
1691 |
ret = s->cmd; |
1692 |
} else {
|
1693 |
page = s->cmd >> 6;
|
1694 |
offset = addr | (page << 4);
|
1695 |
switch(offset) {
|
1696 |
case EN0_TSR:
|
1697 |
ret = s->tsr; |
1698 |
break;
|
1699 |
case EN0_BOUNDARY:
|
1700 |
ret = s->boundary; |
1701 |
break;
|
1702 |
case EN0_ISR:
|
1703 |
ret = s->isr; |
1704 |
break;
|
1705 |
case EN1_PHYS ... EN1_PHYS + 5: |
1706 |
ret = s->phys[offset - EN1_PHYS]; |
1707 |
break;
|
1708 |
case EN1_CURPAG:
|
1709 |
ret = s->curpag; |
1710 |
break;
|
1711 |
case EN1_MULT ... EN1_MULT + 7: |
1712 |
ret = s->mult[offset - EN1_MULT]; |
1713 |
break;
|
1714 |
default:
|
1715 |
ret = 0x00;
|
1716 |
break;
|
1717 |
} |
1718 |
} |
1719 |
#ifdef DEBUG_NE2000
|
1720 |
printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
|
1721 |
#endif
|
1722 |
return ret;
|
1723 |
} |
1724 |
|
1725 |
void ne2000_asic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1726 |
{ |
1727 |
NE2000State *s = &ne2000_state; |
1728 |
uint8_t *p; |
1729 |
|
1730 |
#ifdef DEBUG_NE2000
|
1731 |
printf("NE2000: asic write val=0x%04x\n", val);
|
1732 |
#endif
|
1733 |
p = s->mem + s->rsar; |
1734 |
if (s->dcfg & 0x01) { |
1735 |
/* 16 bit access */
|
1736 |
p[0] = val;
|
1737 |
p[1] = val >> 8; |
1738 |
s->rsar += 2;
|
1739 |
s->rcnt -= 2;
|
1740 |
} else {
|
1741 |
/* 8 bit access */
|
1742 |
p[0] = val;
|
1743 |
s->rsar++; |
1744 |
s->rcnt--; |
1745 |
} |
1746 |
/* wrap */
|
1747 |
if (s->rsar == s->stop)
|
1748 |
s->rsar = s->start; |
1749 |
if (s->rcnt == 0) { |
1750 |
/* signal end of transfert */
|
1751 |
s->isr |= ENISR_RDC; |
1752 |
ne2000_update_irq(s); |
1753 |
} |
1754 |
} |
1755 |
|
1756 |
uint32_t ne2000_asic_ioport_read(CPUX86State *env, uint32_t addr) |
1757 |
{ |
1758 |
NE2000State *s = &ne2000_state; |
1759 |
uint8_t *p; |
1760 |
int ret;
|
1761 |
|
1762 |
p = s->mem + s->rsar; |
1763 |
if (s->dcfg & 0x01) { |
1764 |
/* 16 bit access */
|
1765 |
ret = p[0] | (p[1] << 8); |
1766 |
s->rsar += 2;
|
1767 |
s->rcnt -= 2;
|
1768 |
} else {
|
1769 |
/* 8 bit access */
|
1770 |
ret = p[0];
|
1771 |
s->rsar++; |
1772 |
s->rcnt--; |
1773 |
} |
1774 |
/* wrap */
|
1775 |
if (s->rsar == s->stop)
|
1776 |
s->rsar = s->start; |
1777 |
if (s->rcnt == 0) { |
1778 |
/* signal end of transfert */
|
1779 |
s->isr |= ENISR_RDC; |
1780 |
ne2000_update_irq(s); |
1781 |
} |
1782 |
#ifdef DEBUG_NE2000
|
1783 |
printf("NE2000: asic read val=0x%04x\n", ret);
|
1784 |
#endif
|
1785 |
return ret;
|
1786 |
} |
1787 |
|
1788 |
void ne2000_reset_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1789 |
{ |
1790 |
/* nothing to do (end of reset pulse) */
|
1791 |
} |
1792 |
|
1793 |
uint32_t ne2000_reset_ioport_read(CPUX86State *env, uint32_t addr) |
1794 |
{ |
1795 |
ne2000_reset(); |
1796 |
return 0; |
1797 |
} |
1798 |
|
1799 |
void ne2000_init(void) |
1800 |
{ |
1801 |
register_ioport_write(NE2000_IOPORT, 16, ne2000_ioport_write, 1); |
1802 |
register_ioport_read(NE2000_IOPORT, 16, ne2000_ioport_read, 1); |
1803 |
|
1804 |
register_ioport_write(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write, 1); |
1805 |
register_ioport_read(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read, 1); |
1806 |
register_ioport_write(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write, 2); |
1807 |
register_ioport_read(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read, 2); |
1808 |
|
1809 |
register_ioport_write(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write, 1); |
1810 |
register_ioport_read(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read, 1); |
1811 |
ne2000_reset(); |
1812 |
} |
1813 |
|
1814 |
/***********************************************************/
|
1815 |
/* ide emulation */
|
1816 |
|
1817 |
//#define DEBUG_IDE
|
1818 |
|
1819 |
/* Bits of HD_STATUS */
|
1820 |
#define ERR_STAT 0x01 |
1821 |
#define INDEX_STAT 0x02 |
1822 |
#define ECC_STAT 0x04 /* Corrected error */ |
1823 |
#define DRQ_STAT 0x08 |
1824 |
#define SEEK_STAT 0x10 |
1825 |
#define SRV_STAT 0x10 |
1826 |
#define WRERR_STAT 0x20 |
1827 |
#define READY_STAT 0x40 |
1828 |
#define BUSY_STAT 0x80 |
1829 |
|
1830 |
/* Bits for HD_ERROR */
|
1831 |
#define MARK_ERR 0x01 /* Bad address mark */ |
1832 |
#define TRK0_ERR 0x02 /* couldn't find track 0 */ |
1833 |
#define ABRT_ERR 0x04 /* Command aborted */ |
1834 |
#define MCR_ERR 0x08 /* media change request */ |
1835 |
#define ID_ERR 0x10 /* ID field not found */ |
1836 |
#define MC_ERR 0x20 /* media changed */ |
1837 |
#define ECC_ERR 0x40 /* Uncorrectable ECC error */ |
1838 |
#define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */ |
1839 |
#define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */ |
1840 |
|
1841 |
/* Bits of HD_NSECTOR */
|
1842 |
#define CD 0x01 |
1843 |
#define IO 0x02 |
1844 |
#define REL 0x04 |
1845 |
#define TAG_MASK 0xf8 |
1846 |
|
1847 |
#define IDE_CMD_RESET 0x04 |
1848 |
#define IDE_CMD_DISABLE_IRQ 0x02 |
1849 |
|
1850 |
/* ATA/ATAPI Commands pre T13 Spec */
|
1851 |
#define WIN_NOP 0x00 |
1852 |
/*
|
1853 |
* 0x01->0x02 Reserved
|
1854 |
*/
|
1855 |
#define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */ |
1856 |
/*
|
1857 |
* 0x04->0x07 Reserved
|
1858 |
*/
|
1859 |
#define WIN_SRST 0x08 /* ATAPI soft reset command */ |
1860 |
#define WIN_DEVICE_RESET 0x08 |
1861 |
/*
|
1862 |
* 0x09->0x0F Reserved
|
1863 |
*/
|
1864 |
#define WIN_RECAL 0x10 |
1865 |
#define WIN_RESTORE WIN_RECAL
|
1866 |
/*
|
1867 |
* 0x10->0x1F Reserved
|
1868 |
*/
|
1869 |
#define WIN_READ 0x20 /* 28-Bit */ |
1870 |
#define WIN_READ_ONCE 0x21 /* 28-Bit without retries */ |
1871 |
#define WIN_READ_LONG 0x22 /* 28-Bit */ |
1872 |
#define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */ |
1873 |
#define WIN_READ_EXT 0x24 /* 48-Bit */ |
1874 |
#define WIN_READDMA_EXT 0x25 /* 48-Bit */ |
1875 |
#define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */ |
1876 |
#define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */ |
1877 |
/*
|
1878 |
* 0x28
|
1879 |
*/
|
1880 |
#define WIN_MULTREAD_EXT 0x29 /* 48-Bit */ |
1881 |
/*
|
1882 |
* 0x2A->0x2F Reserved
|
1883 |
*/
|
1884 |
#define WIN_WRITE 0x30 /* 28-Bit */ |
1885 |
#define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */ |
1886 |
#define WIN_WRITE_LONG 0x32 /* 28-Bit */ |
1887 |
#define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */ |
1888 |
#define WIN_WRITE_EXT 0x34 /* 48-Bit */ |
1889 |
#define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */ |
1890 |
#define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */ |
1891 |
#define WIN_SET_MAX_EXT 0x37 /* 48-Bit */ |
1892 |
#define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */ |
1893 |
#define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */ |
1894 |
/*
|
1895 |
* 0x3A->0x3B Reserved
|
1896 |
*/
|
1897 |
#define WIN_WRITE_VERIFY 0x3C /* 28-Bit */ |
1898 |
/*
|
1899 |
* 0x3D->0x3F Reserved
|
1900 |
*/
|
1901 |
#define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */ |
1902 |
#define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */ |
1903 |
#define WIN_VERIFY_EXT 0x42 /* 48-Bit */ |
1904 |
/*
|
1905 |
* 0x43->0x4F Reserved
|
1906 |
*/
|
1907 |
#define WIN_FORMAT 0x50 |
1908 |
/*
|
1909 |
* 0x51->0x5F Reserved
|
1910 |
*/
|
1911 |
#define WIN_INIT 0x60 |
1912 |
/*
|
1913 |
* 0x61->0x5F Reserved
|
1914 |
*/
|
1915 |
#define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */ |
1916 |
#define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */ |
1917 |
#define WIN_DIAGNOSE 0x90 |
1918 |
#define WIN_SPECIFY 0x91 /* set drive geometry translation */ |
1919 |
#define WIN_DOWNLOAD_MICROCODE 0x92 |
1920 |
#define WIN_STANDBYNOW2 0x94 |
1921 |
#define WIN_STANDBY2 0x96 |
1922 |
#define WIN_SETIDLE2 0x97 |
1923 |
#define WIN_CHECKPOWERMODE2 0x98 |
1924 |
#define WIN_SLEEPNOW2 0x99 |
1925 |
/*
|
1926 |
* 0x9A VENDOR
|
1927 |
*/
|
1928 |
#define WIN_PACKETCMD 0xA0 /* Send a packet command. */ |
1929 |
#define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */ |
1930 |
#define WIN_QUEUED_SERVICE 0xA2 |
1931 |
#define WIN_SMART 0xB0 /* self-monitoring and reporting */ |
1932 |
#define CFA_ERASE_SECTORS 0xC0 |
1933 |
#define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/ |
1934 |
#define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */ |
1935 |
#define WIN_SETMULT 0xC6 /* enable/disable multiple mode */ |
1936 |
#define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */ |
1937 |
#define WIN_READDMA 0xC8 /* read sectors using DMA transfers */ |
1938 |
#define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */ |
1939 |
#define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */ |
1940 |
#define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */ |
1941 |
#define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */ |
1942 |
#define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */ |
1943 |
#define WIN_GETMEDIASTATUS 0xDA |
1944 |
#define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */ |
1945 |
#define WIN_POSTBOOT 0xDC |
1946 |
#define WIN_PREBOOT 0xDD |
1947 |
#define WIN_DOORLOCK 0xDE /* lock door on removable drives */ |
1948 |
#define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */ |
1949 |
#define WIN_STANDBYNOW1 0xE0 |
1950 |
#define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */ |
1951 |
#define WIN_STANDBY 0xE2 /* Set device in Standby Mode */ |
1952 |
#define WIN_SETIDLE1 0xE3 |
1953 |
#define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */ |
1954 |
#define WIN_CHECKPOWERMODE1 0xE5 |
1955 |
#define WIN_SLEEPNOW1 0xE6 |
1956 |
#define WIN_FLUSH_CACHE 0xE7 |
1957 |
#define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */ |
1958 |
#define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */ |
1959 |
/* SET_FEATURES 0x22 or 0xDD */
|
1960 |
#define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */ |
1961 |
#define WIN_IDENTIFY 0xEC /* ask drive to identify itself */ |
1962 |
#define WIN_MEDIAEJECT 0xED |
1963 |
#define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */ |
1964 |
#define WIN_SETFEATURES 0xEF /* set special drive features */ |
1965 |
#define EXABYTE_ENABLE_NEST 0xF0 |
1966 |
#define WIN_SECURITY_SET_PASS 0xF1 |
1967 |
#define WIN_SECURITY_UNLOCK 0xF2 |
1968 |
#define WIN_SECURITY_ERASE_PREPARE 0xF3 |
1969 |
#define WIN_SECURITY_ERASE_UNIT 0xF4 |
1970 |
#define WIN_SECURITY_FREEZE_LOCK 0xF5 |
1971 |
#define WIN_SECURITY_DISABLE 0xF6 |
1972 |
#define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */ |
1973 |
#define WIN_SET_MAX 0xF9 |
1974 |
#define DISABLE_SEAGATE 0xFB |
1975 |
|
1976 |
/* set to 1 set disable mult support */
|
1977 |
#define MAX_MULT_SECTORS 8 |
1978 |
|
1979 |
#define MAX_DISKS 2 |
1980 |
|
1981 |
struct IDEState;
|
1982 |
|
1983 |
typedef void EndTransferFunc(struct IDEState *); |
1984 |
|
1985 |
typedef struct IDEState { |
1986 |
/* ide config */
|
1987 |
int cylinders, heads, sectors;
|
1988 |
int64_t nb_sectors; |
1989 |
int mult_sectors;
|
1990 |
int irq;
|
1991 |
/* ide regs */
|
1992 |
uint8_t feature; |
1993 |
uint8_t error; |
1994 |
uint16_t nsector; /* 0 is 256 to ease computations */
|
1995 |
uint8_t sector; |
1996 |
uint8_t lcyl; |
1997 |
uint8_t hcyl; |
1998 |
uint8_t select; |
1999 |
uint8_t status; |
2000 |
/* 0x3f6 command, only meaningful for drive 0 */
|
2001 |
uint8_t cmd; |
2002 |
/* depends on bit 4 in select, only meaningful for drive 0 */
|
2003 |
struct IDEState *cur_drive;
|
2004 |
BlockDriverState *bs; |
2005 |
int req_nb_sectors; /* number of sectors per interrupt */ |
2006 |
EndTransferFunc *end_transfer_func; |
2007 |
uint8_t *data_ptr; |
2008 |
uint8_t *data_end; |
2009 |
uint8_t io_buffer[MAX_MULT_SECTORS*512 + 4]; |
2010 |
} IDEState; |
2011 |
|
2012 |
BlockDriverState *bs_table[MAX_DISKS]; |
2013 |
IDEState ide_state[MAX_DISKS]; |
2014 |
|
2015 |
static void padstr(char *str, const char *src, int len) |
2016 |
{ |
2017 |
int i, v;
|
2018 |
for(i = 0; i < len; i++) { |
2019 |
if (*src)
|
2020 |
v = *src++; |
2021 |
else
|
2022 |
v = ' ';
|
2023 |
*(char *)((long)str ^ 1) = v; |
2024 |
str++; |
2025 |
} |
2026 |
} |
2027 |
|
2028 |
static void ide_identify(IDEState *s) |
2029 |
{ |
2030 |
uint16_t *p; |
2031 |
unsigned int oldsize; |
2032 |
|
2033 |
memset(s->io_buffer, 0, 512); |
2034 |
p = (uint16_t *)s->io_buffer; |
2035 |
stw(p + 0, 0x0040); |
2036 |
stw(p + 1, s->cylinders);
|
2037 |
stw(p + 3, s->heads);
|
2038 |
stw(p + 4, 512 * s->sectors); /* sectors */ |
2039 |
stw(p + 5, 512); /* sector size */ |
2040 |
stw(p + 6, s->sectors);
|
2041 |
stw(p + 20, 3); /* buffer type */ |
2042 |
stw(p + 21, 512); /* cache size in sectors */ |
2043 |
stw(p + 22, 4); /* ecc bytes */ |
2044 |
padstr((uint8_t *)(p + 27), "QEMU HARDDISK", 40); |
2045 |
#if MAX_MULT_SECTORS > 1 |
2046 |
stw(p + 47, MAX_MULT_SECTORS);
|
2047 |
#endif
|
2048 |
stw(p + 48, 1); /* dword I/O */ |
2049 |
stw(p + 49, 1 << 9); /* LBA supported, no DMA */ |
2050 |
stw(p + 51, 0x200); /* PIO transfer cycle */ |
2051 |
stw(p + 52, 0x200); /* DMA transfer cycle */ |
2052 |
stw(p + 54, s->cylinders);
|
2053 |
stw(p + 55, s->heads);
|
2054 |
stw(p + 56, s->sectors);
|
2055 |
oldsize = s->cylinders * s->heads * s->sectors; |
2056 |
stw(p + 57, oldsize);
|
2057 |
stw(p + 58, oldsize >> 16); |
2058 |
if (s->mult_sectors)
|
2059 |
stw(p + 59, 0x100 | s->mult_sectors); |
2060 |
stw(p + 60, s->nb_sectors);
|
2061 |
stw(p + 61, s->nb_sectors >> 16); |
2062 |
stw(p + 80, (1 << 1) | (1 << 2)); |
2063 |
stw(p + 82, (1 << 14)); |
2064 |
stw(p + 83, (1 << 14)); |
2065 |
stw(p + 84, (1 << 14)); |
2066 |
stw(p + 85, (1 << 14)); |
2067 |
stw(p + 86, 0); |
2068 |
stw(p + 87, (1 << 14)); |
2069 |
} |
2070 |
|
2071 |
static inline void ide_abort_command(IDEState *s) |
2072 |
{ |
2073 |
s->status = READY_STAT | ERR_STAT; |
2074 |
s->error = ABRT_ERR; |
2075 |
} |
2076 |
|
2077 |
static inline void ide_set_irq(IDEState *s) |
2078 |
{ |
2079 |
if (!(ide_state[0].cmd & IDE_CMD_DISABLE_IRQ)) { |
2080 |
pic_set_irq(s->irq, 1);
|
2081 |
} |
2082 |
} |
2083 |
|
2084 |
/* prepare data transfer and tell what to do after */
|
2085 |
static void ide_transfer_start(IDEState *s, int size, |
2086 |
EndTransferFunc *end_transfer_func) |
2087 |
{ |
2088 |
s->end_transfer_func = end_transfer_func; |
2089 |
s->data_ptr = s->io_buffer; |
2090 |
s->data_end = s->io_buffer + size; |
2091 |
s->status |= DRQ_STAT; |
2092 |
} |
2093 |
|
2094 |
static void ide_transfer_stop(IDEState *s) |
2095 |
{ |
2096 |
s->end_transfer_func = ide_transfer_stop; |
2097 |
s->data_ptr = s->io_buffer; |
2098 |
s->data_end = s->io_buffer; |
2099 |
s->status &= ~DRQ_STAT; |
2100 |
} |
2101 |
|
2102 |
static int64_t ide_get_sector(IDEState *s)
|
2103 |
{ |
2104 |
int64_t sector_num; |
2105 |
if (s->select & 0x40) { |
2106 |
/* lba */
|
2107 |
sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) | |
2108 |
(s->lcyl << 8) | s->sector;
|
2109 |
} else {
|
2110 |
sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
|
2111 |
(s->select & 0x0f) * s->sectors +
|
2112 |
(s->sector - 1);
|
2113 |
} |
2114 |
return sector_num;
|
2115 |
} |
2116 |
|
2117 |
static void ide_set_sector(IDEState *s, int64_t sector_num) |
2118 |
{ |
2119 |
unsigned int cyl, r; |
2120 |
if (s->select & 0x40) { |
2121 |
s->select = (s->select & 0xf0) | (sector_num >> 24); |
2122 |
s->hcyl = (sector_num >> 16);
|
2123 |
s->lcyl = (sector_num >> 8);
|
2124 |
s->sector = (sector_num); |
2125 |
} else {
|
2126 |
cyl = sector_num / (s->heads * s->sectors); |
2127 |
r = sector_num % (s->heads * s->sectors); |
2128 |
s->hcyl = cyl >> 8;
|
2129 |
s->lcyl = cyl; |
2130 |
s->select = (s->select & 0xf0) | (r / s->sectors);
|
2131 |
s->sector = (r % s->sectors) + 1;
|
2132 |
} |
2133 |
} |
2134 |
|
2135 |
static void ide_sector_read(IDEState *s) |
2136 |
{ |
2137 |
int64_t sector_num; |
2138 |
int ret, n;
|
2139 |
|
2140 |
s->status = READY_STAT | SEEK_STAT; |
2141 |
sector_num = ide_get_sector(s); |
2142 |
n = s->nsector; |
2143 |
if (n == 0) { |
2144 |
/* no more sector to read from disk */
|
2145 |
ide_transfer_stop(s); |
2146 |
} else {
|
2147 |
#if defined(DEBUG_IDE)
|
2148 |
printf("read sector=%Ld\n", sector_num);
|
2149 |
#endif
|
2150 |
if (n > s->req_nb_sectors)
|
2151 |
n = s->req_nb_sectors; |
2152 |
ret = bdrv_read(s->bs, sector_num, s->io_buffer, n); |
2153 |
ide_transfer_start(s, 512 * n, ide_sector_read);
|
2154 |
ide_set_irq(s); |
2155 |
ide_set_sector(s, sector_num + n); |
2156 |
s->nsector -= n; |
2157 |
} |
2158 |
} |
2159 |
|
2160 |
static void ide_sector_write(IDEState *s) |
2161 |
{ |
2162 |
int64_t sector_num; |
2163 |
int ret, n, n1;
|
2164 |
|
2165 |
s->status = READY_STAT | SEEK_STAT; |
2166 |
sector_num = ide_get_sector(s); |
2167 |
#if defined(DEBUG_IDE)
|
2168 |
printf("write sector=%Ld\n", sector_num);
|
2169 |
#endif
|
2170 |
n = s->nsector; |
2171 |
if (n > s->req_nb_sectors)
|
2172 |
n = s->req_nb_sectors; |
2173 |
ret = bdrv_write(s->bs, sector_num, s->io_buffer, n); |
2174 |
s->nsector -= n; |
2175 |
if (s->nsector == 0) { |
2176 |
/* no more sector to write */
|
2177 |
ide_transfer_stop(s); |
2178 |
} else {
|
2179 |
n1 = s->nsector; |
2180 |
if (n1 > s->req_nb_sectors)
|
2181 |
n1 = s->req_nb_sectors; |
2182 |
ide_transfer_start(s, 512 * n1, ide_sector_write);
|
2183 |
} |
2184 |
ide_set_sector(s, sector_num + n); |
2185 |
ide_set_irq(s); |
2186 |
} |
2187 |
|
2188 |
void ide_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
2189 |
{ |
2190 |
IDEState *s = ide_state[0].cur_drive;
|
2191 |
int unit, n;
|
2192 |
|
2193 |
addr &= 7;
|
2194 |
#ifdef DEBUG_IDE
|
2195 |
printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
|
2196 |
#endif
|
2197 |
switch(addr) {
|
2198 |
case 0: |
2199 |
break;
|
2200 |
case 1: |
2201 |
s->feature = val; |
2202 |
break;
|
2203 |
case 2: |
2204 |
if (val == 0) |
2205 |
val = 256;
|
2206 |
s->nsector = val; |
2207 |
break;
|
2208 |
case 3: |
2209 |
s->sector = val; |
2210 |
break;
|
2211 |
case 4: |
2212 |
s->lcyl = val; |
2213 |
break;
|
2214 |
case 5: |
2215 |
s->hcyl = val; |
2216 |
break;
|
2217 |
case 6: |
2218 |
/* select drive */
|
2219 |
unit = (val >> 4) & 1; |
2220 |
s = &ide_state[unit]; |
2221 |
ide_state[0].cur_drive = s;
|
2222 |
s->select = val; |
2223 |
break;
|
2224 |
default:
|
2225 |
case 7: |
2226 |
/* command */
|
2227 |
#if defined(DEBUG_IDE)
|
2228 |
printf("ide: CMD=%02x\n", val);
|
2229 |
#endif
|
2230 |
switch(val) {
|
2231 |
case WIN_PIDENTIFY:
|
2232 |
case WIN_IDENTIFY:
|
2233 |
if (s->bs) {
|
2234 |
ide_identify(s); |
2235 |
s->status = READY_STAT; |
2236 |
ide_transfer_start(s, 512, ide_transfer_stop);
|
2237 |
} else {
|
2238 |
ide_abort_command(s); |
2239 |
} |
2240 |
ide_set_irq(s); |
2241 |
break;
|
2242 |
case WIN_SPECIFY:
|
2243 |
case WIN_RECAL:
|
2244 |
s->status = READY_STAT; |
2245 |
ide_set_irq(s); |
2246 |
break;
|
2247 |
case WIN_SETMULT:
|
2248 |
if (s->nsector > MAX_MULT_SECTORS ||
|
2249 |
s->nsector == 0 ||
|
2250 |
(s->nsector & (s->nsector - 1)) != 0) { |
2251 |
ide_abort_command(s); |
2252 |
} else {
|
2253 |
s->mult_sectors = s->nsector; |
2254 |
s->status = READY_STAT; |
2255 |
} |
2256 |
ide_set_irq(s); |
2257 |
break;
|
2258 |
case WIN_READ:
|
2259 |
case WIN_READ_ONCE:
|
2260 |
s->req_nb_sectors = 1;
|
2261 |
ide_sector_read(s); |
2262 |
break;
|
2263 |
case WIN_WRITE:
|
2264 |
case WIN_WRITE_ONCE:
|
2265 |
s->status = SEEK_STAT; |
2266 |
s->req_nb_sectors = 1;
|
2267 |
ide_transfer_start(s, 512, ide_sector_write);
|
2268 |
break;
|
2269 |
case WIN_MULTREAD:
|
2270 |
if (!s->mult_sectors)
|
2271 |
goto abort_cmd;
|
2272 |
s->req_nb_sectors = s->mult_sectors; |
2273 |
ide_sector_read(s); |
2274 |
break;
|
2275 |
case WIN_MULTWRITE:
|
2276 |
if (!s->mult_sectors)
|
2277 |
goto abort_cmd;
|
2278 |
s->status = SEEK_STAT; |
2279 |
s->req_nb_sectors = s->mult_sectors; |
2280 |
n = s->nsector; |
2281 |
if (n > s->req_nb_sectors)
|
2282 |
n = s->req_nb_sectors; |
2283 |
ide_transfer_start(s, 512 * n, ide_sector_write);
|
2284 |
break;
|
2285 |
default:
|
2286 |
abort_cmd:
|
2287 |
ide_abort_command(s); |
2288 |
ide_set_irq(s); |
2289 |
break;
|
2290 |
} |
2291 |
} |
2292 |
} |
2293 |
|
2294 |
uint32_t ide_ioport_read(CPUX86State *env, uint32_t addr) |
2295 |
{ |
2296 |
IDEState *s = ide_state[0].cur_drive;
|
2297 |
int ret;
|
2298 |
|
2299 |
addr &= 7;
|
2300 |
switch(addr) {
|
2301 |
case 0: |
2302 |
ret = 0xff;
|
2303 |
break;
|
2304 |
case 1: |
2305 |
ret = s->error; |
2306 |
break;
|
2307 |
case 2: |
2308 |
ret = s->nsector & 0xff;
|
2309 |
break;
|
2310 |
case 3: |
2311 |
ret = s->sector; |
2312 |
break;
|
2313 |
case 4: |
2314 |
ret = s->lcyl; |
2315 |
break;
|
2316 |
case 5: |
2317 |
ret = s->hcyl; |
2318 |
break;
|
2319 |
case 6: |
2320 |
ret = s->select; |
2321 |
break;
|
2322 |
default:
|
2323 |
case 7: |
2324 |
ret = s->status; |
2325 |
pic_set_irq(s->irq, 0);
|
2326 |
break;
|
2327 |
} |
2328 |
#ifdef DEBUG_IDE
|
2329 |
printf("ide: read addr=0x%x val=%02x\n", addr, ret);
|
2330 |
#endif
|
2331 |
return ret;
|
2332 |
} |
2333 |
|
2334 |
uint32_t ide_status_read(CPUX86State *env, uint32_t addr) |
2335 |
{ |
2336 |
IDEState *s = ide_state[0].cur_drive;
|
2337 |
int ret;
|
2338 |
ret = s->status; |
2339 |
#ifdef DEBUG_IDE
|
2340 |
printf("ide: read addr=0x%x val=%02x\n", addr, ret);
|
2341 |
#endif
|
2342 |
return ret;
|
2343 |
} |
2344 |
|
2345 |
void ide_cmd_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
2346 |
{ |
2347 |
IDEState *s = &ide_state[0];
|
2348 |
/* common for both drives */
|
2349 |
s->cmd = val; |
2350 |
} |
2351 |
|
2352 |
void ide_data_writew(CPUX86State *env, uint32_t addr, uint32_t val)
|
2353 |
{ |
2354 |
IDEState *s = ide_state[0].cur_drive;
|
2355 |
uint8_t *p; |
2356 |
|
2357 |
p = s->data_ptr; |
2358 |
*(uint16_t *)p = tswap16(val); |
2359 |
p += 2;
|
2360 |
s->data_ptr = p; |
2361 |
if (p >= s->data_end)
|
2362 |
s->end_transfer_func(s); |
2363 |
} |
2364 |
|
2365 |
uint32_t ide_data_readw(CPUX86State *env, uint32_t addr) |
2366 |
{ |
2367 |
IDEState *s = ide_state[0].cur_drive;
|
2368 |
uint8_t *p; |
2369 |
int ret;
|
2370 |
|
2371 |
p = s->data_ptr; |
2372 |
ret = tswap16(*(uint16_t *)p); |
2373 |
p += 2;
|
2374 |
s->data_ptr = p; |
2375 |
if (p >= s->data_end)
|
2376 |
s->end_transfer_func(s); |
2377 |
return ret;
|
2378 |
} |
2379 |
|
2380 |
void ide_data_writel(CPUX86State *env, uint32_t addr, uint32_t val)
|
2381 |
{ |
2382 |
IDEState *s = ide_state[0].cur_drive;
|
2383 |
uint8_t *p; |
2384 |
|
2385 |
p = s->data_ptr; |
2386 |
*(uint32_t *)p = tswap32(val); |
2387 |
p += 4;
|
2388 |
s->data_ptr = p; |
2389 |
if (p >= s->data_end)
|
2390 |
s->end_transfer_func(s); |
2391 |
} |
2392 |
|
2393 |
uint32_t ide_data_readl(CPUX86State *env, uint32_t addr) |
2394 |
{ |
2395 |
IDEState *s = ide_state[0].cur_drive;
|
2396 |
uint8_t *p; |
2397 |
int ret;
|
2398 |
|
2399 |
p = s->data_ptr; |
2400 |
ret = tswap32(*(uint32_t *)p); |
2401 |
p += 4;
|
2402 |
s->data_ptr = p; |
2403 |
if (p >= s->data_end)
|
2404 |
s->end_transfer_func(s); |
2405 |
return ret;
|
2406 |
} |
2407 |
|
2408 |
void ide_reset(IDEState *s)
|
2409 |
{ |
2410 |
s->mult_sectors = MAX_MULT_SECTORS; |
2411 |
s->status = READY_STAT; |
2412 |
s->cur_drive = s; |
2413 |
s->select = 0xa0;
|
2414 |
} |
2415 |
|
2416 |
void ide_init(void) |
2417 |
{ |
2418 |
IDEState *s; |
2419 |
int i, cylinders;
|
2420 |
int64_t nb_sectors; |
2421 |
|
2422 |
for(i = 0; i < MAX_DISKS; i++) { |
2423 |
s = &ide_state[i]; |
2424 |
s->bs = bs_table[i]; |
2425 |
if (s->bs) {
|
2426 |
bdrv_get_geometry(s->bs, &nb_sectors); |
2427 |
cylinders = nb_sectors / (16 * 63); |
2428 |
if (cylinders > 16383) |
2429 |
cylinders = 16383;
|
2430 |
else if (cylinders < 2) |
2431 |
cylinders = 2;
|
2432 |
s->cylinders = cylinders; |
2433 |
s->heads = 16;
|
2434 |
s->sectors = 63;
|
2435 |
s->nb_sectors = nb_sectors; |
2436 |
} |
2437 |
s->irq = 14;
|
2438 |
ide_reset(s); |
2439 |
} |
2440 |
register_ioport_write(0x1f0, 8, ide_ioport_write, 1); |
2441 |
register_ioport_read(0x1f0, 8, ide_ioport_read, 1); |
2442 |
register_ioport_read(0x3f6, 1, ide_status_read, 1); |
2443 |
register_ioport_write(0x3f6, 1, ide_cmd_write, 1); |
2444 |
|
2445 |
/* data ports */
|
2446 |
register_ioport_write(0x1f0, 2, ide_data_writew, 2); |
2447 |
register_ioport_read(0x1f0, 2, ide_data_readw, 2); |
2448 |
register_ioport_write(0x1f0, 4, ide_data_writel, 4); |
2449 |
register_ioport_read(0x1f0, 4, ide_data_readl, 4); |
2450 |
} |
2451 |
|
2452 |
/***********************************************************/
|
2453 |
/* cpu signal handler */
|
2454 |
static void host_segv_handler(int host_signum, siginfo_t *info, |
2455 |
void *puc)
|
2456 |
{ |
2457 |
if (cpu_signal_handler(host_signum, info, puc))
|
2458 |
return;
|
2459 |
term_exit(); |
2460 |
abort(); |
2461 |
} |
2462 |
|
2463 |
static int timer_irq_pending; |
2464 |
static int timer_irq_count; |
2465 |
|
2466 |
static void host_alarm_handler(int host_signum, siginfo_t *info, |
2467 |
void *puc)
|
2468 |
{ |
2469 |
/* NOTE: since usually the OS asks a 100 Hz clock, there can be
|
2470 |
some drift between cpu_get_ticks() and the interrupt time. So
|
2471 |
we queue some interrupts to avoid missing some */
|
2472 |
timer_irq_count += pit_get_out_edges(&pit_channels[0]);
|
2473 |
if (timer_irq_count) {
|
2474 |
if (timer_irq_count > 2) |
2475 |
timer_irq_count = 2;
|
2476 |
timer_irq_count--; |
2477 |
/* just exit from the cpu to have a chance to handle timers */
|
2478 |
cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT); |
2479 |
timer_irq_pending = 1;
|
2480 |
} |
2481 |
} |
2482 |
|
2483 |
/* main execution loop */
|
2484 |
|
2485 |
CPUState *cpu_gdbstub_get_env(void *opaque)
|
2486 |
{ |
2487 |
return global_env;
|
2488 |
} |
2489 |
|
2490 |
void main_loop(void *opaque) |
2491 |
{ |
2492 |
struct pollfd ufds[2], *pf, *serial_ufd, *net_ufd, *gdb_ufd; |
2493 |
int ret, n, timeout;
|
2494 |
uint8_t ch; |
2495 |
CPUState *env = global_env; |
2496 |
|
2497 |
for(;;) {
|
2498 |
|
2499 |
ret = cpu_x86_exec(env); |
2500 |
|
2501 |
/* if hlt instruction, we wait until the next IRQ */
|
2502 |
if (ret == EXCP_HLT)
|
2503 |
timeout = 10;
|
2504 |
else
|
2505 |
timeout = 0;
|
2506 |
/* poll any events */
|
2507 |
serial_ufd = NULL;
|
2508 |
pf = ufds; |
2509 |
if (!(serial_ports[0].lsr & UART_LSR_DR)) { |
2510 |
serial_ufd = pf; |
2511 |
pf->fd = 0;
|
2512 |
pf->events = POLLIN; |
2513 |
pf++; |
2514 |
} |
2515 |
net_ufd = NULL;
|
2516 |
if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) { |
2517 |
net_ufd = pf; |
2518 |
pf->fd = net_fd; |
2519 |
pf->events = POLLIN; |
2520 |
pf++; |
2521 |
} |
2522 |
gdb_ufd = NULL;
|
2523 |
if (gdbstub_fd > 0) { |
2524 |
gdb_ufd = pf; |
2525 |
pf->fd = gdbstub_fd; |
2526 |
pf->events = POLLIN; |
2527 |
pf++; |
2528 |
} |
2529 |
|
2530 |
ret = poll(ufds, pf - ufds, timeout); |
2531 |
if (ret > 0) { |
2532 |
if (serial_ufd && (serial_ufd->revents & POLLIN)) {
|
2533 |
n = read(0, &ch, 1); |
2534 |
if (n == 1) { |
2535 |
serial_received_byte(&serial_ports[0], ch);
|
2536 |
} |
2537 |
} |
2538 |
if (net_ufd && (net_ufd->revents & POLLIN)) {
|
2539 |
uint8_t buf[MAX_ETH_FRAME_SIZE]; |
2540 |
|
2541 |
n = read(net_fd, buf, MAX_ETH_FRAME_SIZE); |
2542 |
if (n > 0) { |
2543 |
if (n < 60) { |
2544 |
memset(buf + n, 0, 60 - n); |
2545 |
n = 60;
|
2546 |
} |
2547 |
ne2000_receive(&ne2000_state, buf, n); |
2548 |
} |
2549 |
} |
2550 |
if (gdb_ufd && (gdb_ufd->revents & POLLIN)) {
|
2551 |
uint8_t buf[1];
|
2552 |
/* stop emulation if requested by gdb */
|
2553 |
n = read(gdbstub_fd, buf, 1);
|
2554 |
if (n == 1) |
2555 |
break;
|
2556 |
} |
2557 |
} |
2558 |
|
2559 |
/* timer IRQ */
|
2560 |
if (timer_irq_pending) {
|
2561 |
pic_set_irq(0, 1); |
2562 |
pic_set_irq(0, 0); |
2563 |
timer_irq_pending = 0;
|
2564 |
} |
2565 |
} |
2566 |
} |
2567 |
|
2568 |
void help(void) |
2569 |
{ |
2570 |
printf("Virtual Linux version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n" |
2571 |
"usage: vl [options] bzImage [kernel parameters...]\n"
|
2572 |
"\n"
|
2573 |
"'bzImage' is a Linux kernel image (PAGE_OFFSET must be defined\n"
|
2574 |
"to 0x90000000 in asm/page.h and arch/i386/vmlinux.lds)\n"
|
2575 |
"\n"
|
2576 |
"General options:\n"
|
2577 |
"-initrd file use 'file' as initial ram disk\n"
|
2578 |
"-hda file use 'file' as hard disk 0 image\n"
|
2579 |
"-hdb file use 'file' as hard disk 1 image\n"
|
2580 |
"-m megs set virtual RAM size to megs MB\n"
|
2581 |
"-n script set network init script [default=%s]\n"
|
2582 |
"\n"
|
2583 |
"Debug options:\n"
|
2584 |
"-s wait gdb connection to port %d\n"
|
2585 |
"-p port change gdb connection port\n"
|
2586 |
"-d output log in /tmp/vl.log\n"
|
2587 |
"\n"
|
2588 |
"During emulation, use C-a h to get terminal commands:\n",
|
2589 |
DEFAULT_NETWORK_SCRIPT, DEFAULT_GDBSTUB_PORT); |
2590 |
term_print_help(); |
2591 |
exit(1);
|
2592 |
} |
2593 |
|
2594 |
struct option long_options[] = {
|
2595 |
{ "initrd", 1, NULL, 0, }, |
2596 |
{ "hda", 1, NULL, 0, }, |
2597 |
{ "hdb", 1, NULL, 0, }, |
2598 |
{ NULL, 0, NULL, 0 }, |
2599 |
}; |
2600 |
|
2601 |
int main(int argc, char **argv) |
2602 |
{ |
2603 |
int c, ret, initrd_size, i, use_gdbstub, gdbstub_port, long_index;
|
2604 |
struct linux_params *params;
|
2605 |
struct sigaction act;
|
2606 |
struct itimerval itv;
|
2607 |
CPUX86State *env; |
2608 |
const char *tmpdir, *initrd_filename; |
2609 |
const char *hd_filename[MAX_DISKS]; |
2610 |
|
2611 |
/* we never want that malloc() uses mmap() */
|
2612 |
mallopt(M_MMAP_THRESHOLD, 4096 * 1024); |
2613 |
initrd_filename = NULL;
|
2614 |
for(i = 0; i < MAX_DISKS; i++) |
2615 |
hd_filename[i] = NULL;
|
2616 |
phys_ram_size = 32 * 1024 * 1024; |
2617 |
pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT);
|
2618 |
use_gdbstub = 0;
|
2619 |
gdbstub_port = DEFAULT_GDBSTUB_PORT; |
2620 |
for(;;) {
|
2621 |
c = getopt_long_only(argc, argv, "hm:dn:sp:", long_options, &long_index);
|
2622 |
if (c == -1) |
2623 |
break;
|
2624 |
switch(c) {
|
2625 |
case 0: |
2626 |
switch(long_index) {
|
2627 |
case 0: |
2628 |
initrd_filename = optarg; |
2629 |
break;
|
2630 |
case 1: |
2631 |
hd_filename[0] = optarg;
|
2632 |
break;
|
2633 |
case 2: |
2634 |
hd_filename[1] = optarg;
|
2635 |
break;
|
2636 |
} |
2637 |
break;
|
2638 |
case 'h': |
2639 |
help(); |
2640 |
break;
|
2641 |
case 'm': |
2642 |
phys_ram_size = atoi(optarg) * 1024 * 1024; |
2643 |
if (phys_ram_size <= 0) |
2644 |
help(); |
2645 |
if (phys_ram_size > PHYS_RAM_MAX_SIZE) {
|
2646 |
fprintf(stderr, "vl: at most %d MB RAM can be simulated\n",
|
2647 |
PHYS_RAM_MAX_SIZE / (1024 * 1024)); |
2648 |
exit(1);
|
2649 |
} |
2650 |
break;
|
2651 |
case 'd': |
2652 |
loglevel = 1;
|
2653 |
break;
|
2654 |
case 'n': |
2655 |
pstrcpy(network_script, sizeof(network_script), optarg);
|
2656 |
break;
|
2657 |
case 's': |
2658 |
use_gdbstub = 1;
|
2659 |
break;
|
2660 |
case 'p': |
2661 |
gdbstub_port = atoi(optarg); |
2662 |
break;
|
2663 |
} |
2664 |
} |
2665 |
if (optind >= argc)
|
2666 |
help(); |
2667 |
|
2668 |
/* init debug */
|
2669 |
setvbuf(stdout, NULL, _IOLBF, 0); |
2670 |
if (loglevel) {
|
2671 |
logfile = fopen(DEBUG_LOGFILE, "w");
|
2672 |
if (!logfile) {
|
2673 |
perror(DEBUG_LOGFILE); |
2674 |
_exit(1);
|
2675 |
} |
2676 |
setvbuf(logfile, NULL, _IOLBF, 0); |
2677 |
} |
2678 |
|
2679 |
/* open the virtual block devices */
|
2680 |
for(i = 0; i < MAX_DISKS; i++) { |
2681 |
if (hd_filename[i]) {
|
2682 |
bs_table[i] = bdrv_open(hd_filename[i]); |
2683 |
if (!bs_table[i]) {
|
2684 |
fprintf(stderr, "vl: could not open hard disk image '%s\n",
|
2685 |
hd_filename[i]); |
2686 |
exit(1);
|
2687 |
} |
2688 |
} |
2689 |
} |
2690 |
|
2691 |
/* init network tun interface */
|
2692 |
net_init(); |
2693 |
|
2694 |
/* init the memory */
|
2695 |
tmpdir = getenv("VLTMPDIR");
|
2696 |
if (!tmpdir)
|
2697 |
tmpdir = "/tmp";
|
2698 |
snprintf(phys_ram_file, sizeof(phys_ram_file), "%s/vlXXXXXX", tmpdir); |
2699 |
if (mkstemp(phys_ram_file) < 0) { |
2700 |
fprintf(stderr, "Could not create temporary memory file '%s'\n",
|
2701 |
phys_ram_file); |
2702 |
exit(1);
|
2703 |
} |
2704 |
phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600);
|
2705 |
if (phys_ram_fd < 0) { |
2706 |
fprintf(stderr, "Could not open temporary memory file '%s'\n",
|
2707 |
phys_ram_file); |
2708 |
exit(1);
|
2709 |
} |
2710 |
ftruncate(phys_ram_fd, phys_ram_size); |
2711 |
unlink(phys_ram_file); |
2712 |
phys_ram_base = mmap((void *)PHYS_RAM_BASE, phys_ram_size,
|
2713 |
PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED, |
2714 |
phys_ram_fd, 0);
|
2715 |
if (phys_ram_base == MAP_FAILED) {
|
2716 |
fprintf(stderr, "Could not map physical memory\n");
|
2717 |
exit(1);
|
2718 |
} |
2719 |
|
2720 |
/* now we can load the kernel */
|
2721 |
ret = load_kernel(argv[optind], phys_ram_base + KERNEL_LOAD_ADDR); |
2722 |
if (ret < 0) { |
2723 |
fprintf(stderr, "vl: could not load kernel '%s'\n", argv[optind]);
|
2724 |
exit(1);
|
2725 |
} |
2726 |
|
2727 |
/* load initrd */
|
2728 |
initrd_size = 0;
|
2729 |
if (initrd_filename) {
|
2730 |
initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); |
2731 |
if (initrd_size < 0) { |
2732 |
fprintf(stderr, "vl: could not load initial ram disk '%s'\n",
|
2733 |
initrd_filename); |
2734 |
exit(1);
|
2735 |
} |
2736 |
} |
2737 |
|
2738 |
/* init kernel params */
|
2739 |
params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR);
|
2740 |
memset(params, 0, sizeof(struct linux_params)); |
2741 |
params->mount_root_rdonly = 0;
|
2742 |
params->cl_magic = 0xA33F;
|
2743 |
params->cl_offset = params->commandline - (uint8_t *)params; |
2744 |
params->alt_mem_k = (phys_ram_size / 1024) - 1024; |
2745 |
for(i = optind + 1; i < argc; i++) { |
2746 |
if (i != optind + 1) |
2747 |
pstrcat(params->commandline, sizeof(params->commandline), " "); |
2748 |
pstrcat(params->commandline, sizeof(params->commandline), argv[i]);
|
2749 |
} |
2750 |
params->loader_type = 0x01;
|
2751 |
if (initrd_size > 0) { |
2752 |
params->initrd_start = INITRD_LOAD_ADDR; |
2753 |
params->initrd_size = initrd_size; |
2754 |
} |
2755 |
params->orig_video_lines = 25;
|
2756 |
params->orig_video_cols = 80;
|
2757 |
|
2758 |
/* init basic PC hardware */
|
2759 |
init_ioports(); |
2760 |
register_ioport_write(0x80, 1, ioport80_write, 1); |
2761 |
|
2762 |
register_ioport_write(0x3d4, 2, vga_ioport_write, 1); |
2763 |
|
2764 |
cmos_init(); |
2765 |
pic_init(); |
2766 |
pit_init(); |
2767 |
serial_init(); |
2768 |
ne2000_init(); |
2769 |
ide_init(); |
2770 |
|
2771 |
/* setup cpu signal handlers for MMU / self modifying code handling */
|
2772 |
sigfillset(&act.sa_mask); |
2773 |
act.sa_flags = SA_SIGINFO; |
2774 |
act.sa_sigaction = host_segv_handler; |
2775 |
sigaction(SIGSEGV, &act, NULL);
|
2776 |
sigaction(SIGBUS, &act, NULL);
|
2777 |
|
2778 |
act.sa_sigaction = host_alarm_handler; |
2779 |
sigaction(SIGALRM, &act, NULL);
|
2780 |
|
2781 |
/* init CPU state */
|
2782 |
env = cpu_init(); |
2783 |
global_env = env; |
2784 |
cpu_single_env = env; |
2785 |
|
2786 |
/* setup basic memory access */
|
2787 |
env->cr[0] = 0x00000033; |
2788 |
cpu_x86_init_mmu(env); |
2789 |
|
2790 |
memset(params->idt_table, 0, sizeof(params->idt_table)); |
2791 |
|
2792 |
params->gdt_table[2] = 0x00cf9a000000ffffLL; /* KERNEL_CS */ |
2793 |
params->gdt_table[3] = 0x00cf92000000ffffLL; /* KERNEL_DS */ |
2794 |
|
2795 |
env->idt.base = (void *)params->idt_table;
|
2796 |
env->idt.limit = sizeof(params->idt_table) - 1; |
2797 |
env->gdt.base = (void *)params->gdt_table;
|
2798 |
env->gdt.limit = sizeof(params->gdt_table) - 1; |
2799 |
|
2800 |
cpu_x86_load_seg(env, R_CS, KERNEL_CS); |
2801 |
cpu_x86_load_seg(env, R_DS, KERNEL_DS); |
2802 |
cpu_x86_load_seg(env, R_ES, KERNEL_DS); |
2803 |
cpu_x86_load_seg(env, R_SS, KERNEL_DS); |
2804 |
cpu_x86_load_seg(env, R_FS, KERNEL_DS); |
2805 |
cpu_x86_load_seg(env, R_GS, KERNEL_DS); |
2806 |
|
2807 |
env->eip = KERNEL_LOAD_ADDR; |
2808 |
env->regs[R_ESI] = KERNEL_PARAMS_ADDR; |
2809 |
env->eflags = 0x2;
|
2810 |
|
2811 |
itv.it_interval.tv_sec = 0;
|
2812 |
itv.it_interval.tv_usec = 1000;
|
2813 |
itv.it_value.tv_sec = 0;
|
2814 |
itv.it_value.tv_usec = 10 * 1000; |
2815 |
setitimer(ITIMER_REAL, &itv, NULL);
|
2816 |
/* we probe the tick duration of the kernel to inform the user if
|
2817 |
the emulated kernel requested a too high timer frequency */
|
2818 |
getitimer(ITIMER_REAL, &itv); |
2819 |
pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) / |
2820 |
1000000;
|
2821 |
|
2822 |
if (use_gdbstub) {
|
2823 |
cpu_gdbstub(NULL, main_loop, gdbstub_port);
|
2824 |
} else {
|
2825 |
main_loop(NULL);
|
2826 |
} |
2827 |
return 0; |
2828 |
} |