root / hw / pxa2xx_timer.c @ 797e9542
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/*
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* Intel XScale PXA255/270 OS Timers.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Copyright (c) 2006 Thorsten Zitterell
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*
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* This code is licenced under the GPL.
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*/
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#include "hw.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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#include "pxa.h" |
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#include "sysbus.h" |
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|
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#define OSMR0 0x00 |
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#define OSMR1 0x04 |
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#define OSMR2 0x08 |
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#define OSMR3 0x0c |
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#define OSMR4 0x80 |
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#define OSMR5 0x84 |
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#define OSMR6 0x88 |
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#define OSMR7 0x8c |
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#define OSMR8 0x90 |
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#define OSMR9 0x94 |
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#define OSMR10 0x98 |
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#define OSMR11 0x9c |
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#define OSCR 0x10 /* OS Timer Count */ |
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#define OSCR4 0x40 |
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#define OSCR5 0x44 |
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#define OSCR6 0x48 |
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#define OSCR7 0x4c |
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#define OSCR8 0x50 |
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#define OSCR9 0x54 |
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#define OSCR10 0x58 |
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#define OSCR11 0x5c |
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#define OSSR 0x14 /* Timer status register */ |
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#define OWER 0x18 |
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#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */ |
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#define OMCR4 0xc0 /* OS Match Control registers */ |
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#define OMCR5 0xc4 |
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#define OMCR6 0xc8 |
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#define OMCR7 0xcc |
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#define OMCR8 0xd0 |
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#define OMCR9 0xd4 |
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#define OMCR10 0xd8 |
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#define OMCR11 0xdc |
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#define OSNR 0x20 |
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|
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#define PXA25X_FREQ 3686400 /* 3.6864 MHz */ |
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#define PXA27X_FREQ 3250000 /* 3.25 MHz */ |
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static int pxa2xx_timer4_freq[8] = { |
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[0] = 0, |
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[1] = 32768, |
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[2] = 1000, |
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[3] = 1, |
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[4] = 1000000, |
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/* [5] is the "Externally supplied clock". Assign if necessary. */
|
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[5 ... 7] = 0, |
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}; |
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typedef struct PXA2xxTimerInfo PXA2xxTimerInfo; |
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typedef struct { |
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uint32_t value; |
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int level;
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QEMUTimer *qtimer; |
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int num;
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PXA2xxTimerInfo *info; |
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} PXA2xxTimer0; |
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|
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typedef struct { |
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PXA2xxTimer0 tm; |
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int32_t oldclock; |
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int32_t clock; |
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uint64_t lastload; |
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uint32_t freq; |
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uint32_t control; |
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} PXA2xxTimer4; |
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|
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struct PXA2xxTimerInfo {
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SysBusDevice busdev; |
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uint32_t flags; |
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|
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int32_t clock; |
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int32_t oldclock; |
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uint64_t lastload; |
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uint32_t freq; |
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PXA2xxTimer0 timer[4];
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qemu_irq irqs[5];
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uint32_t events; |
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uint32_t irq_enabled; |
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uint32_t reset3; |
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uint32_t snapshot; |
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|
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PXA2xxTimer4 tm4[8];
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qemu_irq irq4; |
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}; |
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|
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#define PXA2XX_TIMER_HAVE_TM4 0 |
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|
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static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s) |
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{ |
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return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4); |
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} |
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|
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static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu) |
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{ |
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
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int i;
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uint32_t now_vm; |
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uint64_t new_qemu; |
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|
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now_vm = s->clock + |
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muldiv64(now_qemu - s->lastload, s->freq, get_ticks_per_sec()); |
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|
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for (i = 0; i < 4; i ++) { |
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new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm), |
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get_ticks_per_sec(), s->freq); |
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qemu_mod_timer(s->timer[i].qtimer, new_qemu); |
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} |
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} |
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|
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static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n) |
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{ |
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
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uint32_t now_vm; |
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uint64_t new_qemu; |
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static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 }; |
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int counter;
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|
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if (s->tm4[n].control & (1 << 7)) |
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counter = n; |
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else
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counter = counters[n]; |
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|
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if (!s->tm4[counter].freq) {
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qemu_del_timer(s->tm4[n].tm.qtimer); |
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return;
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} |
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|
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now_vm = s->tm4[counter].clock + muldiv64(now_qemu - |
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s->tm4[counter].lastload, |
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s->tm4[counter].freq, get_ticks_per_sec()); |
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|
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new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm), |
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get_ticks_per_sec(), s->tm4[counter].freq); |
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qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu); |
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} |
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|
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static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset) |
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{ |
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
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int tm = 0; |
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|
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switch (offset) {
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case OSMR3: tm ++;
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case OSMR2: tm ++;
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case OSMR1: tm ++;
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case OSMR0:
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return s->timer[tm].value;
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case OSMR11: tm ++;
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case OSMR10: tm ++;
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case OSMR9: tm ++;
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case OSMR8: tm ++;
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case OSMR7: tm ++;
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case OSMR6: tm ++;
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case OSMR5: tm ++;
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case OSMR4:
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if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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return s->tm4[tm].tm.value;
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case OSCR:
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return s->clock + muldiv64(qemu_get_clock(vm_clock) -
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s->lastload, s->freq, get_ticks_per_sec()); |
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case OSCR11: tm ++;
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case OSCR10: tm ++;
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case OSCR9: tm ++;
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case OSCR8: tm ++;
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case OSCR7: tm ++;
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case OSCR6: tm ++;
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case OSCR5: tm ++;
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case OSCR4:
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if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) { |
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if (s->tm4[tm - 1].freq) |
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s->snapshot = s->tm4[tm - 1].clock + muldiv64(
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qemu_get_clock(vm_clock) - |
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s->tm4[tm - 1].lastload,
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s->tm4[tm - 1].freq, get_ticks_per_sec());
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else
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s->snapshot = s->tm4[tm - 1].clock;
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} |
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if (!s->tm4[tm].freq)
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return s->tm4[tm].clock;
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return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) -
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s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec()); |
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case OIER:
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return s->irq_enabled;
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case OSSR: /* Status register */ |
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return s->events;
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case OWER:
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return s->reset3;
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case OMCR11: tm ++;
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case OMCR10: tm ++;
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case OMCR9: tm ++;
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case OMCR8: tm ++;
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case OMCR7: tm ++;
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case OMCR6: tm ++;
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case OMCR5: tm ++;
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case OMCR4:
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if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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return s->tm4[tm].control;
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case OSNR:
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return s->snapshot;
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default:
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badreg:
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hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset); |
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} |
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return 0; |
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} |
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static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{ |
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int i, tm = 0; |
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
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switch (offset) {
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case OSMR3: tm ++;
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case OSMR2: tm ++;
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case OSMR1: tm ++;
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case OSMR0:
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s->timer[tm].value = value; |
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pxa2xx_timer_update(s, qemu_get_clock(vm_clock)); |
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break;
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case OSMR11: tm ++;
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case OSMR10: tm ++;
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case OSMR9: tm ++;
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case OSMR8: tm ++;
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case OSMR7: tm ++;
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case OSMR6: tm ++;
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case OSMR5: tm ++;
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case OSMR4:
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if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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s->tm4[tm].tm.value = value; |
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pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); |
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break;
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case OSCR:
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s->oldclock = s->clock; |
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s->lastload = qemu_get_clock(vm_clock); |
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s->clock = value; |
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pxa2xx_timer_update(s, s->lastload); |
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break;
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case OSCR11: tm ++;
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case OSCR10: tm ++;
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case OSCR9: tm ++;
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case OSCR8: tm ++;
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case OSCR7: tm ++;
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case OSCR6: tm ++;
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case OSCR5: tm ++;
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case OSCR4:
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if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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s->tm4[tm].oldclock = s->tm4[tm].clock; |
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s->tm4[tm].lastload = qemu_get_clock(vm_clock); |
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s->tm4[tm].clock = value; |
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pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm); |
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break;
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case OIER:
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s->irq_enabled = value & 0xfff;
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break;
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case OSSR: /* Status register */ |
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s->events &= ~value; |
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for (i = 0; i < 4; i ++, value >>= 1) { |
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if (s->timer[i].level && (value & 1)) { |
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s->timer[i].level = 0;
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qemu_irq_lower(s->irqs[i]); |
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} |
287 |
} |
288 |
if (pxa2xx_timer_has_tm4(s)) {
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for (i = 0; i < 8; i ++, value >>= 1) |
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if (s->tm4[i].tm.level && (value & 1)) |
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s->tm4[i].tm.level = 0;
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if (!(s->events & 0xff0)) |
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qemu_irq_lower(s->irq4); |
294 |
} |
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break;
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case OWER: /* XXX: Reset on OSMR3 match? */ |
297 |
s->reset3 = value; |
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break;
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case OMCR7: tm ++;
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case OMCR6: tm ++;
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case OMCR5: tm ++;
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case OMCR4:
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if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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s->tm4[tm].control = value & 0x0ff;
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/* XXX Stop if running (shouldn't happen) */
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if ((value & (1 << 7)) || tm == 0) |
308 |
s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
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else {
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s->tm4[tm].freq = 0;
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pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); |
312 |
} |
313 |
break;
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case OMCR11: tm ++;
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case OMCR10: tm ++;
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case OMCR9: tm ++;
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case OMCR8: tm += 4; |
318 |
if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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s->tm4[tm].control = value & 0x3ff;
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/* XXX Stop if running (shouldn't happen) */
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if ((value & (1 << 7)) || !(tm & 1)) |
323 |
s->tm4[tm].freq = |
324 |
pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)]; |
325 |
else {
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s->tm4[tm].freq = 0;
|
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pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); |
328 |
} |
329 |
break;
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330 |
default:
|
331 |
badreg:
|
332 |
hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset); |
333 |
} |
334 |
} |
335 |
|
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static CPUReadMemoryFunc * const pxa2xx_timer_readfn[] = { |
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pxa2xx_timer_read, |
338 |
pxa2xx_timer_read, |
339 |
pxa2xx_timer_read, |
340 |
}; |
341 |
|
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static CPUWriteMemoryFunc * const pxa2xx_timer_writefn[] = { |
343 |
pxa2xx_timer_write, |
344 |
pxa2xx_timer_write, |
345 |
pxa2xx_timer_write, |
346 |
}; |
347 |
|
348 |
static void pxa2xx_timer_tick(void *opaque) |
349 |
{ |
350 |
PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque; |
351 |
PXA2xxTimerInfo *i = t->info; |
352 |
|
353 |
if (i->irq_enabled & (1 << t->num)) { |
354 |
t->level = 1;
|
355 |
i->events |= 1 << t->num;
|
356 |
qemu_irq_raise(t->num < 4 ? i->irqs[t->num] : i->irq4);
|
357 |
} |
358 |
|
359 |
if (t->num == 3) |
360 |
if (i->reset3 & 1) { |
361 |
i->reset3 = 0;
|
362 |
qemu_system_reset_request(); |
363 |
} |
364 |
} |
365 |
|
366 |
static void pxa2xx_timer_tick4(void *opaque) |
367 |
{ |
368 |
PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque; |
369 |
PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info; |
370 |
|
371 |
pxa2xx_timer_tick(&t->tm); |
372 |
if (t->control & (1 << 3)) |
373 |
t->clock = 0;
|
374 |
if (t->control & (1 << 6)) |
375 |
pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->tm.num - 4);
|
376 |
} |
377 |
|
378 |
static int pxa25x_timer_post_load(void *opaque, int version_id) |
379 |
{ |
380 |
PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
381 |
int64_t now; |
382 |
int i;
|
383 |
|
384 |
now = qemu_get_clock(vm_clock); |
385 |
pxa2xx_timer_update(s, now); |
386 |
|
387 |
if (pxa2xx_timer_has_tm4(s))
|
388 |
for (i = 0; i < 8; i ++) |
389 |
pxa2xx_timer_update4(s, now, i); |
390 |
|
391 |
return 0; |
392 |
} |
393 |
|
394 |
static int pxa2xx_timer_init(SysBusDevice *dev) |
395 |
{ |
396 |
int i;
|
397 |
int iomemtype;
|
398 |
PXA2xxTimerInfo *s; |
399 |
|
400 |
s = FROM_SYSBUS(PXA2xxTimerInfo, dev); |
401 |
s->irq_enabled = 0;
|
402 |
s->oldclock = 0;
|
403 |
s->clock = 0;
|
404 |
s->lastload = qemu_get_clock(vm_clock); |
405 |
s->reset3 = 0;
|
406 |
|
407 |
for (i = 0; i < 4; i ++) { |
408 |
s->timer[i].value = 0;
|
409 |
sysbus_init_irq(dev, &s->irqs[i]); |
410 |
s->timer[i].info = s; |
411 |
s->timer[i].num = i; |
412 |
s->timer[i].level = 0;
|
413 |
s->timer[i].qtimer = qemu_new_timer(vm_clock, |
414 |
pxa2xx_timer_tick, &s->timer[i]); |
415 |
} |
416 |
if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) { |
417 |
sysbus_init_irq(dev, &s->irq4); |
418 |
|
419 |
for (i = 0; i < 8; i ++) { |
420 |
s->tm4[i].tm.value = 0;
|
421 |
s->tm4[i].tm.info = s; |
422 |
s->tm4[i].tm.num = i + 4;
|
423 |
s->tm4[i].tm.level = 0;
|
424 |
s->tm4[i].freq = 0;
|
425 |
s->tm4[i].control = 0x0;
|
426 |
s->tm4[i].tm.qtimer = qemu_new_timer(vm_clock, |
427 |
pxa2xx_timer_tick4, &s->tm4[i]); |
428 |
} |
429 |
} |
430 |
|
431 |
iomemtype = cpu_register_io_memory(pxa2xx_timer_readfn, |
432 |
pxa2xx_timer_writefn, s, DEVICE_NATIVE_ENDIAN); |
433 |
sysbus_init_mmio(dev, 0x00001000, iomemtype);
|
434 |
|
435 |
return 0; |
436 |
} |
437 |
|
438 |
static const VMStateDescription vmstate_pxa2xx_timer0_regs = { |
439 |
.name = "pxa2xx_timer0",
|
440 |
.version_id = 1,
|
441 |
.minimum_version_id = 1,
|
442 |
.minimum_version_id_old = 1,
|
443 |
.fields = (VMStateField[]) { |
444 |
VMSTATE_UINT32(value, PXA2xxTimer0), |
445 |
VMSTATE_INT32(level, PXA2xxTimer0), |
446 |
VMSTATE_END_OF_LIST(), |
447 |
}, |
448 |
}; |
449 |
|
450 |
static const VMStateDescription vmstate_pxa2xx_timer4_regs = { |
451 |
.name = "pxa2xx_timer4",
|
452 |
.version_id = 1,
|
453 |
.minimum_version_id = 1,
|
454 |
.minimum_version_id_old = 1,
|
455 |
.fields = (VMStateField[]) { |
456 |
VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
|
457 |
vmstate_pxa2xx_timer0_regs, PXA2xxTimer0), |
458 |
VMSTATE_INT32(oldclock, PXA2xxTimer4), |
459 |
VMSTATE_INT32(clock, PXA2xxTimer4), |
460 |
VMSTATE_UINT64(lastload, PXA2xxTimer4), |
461 |
VMSTATE_UINT32(freq, PXA2xxTimer4), |
462 |
VMSTATE_UINT32(control, PXA2xxTimer4), |
463 |
VMSTATE_END_OF_LIST(), |
464 |
}, |
465 |
}; |
466 |
|
467 |
static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id) |
468 |
{ |
469 |
return pxa2xx_timer_has_tm4(opaque);
|
470 |
} |
471 |
|
472 |
static const VMStateDescription vmstate_pxa2xx_timer_regs = { |
473 |
.name = "pxa2xx_timer",
|
474 |
.version_id = 1,
|
475 |
.minimum_version_id = 1,
|
476 |
.minimum_version_id_old = 1,
|
477 |
.post_load = pxa25x_timer_post_load, |
478 |
.fields = (VMStateField[]) { |
479 |
VMSTATE_INT32(clock, PXA2xxTimerInfo), |
480 |
VMSTATE_INT32(oldclock, PXA2xxTimerInfo), |
481 |
VMSTATE_UINT64(lastload, PXA2xxTimerInfo), |
482 |
VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1, |
483 |
vmstate_pxa2xx_timer0_regs, PXA2xxTimer0), |
484 |
VMSTATE_UINT32(events, PXA2xxTimerInfo), |
485 |
VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo), |
486 |
VMSTATE_UINT32(reset3, PXA2xxTimerInfo), |
487 |
VMSTATE_UINT32(snapshot, PXA2xxTimerInfo), |
488 |
VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
|
489 |
pxa2xx_timer_has_tm4_test, 0,
|
490 |
vmstate_pxa2xx_timer4_regs, PXA2xxTimer4), |
491 |
VMSTATE_END_OF_LIST(), |
492 |
} |
493 |
}; |
494 |
|
495 |
static SysBusDeviceInfo pxa25x_timer_dev_info = {
|
496 |
.init = pxa2xx_timer_init, |
497 |
.qdev.name = "pxa25x-timer",
|
498 |
.qdev.desc = "PXA25x timer",
|
499 |
.qdev.size = sizeof(PXA2xxTimerInfo),
|
500 |
.qdev.vmsd = &vmstate_pxa2xx_timer_regs, |
501 |
.qdev.props = (Property[]) { |
502 |
DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
|
503 |
DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
|
504 |
PXA2XX_TIMER_HAVE_TM4, false),
|
505 |
DEFINE_PROP_END_OF_LIST(), |
506 |
}, |
507 |
}; |
508 |
|
509 |
static SysBusDeviceInfo pxa27x_timer_dev_info = {
|
510 |
.init = pxa2xx_timer_init, |
511 |
.qdev.name = "pxa27x-timer",
|
512 |
.qdev.desc = "PXA27x timer",
|
513 |
.qdev.size = sizeof(PXA2xxTimerInfo),
|
514 |
.qdev.vmsd = &vmstate_pxa2xx_timer_regs, |
515 |
.qdev.props = (Property[]) { |
516 |
DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
|
517 |
DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
|
518 |
PXA2XX_TIMER_HAVE_TM4, true),
|
519 |
DEFINE_PROP_END_OF_LIST(), |
520 |
}, |
521 |
}; |
522 |
|
523 |
static void pxa2xx_timer_register(void) |
524 |
{ |
525 |
sysbus_register_withprop(&pxa25x_timer_dev_info); |
526 |
sysbus_register_withprop(&pxa27x_timer_dev_info); |
527 |
}; |
528 |
device_init(pxa2xx_timer_register); |