Revision 798b0c25 hw/vga.c
| b/hw/vga.c | ||
|---|---|---|
| 22 | 22 |
* THE SOFTWARE. |
| 23 | 23 |
*/ |
| 24 | 24 |
#include "vl.h" |
| 25 |
#include "vga_int.h" |
|
| 25 | 26 |
|
| 26 | 27 |
//#define DEBUG_VGA |
| 27 | 28 |
//#define DEBUG_VGA_MEM |
| ... | ... | |
| 33 | 34 |
/* S3 VGA is deprecated - another graphic card will be emulated */ |
| 34 | 35 |
//#define CONFIG_S3VGA |
| 35 | 36 |
|
| 36 |
#define MSR_COLOR_EMULATION 0x01 |
|
| 37 |
#define MSR_PAGE_SELECT 0x20 |
|
| 38 |
|
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| 39 |
#define ST01_V_RETRACE 0x08 |
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#define ST01_DISP_ENABLE 0x01 |
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/* bochs VBE support */ |
|
| 43 |
#define CONFIG_BOCHS_VBE |
|
| 44 |
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|
| 45 |
#define VBE_DISPI_MAX_XRES 1024 |
|
| 46 |
#define VBE_DISPI_MAX_YRES 768 |
|
| 47 |
|
|
| 48 |
#define VBE_DISPI_INDEX_ID 0x0 |
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| 49 |
#define VBE_DISPI_INDEX_XRES 0x1 |
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| 50 |
#define VBE_DISPI_INDEX_YRES 0x2 |
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| 51 |
#define VBE_DISPI_INDEX_BPP 0x3 |
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| 52 |
#define VBE_DISPI_INDEX_ENABLE 0x4 |
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#define VBE_DISPI_INDEX_BANK 0x5 |
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#define VBE_DISPI_INDEX_VIRT_WIDTH 0x6 |
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#define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7 |
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#define VBE_DISPI_INDEX_X_OFFSET 0x8 |
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#define VBE_DISPI_INDEX_Y_OFFSET 0x9 |
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#define VBE_DISPI_INDEX_NB 0xa |
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| 59 |
|
|
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#define VBE_DISPI_ID0 0xB0C0 |
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#define VBE_DISPI_ID1 0xB0C1 |
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#define VBE_DISPI_ID2 0xB0C2 |
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#define VBE_DISPI_DISABLED 0x00 |
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#define VBE_DISPI_ENABLED 0x01 |
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#define VBE_DISPI_LFB_ENABLED 0x40 |
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#define VBE_DISPI_NOCLEARMEM 0x80 |
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#define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000 |
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| 70 |
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typedef struct VGAState {
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uint8_t *vram_ptr; |
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unsigned long vram_offset; |
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unsigned int vram_size; |
|
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uint32_t latch; |
|
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uint8_t sr_index; |
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uint8_t sr[8]; |
|
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uint8_t gr_index; |
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uint8_t gr[16]; |
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uint8_t ar_index; |
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uint8_t ar[21]; |
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int ar_flip_flop; |
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uint8_t cr_index; |
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uint8_t cr[256]; /* CRT registers */ |
|
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uint8_t msr; /* Misc Output Register */ |
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uint8_t fcr; /* Feature Control Register */ |
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uint8_t st00; /* status 0 */ |
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uint8_t st01; /* status 1 */ |
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uint8_t dac_state; |
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uint8_t dac_sub_index; |
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uint8_t dac_read_index; |
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uint8_t dac_write_index; |
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uint8_t dac_cache[3]; /* used when writing */ |
|
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uint8_t palette[768]; |
|
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int32_t bank_offset; |
|
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#ifdef CONFIG_BOCHS_VBE |
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uint16_t vbe_index; |
|
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uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; |
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uint32_t vbe_start_addr; |
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uint32_t vbe_line_offset; |
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uint32_t vbe_bank_mask; |
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#endif |
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/* display refresh support */ |
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DisplayState *ds; |
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uint32_t font_offsets[2]; |
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int graphic_mode; |
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uint8_t shift_control; |
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uint8_t double_scan; |
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uint32_t line_offset; |
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uint32_t line_compare; |
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uint32_t start_addr; |
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uint8_t last_cw, last_ch; |
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uint32_t last_width, last_height; /* in chars or pixels */ |
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uint32_t last_scr_width, last_scr_height; /* in pixels */ |
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uint8_t cursor_start, cursor_end; |
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uint32_t cursor_offset; |
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unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned b); |
|
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/* tell for each page if it has been updated since the last time */ |
|
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uint32_t last_palette[256]; |
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#define CH_ATTR_SIZE (160 * 100) |
|
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uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */ |
|
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} VGAState; |
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/* force some bits to zero */ |
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static const uint8_t sr_mask[8] = {
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const uint8_t sr_mask[8] = {
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(uint8_t)~0xfc, |
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(uint8_t)~0xc2, |
| 128 | 41 |
(uint8_t)~0xf0, |
| ... | ... | |
| 133 | 46 |
(uint8_t)~0x00, |
| 134 | 47 |
}; |
| 135 | 48 |
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static const uint8_t gr_mask[16] = {
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const uint8_t gr_mask[16] = {
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(uint8_t)~0xf0, /* 0x00 */ |
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(uint8_t)~0xf0, /* 0x01 */ |
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(uint8_t)~0xf0, /* 0x02 */ |
| ... | ... | |
| 656 | 569 |
#endif |
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/* called for accesses between 0xa0000 and 0xc0000 */ |
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static uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
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uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr) |
|
| 660 | 573 |
{
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VGAState *s = opaque; |
| 662 | 575 |
int memory_map_mode, plane; |
| ... | ... | |
| 743 | 656 |
} |
| 744 | 657 |
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/* called for accesses between 0xa0000 and 0xc0000 */ |
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static void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
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| 747 | 660 |
{
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VGAState *s = opaque; |
| 749 | 662 |
int memory_map_mode, plane, write_mode, b, func_select; |
| ... | ... | |
| 1027 | 940 |
return full_update; |
| 1028 | 941 |
} |
| 1029 | 942 |
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/* update start_addr and line_offset. Return TRUE if modified */ |
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static int update_basic_params(VGAState *s) |
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static void vga_get_offsets(VGAState *s, |
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uint32_t *pline_offset, |
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uint32_t *pstart_addr) |
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{
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int full_update; |
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uint32_t start_addr, line_offset, line_compare; |
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full_update = 0; |
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uint32_t start_addr, line_offset; |
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#ifdef CONFIG_BOCHS_VBE |
| 1039 | 949 |
if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
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| 1040 | 950 |
line_offset = s->vbe_line_offset; |
| ... | ... | |
| 1061 | 971 |
start_addr |= (s->cr[0x69] & 0x1f) << 16; /* S3 extension */ |
| 1062 | 972 |
#endif |
| 1063 | 973 |
} |
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*pline_offset = line_offset; |
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*pstart_addr = start_addr; |
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} |
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|
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/* update start_addr and line_offset. Return TRUE if modified */ |
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static int update_basic_params(VGAState *s) |
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{
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int full_update; |
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uint32_t start_addr, line_offset, line_compare; |
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| 1064 | 983 |
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full_update = 0; |
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s->get_offsets(s, &line_offset, &start_addr); |
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| 1065 | 987 |
/* line compare */ |
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line_compare = s->cr[0x18] | |
| 1067 | 989 |
((s->cr[0x07] & 0x10) << 4) | |
| ... | ... | |
| 1373 | 1295 |
vga_draw_line32_32, |
| 1374 | 1296 |
}; |
| 1375 | 1297 |
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static int vga_get_bpp(VGAState *s) |
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{
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int ret; |
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#ifdef CONFIG_BOCHS_VBE |
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if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
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ret = s->vbe_regs[VBE_DISPI_INDEX_BPP]; |
|
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} else |
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#endif |
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{
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ret = 0; |
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} |
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return ret; |
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} |
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|
|
| 1376 | 1312 |
/* |
| 1377 | 1313 |
* graphic modes |
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* Missing: |
| ... | ... | |
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v = VGA_DRAW_LINE2; |
| 1430 | 1366 |
} |
| 1431 | 1367 |
} else {
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#ifdef CONFIG_BOCHS_VBE |
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if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
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switch(s->vbe_regs[VBE_DISPI_INDEX_BPP]) {
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default: |
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case 8: |
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full_update |= update_palette256(s); |
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v = VGA_DRAW_LINE8; |
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break; |
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| 1440 |
case 15: |
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v = VGA_DRAW_LINE15; |
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break; |
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| 1443 |
case 16: |
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v = VGA_DRAW_LINE16; |
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break; |
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| 1446 |
case 24: |
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v = VGA_DRAW_LINE24; |
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break; |
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| 1449 |
case 32: |
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v = VGA_DRAW_LINE32; |
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break; |
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} |
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} else |
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#endif |
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{
|
|
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switch(s->get_bpp(s)) {
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default: |
|
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case 0: |
|
| 1456 | 1371 |
full_update |= update_palette256(s); |
| 1457 | 1372 |
v = VGA_DRAW_LINE8D2; |
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break; |
|
| 1374 |
case 8: |
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full_update |= update_palette256(s); |
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v = VGA_DRAW_LINE8; |
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break; |
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| 1378 |
case 15: |
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v = VGA_DRAW_LINE15; |
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break; |
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case 16: |
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v = VGA_DRAW_LINE16; |
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break; |
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| 1384 |
case 24: |
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v = VGA_DRAW_LINE24; |
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break; |
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| 1387 |
case 32: |
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| 1388 |
v = VGA_DRAW_LINE32; |
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| 1389 |
break; |
|
| 1458 | 1390 |
} |
| 1459 | 1391 |
} |
| 1460 | 1392 |
vga_draw_line = vga_draw_line_table[v * 4 + get_depth_index(s->ds->depth)]; |
| ... | ... | |
| 1747 | 1679 |
cpu_register_physical_memory(addr, s->vram_size, s->vram_offset); |
| 1748 | 1680 |
} |
| 1749 | 1681 |
|
| 1750 |
int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base, |
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| 1751 |
unsigned long vga_ram_offset, int vga_ram_size, |
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| 1752 |
int is_pci) |
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| 1682 |
void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base, |
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| 1683 |
unsigned long vga_ram_offset, int vga_ram_size) |
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| 1753 | 1684 |
{
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| 1754 |
VGAState *s = &vga_state; |
|
| 1755 | 1685 |
int i, j, v, b; |
| 1756 | 1686 |
|
| 1757 | 1687 |
for(i = 0;i < 256; i++) {
|
| ... | ... | |
| 1783 | 1713 |
s->vram_offset = vga_ram_offset; |
| 1784 | 1714 |
s->vram_size = vga_ram_size; |
| 1785 | 1715 |
s->ds = ds; |
| 1716 |
s->get_bpp = vga_get_bpp; |
|
| 1717 |
s->get_offsets = vga_get_offsets; |
|
| 1718 |
} |
|
| 1719 |
|
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| 1720 |
|
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| 1721 |
int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base, |
|
| 1722 |
unsigned long vga_ram_offset, int vga_ram_size, |
|
| 1723 |
int is_pci) |
|
| 1724 |
{
|
|
| 1725 |
VGAState *s = &vga_state; |
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| 1726 |
|
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| 1727 |
vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size); |
|
| 1786 | 1728 |
|
| 1787 | 1729 |
register_savevm("vga", 0, 1, vga_save, vga_load, s);
|
| 1788 | 1730 |
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