Revision 79aceca5
b/linux-user/ppc/syscall.h | ||
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/* |
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* PPC emulation for qemu: syscall definitions. |
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* |
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* Copyright (c) 2003 Jocelyn Mayer |
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* |
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* This library is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU Lesser General Public |
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* License as published by the Free Software Foundation; either |
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* version 2 of the License, or (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public |
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* License along with this library; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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*/ |
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/* XXX: ABSOLUTELY BUGGY: |
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* for now, this is quite just a cut-and-paste from i386 target... |
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*/ |
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/* default linux values for the selectors */ |
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#define __USER_DS (1) |
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struct target_pt_regs { |
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unsigned long gpr[32]; |
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unsigned long nip; |
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unsigned long msr; |
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unsigned long orig_gpr3; /* Used for restarting system calls */ |
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unsigned long ctr; |
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unsigned long link; |
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unsigned long xer; |
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unsigned long ccr; |
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unsigned long mq; /* 601 only (not used at present) */ |
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/* Used on APUS to hold IPL value. */ |
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unsigned long trap; /* Reason for being here */ |
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unsigned long dar; /* Fault registers */ |
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unsigned long dsisr; |
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unsigned long result; /* Result of a system call */ |
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}; |
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/* ioctls */ |
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struct target_revectored_struct { |
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target_ulong __map[8]; /* 256 bits */ |
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}; |
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/* |
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* flags masks |
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*/ |
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/* ipcs */ |
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#define TARGET_SEMOP 1 |
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#define TARGET_SEMGET 2 |
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#define TARGET_SEMCTL 3 |
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#define TARGET_MSGSND 11 |
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#define TARGET_MSGRCV 12 |
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#define TARGET_MSGGET 13 |
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#define TARGET_MSGCTL 14 |
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#define TARGET_SHMAT 21 |
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#define TARGET_SHMDT 22 |
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#define TARGET_SHMGET 23 |
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#define TARGET_SHMCTL 24 |
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struct target_msgbuf { |
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int mtype; |
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char mtext[1]; |
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}; |
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struct target_ipc_kludge { |
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unsigned int msgp; /* Really (struct msgbuf *) */ |
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int msgtyp; |
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}; |
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struct target_ipc_perm { |
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int key; |
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unsigned short uid; |
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unsigned short gid; |
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unsigned short cuid; |
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unsigned short cgid; |
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unsigned short mode; |
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unsigned short seq; |
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}; |
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struct target_msqid_ds { |
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struct target_ipc_perm msg_perm; |
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unsigned int msg_first; /* really struct target_msg* */ |
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unsigned int msg_last; /* really struct target_msg* */ |
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unsigned int msg_stime; /* really target_time_t */ |
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unsigned int msg_rtime; /* really target_time_t */ |
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unsigned int msg_ctime; /* really target_time_t */ |
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unsigned int wwait; /* really struct wait_queue* */ |
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unsigned int rwait; /* really struct wait_queue* */ |
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unsigned short msg_cbytes; |
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unsigned short msg_qnum; |
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unsigned short msg_qbytes; |
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unsigned short msg_lspid; |
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unsigned short msg_lrpid; |
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}; |
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struct target_shmid_ds { |
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struct target_ipc_perm shm_perm; |
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int shm_segsz; |
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unsigned int shm_atime; /* really target_time_t */ |
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unsigned int shm_dtime; /* really target_time_t */ |
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unsigned int shm_ctime; /* really target_time_t */ |
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unsigned short shm_cpid; |
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unsigned short shm_lpid; |
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short shm_nattch; |
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unsigned short shm_npages; |
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unsigned long *shm_pages; |
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void *attaches; /* really struct shm_desc * */ |
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}; |
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#define TARGET_IPC_RMID 0 |
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#define TARGET_IPC_SET 1 |
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#define TARGET_IPC_STAT 2 |
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union target_semun { |
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int val; |
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unsigned int buf; /* really struct semid_ds * */ |
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unsigned int array; /* really unsigned short * */ |
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unsigned int __buf; /* really struct seminfo * */ |
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unsigned int __pad; /* really void* */ |
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}; |
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b/linux-user/ppc/syscall_nr.h | ||
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/* |
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* This file contains the system call numbers. |
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*/ |
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#define TARGET_NR_restart_syscall 0 |
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#define TARGET_NR_exit 1 |
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#define TARGET_NR_fork 2 |
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#define TARGET_NR_read 3 |
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#define TARGET_NR_write 4 |
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#define TARGET_NR_open 5 |
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#define TARGET_NR_close 6 |
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#define TARGET_NR_waitpid 7 |
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#define TARGET_NR_creat 8 |
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#define TARGET_NR_link 9 |
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#define TARGET_NR_unlink 10 |
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#define TARGET_NR_execve 11 |
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#define TARGET_NR_chdir 12 |
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#define TARGET_NR_time 13 |
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#define TARGET_NR_mknod 14 |
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#define TARGET_NR_chmod 15 |
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#define TARGET_NR_lchown32 16 |
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#define TARGET_NR_break 17 |
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#define TARGET_NR_oldstat 18 |
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#define TARGET_NR_lseek 19 |
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#define TARGET_NR_getpid 20 |
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#define TARGET_NR_mount 21 |
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#define TARGET_NR_umount 22 |
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#define TARGET_NR_setuid32 23 |
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#define TARGET_NR_getuid32 24 |
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#define TARGET_NR_stime 25 |
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#define TARGET_NR_ptrace 26 |
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#define TARGET_NR_alarm 27 |
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#define TARGET_NR_oldfstat 28 |
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#define TARGET_NR_pause 29 |
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#define TARGET_NR_utime 30 |
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#define TARGET_NR_stty 31 |
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#define TARGET_NR_gtty 32 |
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#define TARGET_NR_access 33 |
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#define TARGET_NR_nice 34 |
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#define TARGET_NR_ftime 35 |
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#define TARGET_NR_sync 36 |
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#define TARGET_NR_kill 37 |
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#define TARGET_NR_rename 38 |
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#define TARGET_NR_mkdir 39 |
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#define TARGET_NR_rmdir 40 |
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#define TARGET_NR_dup 41 |
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#define TARGET_NR_pipe 42 |
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#define TARGET_NR_times 43 |
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#define TARGET_NR_prof 44 |
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#define TARGET_NR_brk 45 |
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#define TARGET_NR_setgid32 46 |
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#define TARGET_NR_getgid32 47 |
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#define TARGET_NR_signal 48 |
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#define TARGET_NR_geteuid32 49 |
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#define TARGET_NR_getegid32 50 |
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#define TARGET_NR_acct 51 |
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#define TARGET_NR_umount2 52 |
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#define TARGET_NR_lock 53 |
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#define TARGET_NR_ioctl 54 |
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#define TARGET_NR_fcntl 55 |
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#define TARGET_NR_mpx 56 |
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#define TARGET_NR_setpgid 57 |
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#define TARGET_NR_ulimit 58 |
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#define TARGET_NR_oldolduname 59 |
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#define TARGET_NR_umask 60 |
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#define TARGET_NR_chroot 61 |
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#define TARGET_NR_ustat 62 |
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#define TARGET_NR_dup2 63 |
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#define TARGET_NR_getppid 64 |
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#define TARGET_NR_getpgrp 65 |
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#define TARGET_NR_setsid 66 |
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#define TARGET_NR_sigaction 67 |
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#define TARGET_NR_sgetmask 68 |
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#define TARGET_NR_ssetmask 69 |
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#define TARGET_NR_setreuid32 70 |
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#define TARGET_NR_setregid32 71 |
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#define TARGET_NR_sigsuspend 72 |
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#define TARGET_NR_sigpending 73 |
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#define TARGET_NR_sethostname 74 |
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#define TARGET_NR_setrlimit 75 |
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#define TARGET_NR_getrlimit 76 |
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#define TARGET_NR_getrusage 77 |
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#define TARGET_NR_gettimeofday 78 |
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#define TARGET_NR_settimeofday 79 |
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#define TARGET_NR_getgroups32 80 |
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#define TARGET_NR_setgroups32 81 |
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#define TARGET_NR_select 82 |
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#define TARGET_NR_symlink 83 |
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#define TARGET_NR_oldlstat 84 |
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#define TARGET_NR_readlink 85 |
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#define TARGET_NR_uselib 86 |
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#define TARGET_NR_swapon 87 |
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#define TARGET_NR_reboot 88 |
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#define TARGET_NR_readdir 89 |
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#define TARGET_NR_mmap 90 |
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#define TARGET_NR_munmap 91 |
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#define TARGET_NR_truncate 92 |
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#define TARGET_NR_ftruncate 93 |
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#define TARGET_NR_fchmod 94 |
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#define TARGET_NR_fchown32 95 |
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#define TARGET_NR_getpriority 96 |
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#define TARGET_NR_setpriority 97 |
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#define TARGET_NR_profil 98 |
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#define TARGET_NR_statfs 99 |
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#define TARGET_NR_fstatfs 100 |
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#define TARGET_NR_ioperm 101 |
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#define TARGET_NR_socketcall 102 |
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#define TARGET_NR_syslog 103 |
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#define TARGET_NR_setitimer 104 |
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#define TARGET_NR_getitimer 105 |
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#define TARGET_NR_stat 106 |
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#define TARGET_NR_lstat 107 |
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#define TARGET_NR_fstat 108 |
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#define TARGET_NR_olduname 109 |
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#define TARGET_NR_iopl 110 |
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#define TARGET_NR_vhangup 111 |
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#define TARGET_NR_idle 112 |
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#define TARGET_NR_vm86 113 |
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#define TARGET_NR_wait4 114 |
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#define TARGET_NR_swapoff 115 |
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#define TARGET_NR_sysinfo 116 |
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#define TARGET_NR_ipc 117 |
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#define TARGET_NR_fsync 118 |
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#define TARGET_NR_sigreturn 119 |
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#define TARGET_NR_clone 120 |
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#define TARGET_NR_setdomainname 121 |
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#define TARGET_NR_uname 122 |
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#define TARGET_NR_modify_ldt 123 |
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#define TARGET_NR_adjtimex 124 |
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#define TARGET_NR_mprotect 125 |
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#define TARGET_NR_sigprocmask 126 |
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#define TARGET_NR_create_module 127 |
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#define TARGET_NR_init_module 128 |
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#define TARGET_NR_delete_module 129 |
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#define TARGET_NR_get_kernel_syms 130 |
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#define TARGET_NR_quotactl 131 |
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#define TARGET_NR_getpgid 132 |
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#define TARGET_NR_fchdir 133 |
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#define TARGET_NR_bdflush 134 |
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#define TARGET_NR_sysfs 135 |
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#define TARGET_NR_personality 136 |
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#define TARGET_NR_afs_syscall 137 /* Syscall for Andrew File System */ |
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#define TARGET_NR_setfsuid32 138 |
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#define TARGET_NR_setfsgid32 139 |
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#define TARGET_NR__llseek 140 |
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#define TARGET_NR_getdents 141 |
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#define TARGET_NR__newselect 142 |
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#define TARGET_NR_flock 143 |
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#define TARGET_NR_msync 144 |
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#define TARGET_NR_readv 145 |
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#define TARGET_NR_writev 146 |
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#define TARGET_NR_getsid 147 |
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#define TARGET_NR_fdatasync 148 |
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#define TARGET_NR__sysctl 149 |
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#define TARGET_NR_mlock 150 |
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#define TARGET_NR_munlock 151 |
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#define TARGET_NR_mlockall 152 |
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#define TARGET_NR_munlockall 153 |
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#define TARGET_NR_sched_setparam 154 |
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#define TARGET_NR_sched_getparam 155 |
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#define TARGET_NR_sched_setscheduler 156 |
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#define TARGET_NR_sched_getscheduler 157 |
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#define TARGET_NR_sched_yield 158 |
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#define TARGET_NR_sched_get_priority_max 159 |
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#define TARGET_NR_sched_get_priority_min 160 |
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#define TARGET_NR_sched_rr_get_interval 161 |
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#define TARGET_NR_nanosleep 162 |
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#define TARGET_NR_mremap 163 |
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#define TARGET_NR_setresuid32 164 |
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#define TARGET_NR_getresuid32 165 |
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#define TARGET_NR_query_module 166 |
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#define TARGET_NR_poll 167 |
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#define TARGET_NR_nfsservctl 168 |
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#define TARGET_NR_setresgid32 169 |
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#define TARGET_NR_getresgid32 170 |
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#define TARGET_NR_prctl 171 |
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#define TARGET_NR_rt_sigreturn 172 |
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#define TARGET_NR_rt_sigaction 173 |
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#define TARGET_NR_rt_sigprocmask 174 |
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#define TARGET_NR_rt_sigpending 175 |
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#define TARGET_NR_rt_sigtimedwait 176 |
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#define TARGET_NR_rt_sigqueueinfo 177 |
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#define TARGET_NR_rt_sigsuspend 178 |
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#define TARGET_NR_pread64 179 |
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#define TARGET_NR_pwrite64 180 |
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#define TARGET_NR_chown32 181 |
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#define TARGET_NR_getcwd 182 |
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#define TARGET_NR_capget 183 |
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#define TARGET_NR_capset 184 |
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#define TARGET_NR_sigaltstack 185 |
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#define TARGET_NR_sendfile 186 |
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#define TARGET_NR_getpmsg 187 /* some people actually want streams */ |
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#define TARGET_NR_putpmsg 188 /* some people actually want streams */ |
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#define TARGET_NR_vfork 189 |
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#define TARGET_NR_ugetrlimit 190 /* SuS compliant getrlimit */ |
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#define TARGET_NR_readahead 191 |
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#define TARGET_NR_mmap2 192 |
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#define TARGET_NR_truncate64 193 |
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#define TARGET_NR_ftruncate64 194 |
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#define TARGET_NR_stat64 195 |
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#define TARGET_NR_lstat64 196 |
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#define TARGET_NR_fstat64 197 |
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#define TARGET_NR_pciconfig_read 198 |
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#define TARGET_NR_pciconfig_write 199 |
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#define TARGET_NR_pciconfig_iobase 200 |
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#define TARGET_NR_multiplexer 201 |
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#define TARGET_NR_getdents64 202 |
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#define TARGET_NR_pivot_root 203 |
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#define TARGET_NR_fcntl64 204 |
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#define TARGET_NR_madvise 205 |
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#define TARGET_NR_mincore 206 |
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#define TARGET_NR_gettid 207 |
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#define TARGET_NR_tkill 208 |
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#define TARGET_NR_setxattr 209 |
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#define TARGET_NR_lsetxattr 210 |
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#define TARGET_NR_fsetxattr 211 |
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#define TARGET_NR_getxattr 212 |
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#define TARGET_NR_lgetxattr 213 |
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#define TARGET_NR_fgetxattr 214 |
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#define TARGET_NR_listxattr 215 |
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#define TARGET_NR_llistxattr 216 |
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#define TARGET_NR_flistxattr 217 |
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#define TARGET_NR_removexattr 218 |
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#define TARGET_NR_lremovexattr 219 |
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#define TARGET_NR_fremovexattr 220 |
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#define TARGET_NR_futex 221 |
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#define TARGET_NR_sched_setaffinity 222 |
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#define TARGET_NR_sched_getaffinity 223 |
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/* 224 currently unused */ |
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#define TARGET_NR_tuxcall 225 |
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#define TARGET_NR_sendfile64 226 |
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#define TARGET_NR_io_setup 227 |
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#define TARGET_NR_io_destroy 228 |
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#define TARGET_NR_io_getevents 229 |
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#define TARGET_NR_io_submit 230 |
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#define TARGET_NR_io_cancel 231 |
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#define TARGET_NR_set_tid_address 232 |
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#define TARGET_NR_fadvise64 233 |
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#define TARGET_NR_exit_group 234 |
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#define TARGET_NR_lookup_dcookie 235 |
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#define TARGET_NR_epoll_create 236 |
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#define TARGET_NR_epoll_ctl 237 |
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#define TARGET_NR_epoll_wait 238 |
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#define TARGET_NR_remap_file_pages 239 |
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#define TARGET_NR_timer_create 240 |
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#define TARGET_NR_timer_settime 241 |
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#define TARGET_NR_timer_gettime 242 |
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#define TARGET_NR_timer_getoverrun 243 |
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#define TARGET_NR_timer_delete 244 |
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#define TARGET_NR_clock_settime 245 |
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#define TARGET_NR_clock_gettime 246 |
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#define TARGET_NR_clock_getres 247 |
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#define TARGET_NR_clock_nanosleep 248 |
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#define TARGET_NR_swapcontext 249 |
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#define TARGET_NR_tgkill 250 |
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#define TARGET_NR_utimes 251 |
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#define TARGET_NR_statfs64 252 |
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#define TARGET_NR_fstatfs64 253 |
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#define TARGET_NR_fadvise64_64 254 |
b/target-ppc/cpu.h | ||
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1 |
/* |
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2 |
* PPC emulation cpu definitions for qemu. |
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3 |
* |
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4 |
* Copyright (c) 2003 Jocelyn Mayer |
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5 |
* |
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6 |
* This library is free software; you can redistribute it and/or |
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7 |
* modify it under the terms of the GNU Lesser General Public |
|
8 |
* License as published by the Free Software Foundation; either |
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9 |
* version 2 of the License, or (at your option) any later version. |
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10 |
* |
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11 |
* This library is distributed in the hope that it will be useful, |
|
12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
|
14 |
* Lesser General Public License for more details. |
|
15 |
* |
|
16 |
* You should have received a copy of the GNU Lesser General Public |
|
17 |
* License along with this library; if not, write to the Free Software |
|
18 |
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
19 |
*/ |
|
20 |
#if !defined (__CPU_PPC_H__) |
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21 |
#define __CPU_PPC_H__ |
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22 |
|
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23 |
#include <endian.h> |
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24 |
#include <asm/byteorder.h> |
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25 |
|
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26 |
#include "cpu-defs.h" |
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27 |
|
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28 |
/*** Sign extend constants ***/ |
|
29 |
/* 8 to 32 bits */ |
|
30 |
static inline int32_t s_ext8 (uint8_t value) |
|
31 |
{ |
|
32 |
int8_t *tmp = &value; |
|
33 |
|
|
34 |
return *tmp; |
|
35 |
} |
|
36 |
|
|
37 |
/* 16 to 32 bits */ |
|
38 |
static inline int32_t s_ext16 (uint16_t value) |
|
39 |
{ |
|
40 |
int16_t *tmp = &value; |
|
41 |
|
|
42 |
return *tmp; |
|
43 |
} |
|
44 |
|
|
45 |
/* 24 to 32 bits */ |
|
46 |
static inline int32_t s_ext24 (uint32_t value) |
|
47 |
{ |
|
48 |
uint16_t utmp = (value >> 8) & 0xFFFF; |
|
49 |
int16_t *tmp = &utmp; |
|
50 |
|
|
51 |
return (*tmp << 8) | (value & 0xFF); |
|
52 |
} |
|
53 |
|
|
54 |
#include "config.h" |
|
55 |
#include <setjmp.h> |
|
56 |
|
|
57 |
/* Floting point status and control register */ |
|
58 |
#define FPSCR_FX 31 |
|
59 |
#define FPSCR_FEX 30 |
|
60 |
#define FPSCR_VX 29 |
|
61 |
#define FPSCR_OX 28 |
|
62 |
#define FPSCR_UX 27 |
|
63 |
#define FPSCR_ZX 26 |
|
64 |
#define FPSCR_XX 25 |
|
65 |
#define FPSCR_VXSNAN 24 |
|
66 |
#define FPSCR_VXISI 26 |
|
67 |
#define FPSCR_VXIDI 25 |
|
68 |
#define FPSCR_VXZDZ 21 |
|
69 |
#define FPSCR_VXIMZ 20 |
|
70 |
|
|
71 |
#define FPSCR_VXVC 18 |
|
72 |
#define FPSCR_FR 17 |
|
73 |
#define FPSCR_FI 16 |
|
74 |
#define FPSCR_FPRF 11 |
|
75 |
#define FPSCR_VXSOFT 9 |
|
76 |
#define FPSCR_VXSQRT 8 |
|
77 |
#define FPSCR_VXCVI 7 |
|
78 |
#define FPSCR_OE 6 |
|
79 |
#define FPSCR_UE 5 |
|
80 |
#define FPSCR_ZE 4 |
|
81 |
#define FPSCR_XE 3 |
|
82 |
#define FPSCR_NI 2 |
|
83 |
#define FPSCR_RN 0 |
|
84 |
#define fpscr_fx env->fpscr[FPSCR_FX] |
|
85 |
#define fpscr_fex env->fpscr[FPSCR_FEX] |
|
86 |
#define fpscr_vx env->fpscr[FPSCR_VX] |
|
87 |
#define fpscr_ox env->fpscr[FPSCR_OX] |
|
88 |
#define fpscr_ux env->fpscr[FPSCR_UX] |
|
89 |
#define fpscr_zx env->fpscr[FPSCR_ZX] |
|
90 |
#define fpscr_xx env->fpscr[FPSCR_XX] |
|
91 |
#define fpscr_vsxnan env->fpscr[FPSCR_VXSNAN] |
|
92 |
#define fpscr_vxisi env->fpscr[FPSCR_VXISI] |
|
93 |
#define fpscr_vxidi env->fpscr[FPSCR_VXIDI] |
|
94 |
#define fpscr_vxzdz env->fpscr[FPSCR_VXZDZ] |
|
95 |
#define fpscr_vximz env->fpscr[FPSCR_VXIMZ] |
|
96 |
#define fpscr_fr env->fpscr[FPSCR_FR] |
|
97 |
#define fpscr_fi env->fpscr[FPSCR_FI] |
|
98 |
#define fpscr_fprf env->fpscr[FPSCR_FPRF] |
|
99 |
#define fpscr_vxsoft env->fpscr[FPSCR_VXSOFT] |
|
100 |
#define fpscr_vxsqrt env->fpscr[FPSCR_VXSQRT] |
|
101 |
#define fpscr_oe env->fpscr[FPSCR_OE] |
|
102 |
#define fpscr_ue env->fpscr[FPSCR_UE] |
|
103 |
#define fpscr_ze env->fpscr[FPSCR_ZE] |
|
104 |
#define fpscr_xe env->fpscr[FPSCR_XE] |
|
105 |
#define fpscr_ni env->fpscr[FPSCR_NI] |
|
106 |
#define fpscr_rn env->fpscr[FPSCR_RN] |
|
107 |
|
|
108 |
/* Supervisor mode registers */ |
|
109 |
/* Machine state register */ |
|
110 |
#define MSR_POW 18 |
|
111 |
#define MSR_ILE 16 |
|
112 |
#define MSR_EE 15 |
|
113 |
#define MSR_PR 14 |
|
114 |
#define MSR_FP 13 |
|
115 |
#define MSR_ME 12 |
|
116 |
#define MSR_FE0 11 |
|
117 |
#define MSR_SE 10 |
|
118 |
#define MSR_BE 9 |
|
119 |
#define MSR_FE1 8 |
|
120 |
#define MSR_IP 6 |
|
121 |
#define MSR_IR 5 |
|
122 |
#define MSR_DR 4 |
|
123 |
#define MSR_RI 1 |
|
124 |
#define MSR_LE 0 |
|
125 |
#define msr_pow env->msr[MSR_POW] |
|
126 |
#define msr_ile env->msr[MSR_ILE] |
|
127 |
#define msr_ee env->msr[MSR_EE] |
|
128 |
#define msr_pr env->msr[MSR_PR] |
|
129 |
#define msr_fp env->msr[MSR_FP] |
|
130 |
#define msr_me env->msr[MSR_ME] |
|
131 |
#define msr_fe0 env->msr[MSR_FE0] |
|
132 |
#define msr_se env->msr[MSR_SE] |
|
133 |
#define msr_be env->msr[MSR_BE] |
|
134 |
#define msr_fe1 env->msr[MSR_FE1] |
|
135 |
#define msr_ip env->msr[MSR_IP] |
|
136 |
#define msr_ir env->msr[MSR_IR] |
|
137 |
#define msr_dr env->msr[MSR_DR] |
|
138 |
#define msr_ri env->msr[MSR_RI] |
|
139 |
#define msr_le env->msr[MSR_LE] |
|
140 |
|
|
141 |
/* Segment registers */ |
|
142 |
typedef struct ppc_sr_t { |
|
143 |
uint32_t t:1; |
|
144 |
uint32_t ks:1; |
|
145 |
uint32_t kp:1; |
|
146 |
uint32_t n:1; |
|
147 |
uint32_t res:4; |
|
148 |
uint32_t vsid:24; |
|
149 |
} ppc_sr_t; |
|
150 |
|
|
151 |
typedef struct CPUPPCState { |
|
152 |
/* general purpose registers */ |
|
153 |
uint32_t gpr[32]; |
|
154 |
/* floating point registers */ |
|
155 |
uint64_t fpr[32]; |
|
156 |
/* segment registers */ |
|
157 |
ppc_sr_t sr[16]; |
|
158 |
/* special purpose registers */ |
|
159 |
uint32_t spr[1024]; |
|
160 |
/* XER */ |
|
161 |
uint8_t xer[32]; |
|
162 |
/* Reservation address */ |
|
163 |
uint32_t reserve; |
|
164 |
/* machine state register */ |
|
165 |
uint8_t msr[32]; |
|
166 |
/* condition register */ |
|
167 |
uint8_t crf[8]; |
|
168 |
/* floating point status and control register */ |
|
169 |
uint8_t fpscr[32]; |
|
170 |
uint32_t nip; |
|
171 |
/* CPU exception code */ |
|
172 |
uint32_t exception; |
|
173 |
|
|
174 |
/* qemu dedicated */ |
|
175 |
int interrupt_request; |
|
176 |
jmp_buf jmp_env; |
|
177 |
int exception_index; |
|
178 |
int error_code; |
|
179 |
int user_mode_only; /* user mode only simulation */ |
|
180 |
struct TranslationBlock *current_tb; /* currently executing TB */ |
|
181 |
|
|
182 |
/* user data */ |
|
183 |
void *opaque; |
|
184 |
} CPUPPCState; |
|
185 |
|
|
186 |
CPUPPCState *cpu_ppc_init(void); |
|
187 |
int cpu_ppc_exec(CPUPPCState *s); |
|
188 |
void cpu_ppc_close(CPUPPCState *s); |
|
189 |
/* you can call this signal handler from your SIGBUS and SIGSEGV |
|
190 |
signal handlers to inform the virtual CPU of exceptions. non zero |
|
191 |
is returned if the signal was handled by the virtual CPU. */ |
|
192 |
struct siginfo; |
|
193 |
int cpu_ppc_signal_handler(int host_signum, struct siginfo *info, |
|
194 |
void *puc); |
|
195 |
|
|
196 |
void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags); |
|
197 |
|
|
198 |
#define TARGET_PAGE_BITS 12 |
|
199 |
#include "cpu-all.h" |
|
200 |
|
|
201 |
#define ugpr(n) (env->gpr[n]) |
|
202 |
#define fpr(n) (env->fpr[n]) |
|
203 |
|
|
204 |
#define SPR_ENCODE(sprn) \ |
|
205 |
(((sprn) >> 5) | (((sprn) & 0x1F) << 5)) |
|
206 |
|
|
207 |
/* User mode SPR */ |
|
208 |
#define spr(n) env->spr[n] |
|
209 |
//#define XER spr[1] |
|
210 |
#define XER env->xer |
|
211 |
#define XER_SO 31 |
|
212 |
#define XER_OV 30 |
|
213 |
#define XER_CA 29 |
|
214 |
#define XER_BC 0 |
|
215 |
#define xer_so env->xer[XER_SO] |
|
216 |
#define xer_ov env->xer[XER_OV] |
|
217 |
#define xer_ca env->xer[XER_CA] |
|
218 |
#define xer_bc env->xer[XER_BC] |
|
219 |
|
|
220 |
#define LR spr[SPR_ENCODE(8)] |
|
221 |
#define CTR spr[SPR_ENCODE(9)] |
|
222 |
/* VEA mode SPR */ |
|
223 |
#define V_TBL spr[SPR_ENCODE(268)] |
|
224 |
#define V_TBU spr[SPR_ENCODE(269)] |
|
225 |
/* supervisor mode SPR */ |
|
226 |
#define DSISR spr[SPR_ENCODE(18)] |
|
227 |
#define DAR spr[SPR_ENCODE(19)] |
|
228 |
#define DEC spr[SPR_ENCODE(22)] |
|
229 |
#define SDR1 spr[SPR_ENCODE(25)] |
|
230 |
typedef struct ppc_sdr1_t { |
|
231 |
uint32_t htaborg:16; |
|
232 |
uint32_t res:7; |
|
233 |
uint32_t htabmask:9; |
|
234 |
} ppc_sdr1_t; |
|
235 |
#define SRR0 spr[SPR_ENCODE(26)] |
|
236 |
#define SRR0_MASK 0xFFFFFFFC |
|
237 |
#define SRR1 spr[SPR_ENCODE(27)] |
|
238 |
#define SPRG0 spr[SPR_ENCODE(272)] |
|
239 |
#define SPRG1 spr[SPR_ENCODE(273)] |
|
240 |
#define SPRG2 spr[SPR_ENCODE(274)] |
|
241 |
#define SPRG3 spr[SPR_ENCODE(275)] |
|
242 |
#define EAR spr[SPR_ENCODE(282)] |
|
243 |
typedef struct ppc_ear_t { |
|
244 |
uint32_t e:1; |
|
245 |
uint32_t res:25; |
|
246 |
uint32_t rid:6; |
|
247 |
} ppc_ear_t; |
|
248 |
#define TBL spr[SPR_ENCODE(284)] |
|
249 |
#define TBU spr[SPR_ENCODE(285)] |
|
250 |
#define PVR spr[SPR_ENCODE(287)] |
|
251 |
typedef struct ppc_pvr_t { |
|
252 |
uint32_t version:16; |
|
253 |
uint32_t revision:16; |
|
254 |
} ppc_pvr_t; |
|
255 |
#define IBAT0U spr[SPR_ENCODE(528)] |
|
256 |
#define IBAT0L spr[SPR_ENCODE(529)] |
|
257 |
#define IBAT1U spr[SPR_ENCODE(530)] |
|
258 |
#define IBAT1L spr[SPR_ENCODE(531)] |
|
259 |
#define IBAT2U spr[SPR_ENCODE(532)] |
|
260 |
#define IBAT2L spr[SPR_ENCODE(533)] |
|
261 |
#define IBAT3U spr[SPR_ENCODE(534)] |
|
262 |
#define IBAT3L spr[SPR_ENCODE(535)] |
|
263 |
#define DBAT0U spr[SPR_ENCODE(536)] |
|
264 |
#define DBAT0L spr[SPR_ENCODE(537)] |
|
265 |
#define DBAT1U spr[SPR_ENCODE(538)] |
|
266 |
#define DBAT1L spr[SPR_ENCODE(539)] |
|
267 |
#define DBAT2U spr[SPR_ENCODE(540)] |
|
268 |
#define DBAT2L spr[SPR_ENCODE(541)] |
|
269 |
#define DBAT3U spr[SPR_ENCODE(542)] |
|
270 |
#define DBAT3L spr[SPR_ENCODE(543)] |
|
271 |
typedef struct ppc_ubat_t { |
|
272 |
uint32_t bepi:15; |
|
273 |
uint32_t res:4; |
|
274 |
uint32_t bl:11; |
|
275 |
uint32_t vs:1; |
|
276 |
uint32_t vp:1; |
|
277 |
} ppc_ubat_t; |
|
278 |
typedef struct ppc_lbat_t { |
|
279 |
uint32_t brpn:15; |
|
280 |
uint32_t res0:10; |
|
281 |
uint32_t w:1; |
|
282 |
uint32_t i:1; |
|
283 |
uint32_t m:1; |
|
284 |
uint32_t g:1; |
|
285 |
uint32_t res1:1; |
|
286 |
uint32_t pp:2; |
|
287 |
} ppc_lbat_t; |
|
288 |
#define DABR spr[SPR_ENCODE(1013)] |
|
289 |
#define DABR_MASK 0xFFFFFFF8 |
|
290 |
typedef struct ppc_dabr_t { |
|
291 |
uint32_t dab:29; |
|
292 |
uint32_t bt:1; |
|
293 |
uint32_t dw:1; |
|
294 |
uint32_t dr:1; |
|
295 |
} ppc_dabr_t; |
|
296 |
#define FPECR spr[SPR_ENCODE(1022)] |
|
297 |
#define PIR spr[SPR_ENCODE(1023)] |
|
298 |
|
|
299 |
#define TARGET_PAGE_BITS 12 |
|
300 |
#include "cpu-all.h" |
|
301 |
|
|
302 |
CPUPPCState *cpu_ppc_init(void); |
|
303 |
int cpu_ppc_exec(CPUPPCState *s); |
|
304 |
void cpu_ppc_close(CPUPPCState *s); |
|
305 |
void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags); |
|
306 |
|
|
307 |
/* Exeptions */ |
|
308 |
enum { |
|
309 |
EXCP_NONE = 0x00, |
|
310 |
/* PPC hardware exceptions : exception vector / 0x100 */ |
|
311 |
EXCP_RESET = 0x01, /* System reset */ |
|
312 |
EXCP_MACHINE_CHECK = 0x02, /* Machine check exception */ |
|
313 |
EXCP_DSI = 0x03, /* Impossible memory access */ |
|
314 |
EXCP_ISI = 0x04, /* Impossible instruction fetch */ |
|
315 |
EXCP_EXTERNAL = 0x05, /* External interruption */ |
|
316 |
EXCP_ALIGN = 0x06, /* Alignment exception */ |
|
317 |
EXCP_PROGRAM = 0x07, /* Program exception */ |
|
318 |
EXCP_NO_FP = 0x08, /* No floating point */ |
|
319 |
EXCP_DECR = 0x09, /* Decrementer exception */ |
|
320 |
EXCP_RESA = 0x0A, /* Implementation specific */ |
|
321 |
EXCP_RESB = 0x0B, /* Implementation specific */ |
|
322 |
EXCP_SYSCALL = 0x0C, /* System call */ |
|
323 |
EXCP_TRACE = 0x0D, /* Trace exception (optional) */ |
|
324 |
EXCP_FP_ASSIST = 0x0E, /* Floating-point assist (optional) */ |
|
325 |
#if 0 |
|
326 |
/* Exeption subtypes for EXCP_DSI */ |
|
327 |
EXCP_DSI_TRANSLATE = 0x10301, /* Data address can't be translated */ |
|
328 |
EXCP_DSI_NOTSUP = 0x10302, /* Access type not supported */ |
|
329 |
EXCP_DSI_PROT = 0x10303, /* Memory protection violation */ |
|
330 |
EXCP_DSI_EXTERNAL = 0x10304, /* External access disabled */ |
|
331 |
EXCP_DSI_DABR = 0x10305, /* Data address breakpoint */ |
|
332 |
/* Exeption subtypes for EXCP_ISI */ |
|
333 |
EXCP_ISI_TRANSLATE = 0x10401, /* Code address can't be translated */ |
|
334 |
EXCP_ISI_NOTSUP = 0x10402, /* Access type not supported */ |
|
335 |
EXCP_ISI_PROT = 0x10403, /* Memory protection violation */ |
|
336 |
EXCP_ISI_GUARD = 0x10404, /* Fetch into guarded memory */ |
|
337 |
/* Exeption subtypes for EXCP_ALIGN */ |
|
338 |
EXCP_ALIGN_FP = 0x10601, /* FP alignment exception */ |
|
339 |
EXCP_ALIGN_LST = 0x10602, /* Unaligned memory load/store */ |
|
340 |
EXCP_ALIGN_LE = 0x10603, /* Unaligned little-endian access */ |
|
341 |
EXCP_ALIGN_PROT = 0x10604, /* Access cross protection boundary */ |
|
342 |
EXCP_ALIGN_BAT = 0x10605, /* Access cross a BAT/seg boundary */ |
|
343 |
EXCP_ALIGN_CACHE = 0x10606, /* Impossible dcbz access */ |
|
344 |
/* Exeption subtypes for EXCP_PROGRAM */ |
|
345 |
/* FP exceptions */ |
|
346 |
EXCP_FP_OX = 0x10701, /* FP overflow */ |
|
347 |
EXCP_FP_UX = 0x10702, /* FP underflow */ |
|
348 |
EXCP_FP_ZX = 0x10703, /* FP divide by zero */ |
|
349 |
EXCP_FP_XX = 0x10704, /* FP inexact */ |
|
350 |
EXCP_FP_VXNAN = 0x10705, /* FP invalid SNaN op */ |
|
351 |
EXCP_FP_VXISI = 0x10706, /* FP invalid infinite substraction */ |
|
352 |
EXCP_FP_VXIDI = 0x10707, /* FP invalid infinite divide */ |
|
353 |
EXCP_FP_VXZDZ = 0x10708, /* FP invalid zero divide */ |
|
354 |
EXCP_FP_VXIMZ = 0x10709, /* FP invalid infinite * zero */ |
|
355 |
EXCP_FP_VXVC = 0x1070A, /* FP invalid compare */ |
|
356 |
EXCP_FP_VXSOFT = 0x1070B, /* FP invalid operation */ |
|
357 |
EXCP_FP_VXSQRT = 0x1070C, /* FP invalid square root */ |
|
358 |
EXCP_FP_VXCVI = 0x1070D, /* FP invalid integer conversion */ |
|
359 |
/* Invalid instruction */ |
|
360 |
EXCP_INVAL_INVAL = 0x10711, /* Invalid instruction */ |
|
361 |
EXCP_INVAL_LSWX = 0x10712, /* Invalid lswx instruction */ |
|
362 |
EXCP_INVAL_SPR = 0x10713, /* Invalid SPR access */ |
|
363 |
EXCP_INVAL_FP = 0x10714, /* Unimplemented mandatory fp instr */ |
|
364 |
#endif |
|
365 |
EXCP_INVAL = 0x70, /* Invalid instruction */ |
|
366 |
/* Privileged instruction */ |
|
367 |
EXCP_PRIV = 0x71, /* Privileged instruction */ |
|
368 |
/* Trap */ |
|
369 |
EXCP_TRAP = 0x72, /* Trap */ |
|
370 |
/* Special cases where we want to stop translation */ |
|
371 |
EXCP_MTMSR = 0x103, /* mtmsr instruction: */ |
|
372 |
/* may change privilege level */ |
|
373 |
EXCP_BRANCH = 0x104, /* branch instruction */ |
|
374 |
}; |
|
375 |
|
|
376 |
/* |
|
377 |
* We need to put in some extra aux table entries to tell glibc what |
|
378 |
* the cache block size is, so it can use the dcbz instruction safely. |
|
379 |
*/ |
|
380 |
#define AT_DCACHEBSIZE 19 |
|
381 |
#define AT_ICACHEBSIZE 20 |
|
382 |
#define AT_UCACHEBSIZE 21 |
|
383 |
/* A special ignored type value for PPC, for glibc compatibility. */ |
|
384 |
#define AT_IGNOREPPC 22 |
|
385 |
/* |
|
386 |
* The requirements here are: |
|
387 |
* - keep the final alignment of sp (sp & 0xf) |
|
388 |
* - make sure the 32-bit value at the first 16 byte aligned position of |
|
389 |
* AUXV is greater than 16 for glibc compatibility. |
|
390 |
* AT_IGNOREPPC is used for that. |
|
391 |
* - for compatibility with glibc ARCH_DLINFO must always be defined on PPC, |
|
392 |
* even if DLINFO_ARCH_ITEMS goes to zero or is undefined. |
|
393 |
*/ |
|
394 |
#define DLINFO_ARCH_ITEMS 3 |
|
395 |
#define ARCH_DLINFO \ |
|
396 |
do { \ |
|
397 |
/* \ |
|
398 |
* Now handle glibc compatibility. \ |
|
399 |
*/ \ |
|
400 |
NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \ |
|
401 |
NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \ |
|
402 |
\ |
|
403 |
NEW_AUX_ENT(AT_DCACHEBSIZE, 0x20); \ |
|
404 |
NEW_AUX_ENT(AT_ICACHEBSIZE, 0x20); \ |
|
405 |
NEW_AUX_ENT(AT_UCACHEBSIZE, 0); \ |
|
406 |
} while (0) |
|
407 |
#endif /* !defined (__CPU_PPC_H__) */ |
b/target-ppc/exec.h | ||
---|---|---|
1 |
/* |
|
2 |
* PPC emulation definitions for qemu. |
|
3 |
* |
|
4 |
* Copyright (c) 2003 Jocelyn Mayer |
|
5 |
* |
|
6 |
* This library is free software; you can redistribute it and/or |
|
7 |
* modify it under the terms of the GNU Lesser General Public |
|
8 |
* License as published by the Free Software Foundation; either |
|
9 |
* version 2 of the License, or (at your option) any later version. |
|
10 |
* |
|
11 |
* This library is distributed in the hope that it will be useful, |
|
12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
|
14 |
* Lesser General Public License for more details. |
|
15 |
* |
|
16 |
* You should have received a copy of the GNU Lesser General Public |
|
17 |
* License along with this library; if not, write to the Free Software |
|
18 |
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
19 |
*/ |
|
20 |
#if !defined (__PPC_H__) |
|
21 |
#define __PPC_H__ |
|
22 |
|
|
23 |
#include "dyngen-exec.h" |
|
24 |
|
|
25 |
register struct CPUPPCState *env asm(AREG0); |
|
26 |
register uint32_t T0 asm(AREG1); |
|
27 |
register uint32_t T1 asm(AREG2); |
|
28 |
register uint32_t T2 asm(AREG3); |
|
29 |
|
|
30 |
#define PARAM(n) ((uint32_t)PARAM##n) |
|
31 |
#define SPARAM(n) ((int32_t)PARAM##n) |
|
32 |
|
|
33 |
#define RETURN() __asm__ __volatile__(""); |
|
34 |
|
|
35 |
#include "cpu.h" |
|
36 |
#include "exec-all.h" |
|
37 |
|
|
38 |
static inline uint8_t ld8 (uint32_t EA) |
|
39 |
{ |
|
40 |
return *((uint8_t *)EA); |
|
41 |
} |
|
42 |
|
|
43 |
static inline uint16_t ld16 (uint32_t EA) |
|
44 |
{ |
|
45 |
return __be16_to_cpu(*((uint16_t *)EA)); |
|
46 |
} |
|
47 |
|
|
48 |
static inline uint16_t ld16r (uint32_t EA) |
|
49 |
{ |
|
50 |
return __le16_to_cpu(*((uint16_t *)EA)); |
|
51 |
} |
|
52 |
|
|
53 |
static inline uint32_t ld32 (uint32_t EA) |
|
54 |
{ |
|
55 |
return __be32_to_cpu(*((uint32_t *)EA)); |
|
56 |
} |
|
57 |
|
|
58 |
static inline uint32_t ld32r (uint32_t EA) |
|
59 |
{ |
|
60 |
return __le32_to_cpu(*((uint32_t *)EA)); |
|
61 |
} |
|
62 |
|
|
63 |
static inline uint64_t ld64 (uint32_t EA) |
|
64 |
{ |
|
65 |
return __be64_to_cpu(*((uint64_t *)EA)); |
|
66 |
} |
|
67 |
|
|
68 |
static inline uint64_t ld64r (uint32_t EA) |
|
69 |
{ |
|
70 |
return __le64_to_cpu(*((uint64_t *)EA)); |
|
71 |
} |
|
72 |
|
|
73 |
static inline void st8 (uint32_t EA, uint8_t data) |
|
74 |
{ |
|
75 |
*((uint8_t *)EA) = data; |
|
76 |
} |
|
77 |
|
|
78 |
static inline void st16 (uint32_t EA, uint16_t data) |
|
79 |
{ |
|
80 |
*((uint16_t *)EA) = __cpu_to_be16(data); |
|
81 |
} |
|
82 |
|
|
83 |
static inline void st16r (uint32_t EA, uint16_t data) |
|
84 |
{ |
|
85 |
*((uint16_t *)EA) = __cpu_to_le16(data); |
|
86 |
} |
|
87 |
|
|
88 |
static inline void st32 (uint32_t EA, uint32_t data) |
|
89 |
{ |
|
90 |
*((uint32_t *)EA) = __cpu_to_be32(data); |
|
91 |
} |
|
92 |
|
|
93 |
static inline void st32r (uint32_t EA, uint32_t data) |
|
94 |
{ |
|
95 |
*((uint32_t *)EA) = __cpu_to_le32(data); |
|
96 |
} |
|
97 |
|
|
98 |
static inline void st64 (uint32_t EA, uint64_t data) |
|
99 |
{ |
|
100 |
*((uint64_t *)EA) = __cpu_to_be64(data); |
|
101 |
} |
|
102 |
|
|
103 |
static inline void st64r (uint32_t EA, uint64_t data) |
|
104 |
{ |
|
105 |
*((uint64_t *)EA) = __cpu_to_le64(data); |
|
106 |
} |
|
107 |
|
|
108 |
static inline void set_CRn(int n, uint8_t value) |
|
109 |
{ |
|
110 |
env->crf[n] = value; |
|
111 |
} |
|
112 |
|
|
113 |
static inline void set_carry (void) |
|
114 |
{ |
|
115 |
xer_ca = 1; |
|
116 |
} |
|
117 |
|
|
118 |
static inline void reset_carry (void) |
|
119 |
{ |
|
120 |
xer_ca = 0; |
|
121 |
} |
|
122 |
|
|
123 |
static inline void set_overflow (void) |
|
124 |
{ |
|
125 |
xer_so = 1; |
|
126 |
xer_ov = 1; |
|
127 |
} |
|
128 |
|
|
129 |
static inline void reset_overflow (void) |
|
130 |
{ |
|
131 |
xer_ov = 0; |
|
132 |
} |
|
133 |
|
|
134 |
static inline uint32_t rotl (uint32_t i, int n) |
|
135 |
{ |
|
136 |
return ((i << n) | (i >> (32 - n))); |
|
137 |
} |
|
138 |
|
|
139 |
void raise_exception (int exception_index); |
|
140 |
void raise_exception_err (int exception_index, int error_code); |
|
141 |
|
|
142 |
uint32_t do_load_cr (void); |
|
143 |
void do_store_cr (uint32_t crn, uint32_t value); |
|
144 |
uint32_t do_load_xer (void); |
|
145 |
void do_store_xer (uint32_t value); |
|
146 |
uint32_t do_load_msr (void); |
|
147 |
void do_store_msr (uint32_t msr_value); |
|
148 |
uint32_t do_load_fpscr (void); |
|
149 |
void do_store_fpscr (uint8_t mask, uint32_t fp); |
|
150 |
|
|
151 |
int32_t do_sraw(int32_t Ta, uint32_t Tb); |
|
152 |
void do_lmw (int reg, uint32_t src); |
|
153 |
void do_stmw (int reg, uint32_t dest); |
|
154 |
void do_lsw (uint32_t reg, int count, uint32_t src); |
|
155 |
void do_stsw (uint32_t reg, int count, uint32_t dest); |
|
156 |
|
|
157 |
#endif /* !defined (__PPC_H__) */ |
b/target-ppc/helper.c | ||
---|---|---|
1 |
/* |
|
2 |
* PPC emulation helpers for qemu. |
|
3 |
* |
|
4 |
* Copyright (c) 2003 Jocelyn Mayer |
|
5 |
* |
|
6 |
* This library is free software; you can redistribute it and/or |
|
7 |
* modify it under the terms of the GNU Lesser General Public |
|
8 |
* License as published by the Free Software Foundation; either |
|
9 |
* version 2 of the License, or (at your option) any later version. |
|
10 |
* |
|
11 |
* This library is distributed in the hope that it will be useful, |
|
12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
|
14 |
* Lesser General Public License for more details. |
|
15 |
* |
|
16 |
* You should have received a copy of the GNU Lesser General Public |
|
17 |
* License along with this library; if not, write to the Free Software |
|
18 |
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
19 |
*/ |
|
20 |
#include "exec.h" |
|
21 |
|
|
22 |
extern FILE *logfile; |
|
23 |
|
|
24 |
void cpu_loop_exit(void) |
|
25 |
{ |
|
26 |
longjmp(env->jmp_env, 1); |
|
27 |
} |
|
28 |
|
|
29 |
/* shortcuts to generate exceptions */ |
|
30 |
void raise_exception_err (int exception_index, int error_code) |
|
31 |
{ |
|
32 |
env->exception_index = exception_index; |
|
33 |
env->error_code = error_code; |
|
34 |
|
|
35 |
cpu_loop_exit(); |
|
36 |
} |
|
37 |
|
|
38 |
void raise_exception (int exception_index) |
|
39 |
{ |
|
40 |
env->exception_index = exception_index; |
|
41 |
env->error_code = 0; |
|
42 |
|
|
43 |
cpu_loop_exit(); |
|
44 |
} |
|
45 |
|
|
46 |
/* Helpers for "fat" micro operations */ |
|
47 |
uint32_t do_load_cr (void) |
|
48 |
{ |
|
49 |
return (env->crf[0] << 28) | |
|
50 |
(env->crf[1] << 24) | |
|
51 |
(env->crf[2] << 20) | |
|
52 |
(env->crf[3] << 16) | |
|
53 |
(env->crf[4] << 12) | |
|
54 |
(env->crf[5] << 8) | |
|
55 |
(env->crf[6] << 4) | |
|
56 |
(env->crf[7] << 0); |
|
57 |
} |
|
58 |
|
|
59 |
void do_store_cr (uint32_t crn, uint32_t value) |
|
60 |
{ |
|
61 |
int i, sh; |
|
62 |
|
|
63 |
for (i = 0, sh = 7; i < 8; i++, sh --) { |
|
64 |
if (crn & (1 << sh)) |
|
65 |
env->crf[i] = (value >> (sh * 4)) & 0xF; |
|
66 |
} |
|
67 |
} |
|
68 |
|
|
69 |
uint32_t do_load_xer (void) |
|
70 |
{ |
|
71 |
return (xer_so << XER_SO) | |
|
72 |
(xer_ov << XER_OV) | |
|
73 |
(xer_ca << XER_CA) | |
|
74 |
(xer_bc << XER_BC); |
|
75 |
} |
|
76 |
|
|
77 |
void do_store_xer (uint32_t value) |
|
78 |
{ |
|
79 |
xer_so = (value >> XER_SO) & 0x01; |
|
80 |
xer_ov = (value >> XER_OV) & 0x01; |
|
81 |
xer_ca = (value >> XER_CA) & 0x01; |
|
82 |
xer_bc = (value >> XER_BC) & 0x1f; |
|
83 |
} |
|
84 |
|
|
85 |
uint32_t do_load_msr (void) |
|
86 |
{ |
|
87 |
return (msr_pow << MSR_POW) | |
|
88 |
(msr_ile << MSR_ILE) | |
|
89 |
(msr_ee << MSR_EE) | |
|
90 |
(msr_pr << MSR_PR) | |
|
91 |
(msr_fp << MSR_FP) | |
|
92 |
(msr_me << MSR_ME) | |
|
93 |
(msr_fe0 << MSR_FE0) | |
|
94 |
(msr_se << MSR_SE) | |
|
95 |
(msr_be << MSR_BE) | |
|
96 |
(msr_fe1 << MSR_FE1) | |
|
97 |
(msr_ip << MSR_IP) | |
|
98 |
(msr_ir << MSR_IR) | |
|
99 |
(msr_dr << MSR_DR) | |
|
100 |
(msr_ri << MSR_RI) | |
|
101 |
(msr_le << MSR_LE); |
|
102 |
} |
|
103 |
|
|
104 |
void do_store_msr (uint32_t msr_value) |
|
105 |
{ |
|
106 |
msr_pow = (msr_value >> MSR_POW) & 0x03; |
|
107 |
msr_ile = (msr_value >> MSR_ILE) & 0x01; |
|
108 |
msr_ee = (msr_value >> MSR_EE) & 0x01; |
|
109 |
msr_pr = (msr_value >> MSR_PR) & 0x01; |
|
110 |
msr_fp = (msr_value >> MSR_FP) & 0x01; |
|
111 |
msr_me = (msr_value >> MSR_ME) & 0x01; |
|
112 |
msr_fe0 = (msr_value >> MSR_FE0) & 0x01; |
|
113 |
msr_se = (msr_value >> MSR_SE) & 0x01; |
|
114 |
msr_be = (msr_value >> MSR_BE) & 0x01; |
|
115 |
msr_fe1 = (msr_value >> MSR_FE1) & 0x01; |
|
116 |
msr_ip = (msr_value >> MSR_IP) & 0x01; |
|
117 |
msr_ir = (msr_value >> MSR_IR) & 0x01; |
|
118 |
msr_dr = (msr_value >> MSR_DR) & 0x01; |
|
119 |
msr_ri = (msr_value >> MSR_RI) & 0x01; |
|
120 |
msr_le = (msr_value >> MSR_LE) & 0x01; |
|
121 |
} |
|
122 |
|
|
123 |
/* The 32 MSB of the target fpr are undefined. They'll be zero... */ |
|
124 |
uint32_t do_load_fpscr (void) |
|
125 |
{ |
|
126 |
return (fpscr_fx << FPSCR_FX) | |
|
127 |
(fpscr_fex << FPSCR_FEX) | |
|
128 |
(fpscr_vx << FPSCR_VX) | |
|
129 |
(fpscr_ox << FPSCR_OX) | |
|
130 |
(fpscr_ux << FPSCR_UX) | |
|
131 |
(fpscr_zx << FPSCR_ZX) | |
|
132 |
(fpscr_xx << FPSCR_XX) | |
|
133 |
(fpscr_vsxnan << FPSCR_VXSNAN) | |
|
134 |
(fpscr_vxisi << FPSCR_VXISI) | |
|
135 |
(fpscr_vxidi << FPSCR_VXIDI) | |
|
136 |
(fpscr_vxzdz << FPSCR_VXZDZ) | |
|
137 |
(fpscr_vximz << FPSCR_VXIMZ) | |
|
138 |
(fpscr_fr << FPSCR_FR) | |
|
139 |
(fpscr_fi << FPSCR_FI) | |
|
140 |
(fpscr_fprf << FPSCR_FPRF) | |
|
141 |
(fpscr_vxsoft << FPSCR_VXSOFT) | |
|
142 |
(fpscr_vxsqrt << FPSCR_VXSQRT) | |
|
143 |
(fpscr_oe << FPSCR_OE) | |
|
144 |
(fpscr_ue << FPSCR_UE) | |
|
145 |
(fpscr_ze << FPSCR_ZE) | |
|
146 |
(fpscr_xe << FPSCR_XE) | |
|
147 |
(fpscr_ni << FPSCR_NI) | |
|
148 |
(fpscr_rn << FPSCR_RN); |
|
149 |
} |
|
150 |
|
|
151 |
/* We keep only 32 bits of input... */ |
|
152 |
/* For now, this is COMPLETELY BUGGY ! */ |
|
153 |
void do_store_fpscr (uint8_t mask, uint32_t fp) |
|
154 |
{ |
|
155 |
int i; |
|
156 |
|
|
157 |
for (i = 0; i < 7; i++) { |
|
158 |
if ((mask & (1 << i)) == 0) |
|
159 |
fp &= ~(0xf << (4 * i)); |
|
160 |
} |
|
161 |
if ((mask & 80) != 0) |
|
162 |
fpscr_fx = (fp >> FPSCR_FX) & 0x01; |
|
163 |
fpscr_fex = (fp >> FPSCR_FEX) & 0x01; |
|
164 |
fpscr_vx = (fp >> FPSCR_VX) & 0x01; |
|
165 |
fpscr_ox = (fp >> FPSCR_OX) & 0x01; |
|
166 |
fpscr_ux = (fp >> FPSCR_UX) & 0x01; |
|
167 |
fpscr_zx = (fp >> FPSCR_ZX) & 0x01; |
|
168 |
fpscr_xx = (fp >> FPSCR_XX) & 0x01; |
|
169 |
fpscr_vsxnan = (fp >> FPSCR_VXSNAN) & 0x01; |
|
170 |
fpscr_vxisi = (fp >> FPSCR_VXISI) & 0x01; |
|
171 |
fpscr_vxidi = (fp >> FPSCR_VXIDI) & 0x01; |
|
172 |
fpscr_vxzdz = (fp >> FPSCR_VXZDZ) & 0x01; |
|
173 |
fpscr_vximz = (fp >> FPSCR_VXIMZ) & 0x01; |
|
174 |
fpscr_fr = (fp >> FPSCR_FR) & 0x01; |
|
175 |
fpscr_fi = (fp >> FPSCR_FI) & 0x01; |
|
176 |
fpscr_fprf = (fp >> FPSCR_FPRF) & 0x1F; |
|
177 |
fpscr_vxsoft = (fp >> FPSCR_VXSOFT) & 0x01; |
|
178 |
fpscr_vxsqrt = (fp >> FPSCR_VXSQRT) & 0x01; |
|
179 |
fpscr_oe = (fp >> FPSCR_OE) & 0x01; |
|
180 |
fpscr_ue = (fp >> FPSCR_UE) & 0x01; |
|
181 |
fpscr_ze = (fp >> FPSCR_ZE) & 0x01; |
|
182 |
fpscr_xe = (fp >> FPSCR_XE) & 0x01; |
|
183 |
fpscr_ni = (fp >> FPSCR_NI) & 0x01; |
|
184 |
fpscr_rn = (fp >> FPSCR_RN) & 0x03; |
|
185 |
} |
|
186 |
|
|
187 |
int32_t do_sraw(int32_t value, uint32_t shift) |
|
188 |
{ |
|
189 |
int32_t ret; |
|
190 |
|
|
191 |
xer_ca = 0; |
|
192 |
if (shift & 0x20) { |
|
193 |
ret = (-1) * ((uint32_t)value >> 31); |
|
194 |
if (ret < 0) |
|
195 |
xer_ca = 1; |
|
196 |
} else { |
|
197 |
ret = value >> (shift & 0x1f); |
|
198 |
if (ret < 0 && (value & ((1 << shift) - 1)) != 0) |
|
199 |
xer_ca = 1; |
|
200 |
} |
|
201 |
|
|
202 |
return ret; |
|
203 |
} |
|
204 |
|
|
205 |
void do_lmw (int reg, uint32_t src) |
|
206 |
{ |
|
207 |
for (; reg <= 31; reg++, src += 4) |
|
208 |
ugpr(reg) = ld32(src); |
|
209 |
} |
|
210 |
|
|
211 |
void do_stmw (int reg, uint32_t dest) |
|
212 |
{ |
|
213 |
for (; reg <= 31; reg++, dest += 4) |
|
214 |
st32(dest, ugpr(reg)); |
|
215 |
} |
|
216 |
|
|
217 |
void do_lsw (uint32_t reg, int count, uint32_t src) |
|
218 |
{ |
|
219 |
uint32_t tmp; |
|
220 |
int sh; |
|
221 |
|
|
222 |
for (; count > 3; count -= 4, src += 4) { |
|
223 |
if (reg == 32) |
|
224 |
reg = 0; |
|
225 |
ugpr(reg++) = ld32(src); |
|
226 |
} |
|
227 |
if (count > 0) { |
|
228 |
for (sh = 24, tmp = 0; count > 0; count--, src++, sh -= 8) { |
|
229 |
if (reg == 32) |
|
230 |
reg = 0; |
|
231 |
tmp |= ld8(src) << sh; |
|
232 |
if (sh == 0) { |
|
233 |
sh = 32; |
|
234 |
ugpr(reg++) = tmp; |
|
235 |
tmp = 0; |
|
236 |
} |
|
237 |
} |
|
238 |
ugpr(reg) = tmp; |
|
239 |
} |
|
240 |
} |
|
241 |
|
|
242 |
void do_stsw (uint32_t reg, int count, uint32_t dest) |
|
243 |
{ |
|
244 |
int sh; |
|
245 |
|
|
246 |
for (; count > 3; count -= 4, dest += 4) { |
|
247 |
if (reg == 32) |
|
248 |
reg = 0; |
|
249 |
st32(dest, ugpr(reg++)); |
|
250 |
} |
|
251 |
if (count > 0) { |
|
252 |
for (sh = 24; count > 0; count--, dest++, sh -= 8) { |
|
253 |
if (reg == 32) |
|
254 |
reg = 0; |
|
255 |
st8(dest, (ugpr(reg) >> sh) & 0xFF); |
|
256 |
if (sh == 0) { |
|
257 |
sh = 32; |
|
258 |
reg++; |
|
259 |
} |
|
260 |
} |
|
261 |
} |
|
262 |
} |
b/target-ppc/op.c | ||
---|---|---|
1 |
/* |
|
2 |
* PPC emulation micro-operations for qemu. |
|
3 |
* |
|
4 |
* Copyright (c) 2003 Jocelyn Mayer |
|
5 |
* |
|
6 |
* This library is free software; you can redistribute it and/or |
|
7 |
* modify it under the terms of the GNU Lesser General Public |
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* License as published by the Free Software Foundation; either |
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* version 2 of the License, or (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public |
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* License along with this library; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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*/ |
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|
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#include "config.h" |
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#include "exec.h" |
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|
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#define regs (env) |
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extern uint32_t __a; |
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extern uint32_t __b; |
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extern uint32_t __c; |
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extern uint32_t __d; |
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extern uint32_t __e; |
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extern uint32_t __f; |
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#define Ts0 (int32_t)T0 |
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#define Ts1 (int32_t)T1 |
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#define Ts2 (int32_t)T2 |
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|
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#include "op-multi.c" |
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|
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#define PPC_OP(name) void op_##name(void) |
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|
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/* PPC state maintenance operations */ |
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/* set_Rc0 */ |
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PPC_OP(set_Rc0) |
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{ |
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uint32_t tmp; |
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|
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if (Ts0 < 0) { |
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tmp = 0x08; |
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} else if (Ts0 > 0) { |
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tmp = 0x04; |
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} else { |
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tmp = 0x02; |
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} |
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set_CRn(0, tmp); |
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RETURN(); |
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} |
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|
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PPC_OP(set_Rc0_ov) |
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{ |
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uint32_t tmp; |
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|
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if (Ts0 < 0) { |
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tmp = 0x08; |
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} else if (Ts0 > 0) { |
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tmp = 0x04; |
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} else { |
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tmp = 0x02; |
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} |
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tmp |= xer_ov; |
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set_CRn(0, tmp); |
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RETURN(); |
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} |
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|
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/* reset_Rc0 */ |
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PPC_OP(reset_Rc0) |
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{ |
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set_CRn(0, 0x02 | xer_ov); |
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RETURN(); |
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} |
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|
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/* set_Rc0_1 */ |
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PPC_OP(set_Rc0_1) |
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{ |
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set_CRn(0, 0x04 | xer_ov); |
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RETURN(); |
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} |
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|
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PPC_OP(set_T0) |
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{ |
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T0 = PARAM(1); |
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RETURN(); |
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} |
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|
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PPC_OP(set_T1) |
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{ |
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T1 = PARAM(1); |
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RETURN(); |
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} |
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|
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PPC_OP(set_T2) |
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{ |
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T2 = PARAM(1); |
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RETURN(); |
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} |
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|
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/* Update time base */ |
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PPC_OP(update_tb) |
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{ |
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T0 = regs->spr[SPR_ENCODE(268)]; |
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T1 = T0; |
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T0 += PARAM(1); |
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if (T0 < T1) { |
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T1 = regs->spr[SPR_ENCODE(269)] + 1; |
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regs->spr[SPR_ENCODE(269)] = T1; |
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} |
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regs->spr[SPR_ENCODE(268)] = T0; |
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RETURN(); |
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} |
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|
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PPC_OP(raise_exception) |
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{ |
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raise_exception(PARAM(1)); |
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RETURN(); |
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} |
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|
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PPC_OP(exit_tb) |
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{ |
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EXIT_TB(); |
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} |
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|
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PPC_OP(load_cr) |
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{ |
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T0 = do_load_cr(); |
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RETURN(); |
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} |
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|
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PPC_OP(store_cr) |
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{ |
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do_store_cr(PARAM(1), T0); |
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RETURN(); |
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} |
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|
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PPC_OP(load_xer_cr) |
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{ |
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T0 = (xer_so << 3) | (xer_ov << 2) | (xer_ca << 1); |
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RETURN(); |
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} |
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|
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PPC_OP(clear_xer_cr) |
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{ |
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xer_so = 0; |
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xer_ov = 0; |
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xer_ca = 0; |
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RETURN(); |
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} |
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|
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PPC_OP(load_xer_bc) |
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{ |
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T0 = xer_bc; |
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RETURN(); |
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} |
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160 |
|
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PPC_OP(load_xer) |
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{ |
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T0 = do_load_xer(); |
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RETURN(); |
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} |
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|
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PPC_OP(store_xer) |
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{ |
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do_store_xer(T0); |
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RETURN(); |
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} |
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|
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PPC_OP(load_msr) |
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{ |
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T0 = do_load_msr(); |
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RETURN(); |
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} |
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|
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PPC_OP(store_msr) |
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{ |
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do_store_msr(T0); |
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RETURN(); |
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} |
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|
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PPC_OP(load_lr) |
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{ |
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regs->LR = PARAM(1); |
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RETURN(); |
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} |
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190 |
|
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/* Set reservation */ |
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PPC_OP(set_reservation) |
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{ |
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regs->reserve = T1 & ~0x03; |
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RETURN(); |
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} |
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197 |
|
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/* Reset reservation */ |
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PPC_OP(reset_reservation) |
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{ |
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regs->reserve = 0; |
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RETURN(); |
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} |
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|
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/* crf operations */ |
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PPC_OP(getbit_T0) |
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{ |
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T0 = (T0 >> PARAM(1)) & 1; |
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RETURN(); |
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} |
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211 |
|
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PPC_OP(getbit_T1) |
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{ |
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T1 = (T1 >> PARAM(1)) & 1; |
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RETURN(); |
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} |
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217 |
|
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PPC_OP(setcrfbit) |
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{ |
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T1 = (T1 & PARAM(1)) | (T0 << PARAM(2)); |
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RETURN(); |
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} |
|
223 |
|
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/* Branch */ |
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225 |
#define __PPC_OP_B(name, target) \ |
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PPC_OP(name) \ |
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{ \ |
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regs->nip = (target); \ |
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RETURN(); \ |
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} |
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231 |
|
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#define __PPC_OP_BL(name, target) \ |
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PPC_OP(name) \ |
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{ \ |
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regs->LR = PARAM(1); \ |
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regs->nip = (target); \ |
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RETURN(); \ |
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} |
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239 |
|
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#define PPC_OP_B(name, target) \ |
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__PPC_OP_B(name, target); \ |
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242 |
__PPC_OP_BL(name##l, target) |
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243 |
|
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