Revision 79c4f6b0 target-i386/op_helper.c

b/target-i386/op_helper.c
3133 3133 
    case MSR_MTRRdefType:
3134 3134 
        env->mtrr_deftype = val;
3135 3135 
        break;
3136 
    case MSR_MCG_STATUS:
3137 
        env->mcg_status = val;
3138 
        break;
3139 
    case MSR_MCG_CTL:
3140 
        if ((env->mcg_cap & MCG_CTL_P)
3141 
            && (val == 0 || val == ~(uint64_t)0))
3142 
            env->mcg_ctl = val;
3143 
        break;
3136 3144 
    default:
3145 
        if ((uint32_t)ECX >= MSR_MC0_CTL
3146 
            && (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
3147 
            uint32_t offset = (uint32_t)ECX - MSR_MC0_CTL;
3148 
            if ((offset & 0x3) != 0
3149 
                || (val == 0 || val == ~(uint64_t)0))
3150 
                env->mce_banks[offset] = val;
3151 
            break;
3152 
        }
3137 3153 
        /* XXX: exception ? */
3138 3154 
        break;
3139 3155 
    }
......
3252 3268 
            /* XXX: exception ? */
3253 3269 
            val = 0;
3254 3270 
        break;
3271 
    case MSR_MCG_CAP:
3272 
        val = env->mcg_cap;
3273 
        break;
3274 
    case MSR_MCG_CTL:
3275 
        if (env->mcg_cap & MCG_CTL_P)
3276 
            val = env->mcg_ctl;
3277 
        else
3278 
            val = 0;
3279 
        break;
3280 
    case MSR_MCG_STATUS:
3281 
        val = env->mcg_status;
3282 
        break;
3255 3283 
    default:
3284 
        if ((uint32_t)ECX >= MSR_MC0_CTL
3285 
            && (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
3286 
            uint32_t offset = (uint32_t)ECX - MSR_MC0_CTL;
3287 
            val = env->mce_banks[offset];
3288 
            break;
3289 
        }
3256 3290 
        /* XXX: exception ? */
3257 3291 
        val = 0;
3258 3292 
        break;

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