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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "tcg.h"
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int gen_new_label(void);
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static inline void tcg_gen_op1_i32(int opc, TCGv_i32 arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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}
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static inline void tcg_gen_op1_i64(int opc, TCGv_i64 arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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}
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static inline void tcg_gen_op1i(int opc, TCGArg arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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}
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static inline void tcg_gen_op2_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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}
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static inline void tcg_gen_op2_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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}
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static inline void tcg_gen_op2i_i32(int opc, TCGv_i32 arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op2i_i64(int opc, TCGv_i64 arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op2ii(int opc, TCGArg arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op3_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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}
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static inline void tcg_gen_op3_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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}
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static inline void tcg_gen_op3i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_op3i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_ldst_op_i32(int opc, TCGv_i32 val, TCGv_ptr base,
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                                       TCGArg offset)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(val);
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    *gen_opparam_ptr++ = GET_TCGV_PTR(base);
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    *gen_opparam_ptr++ = offset;
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}
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static inline void tcg_gen_ldst_op_i64(int opc, TCGv_i64 val, TCGv_ptr base,
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                                       TCGArg offset)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_PTR(base);
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    *gen_opparam_ptr++ = offset;
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}
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static inline void tcg_gen_qemu_ldst_op_i64_i32(int opc, TCGv_i64 val, TCGv_i32 addr,
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                                                TCGArg mem_index)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_I32(addr);
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    *gen_opparam_ptr++ = mem_index;
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}
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static inline void tcg_gen_qemu_ldst_op_i64_i64(int opc, TCGv_i64 val, TCGv_i64 addr,
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                                                TCGArg mem_index)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_I64(addr);
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    *gen_opparam_ptr++ = mem_index;
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}
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static inline void tcg_gen_op4_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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}
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static inline void tcg_gen_op4_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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}
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static inline void tcg_gen_op4i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGv_i64 arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                     TCGArg arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                     TCGArg arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op5_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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}
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static inline void tcg_gen_op5_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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}
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static inline void tcg_gen_op5i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op5i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op6_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
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                                   TCGv_i32 arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg6);
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}
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static inline void tcg_gen_op6_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
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                                   TCGv_i64 arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg6);
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}
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static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                     TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5,
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                                     TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = arg5;
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    *gen_opparam_ptr++ = arg6;
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}
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static inline void tcg_gen_op6ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                     TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5,
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                                     TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = arg5;
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    *gen_opparam_ptr++ = arg6;
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}
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static inline void gen_set_label(int n)
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{
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    tcg_gen_op1i(INDEX_op_set_label, n);
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}
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static inline void tcg_gen_br(int label)
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{
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    tcg_gen_op1i(INDEX_op_br, label);
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}
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static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
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{
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    if (!TCGV_EQUAL_I32(ret, arg))
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        tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
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}
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static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
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{
327 a7812ae4 pbrook
    tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
328 c896fe29 bellard
}
329 c896fe29 bellard
330 c896fe29 bellard
/* helper calls */
331 a7812ae4 pbrook
static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
332 a7812ae4 pbrook
                                   TCGArg ret, int nargs, TCGArg *args)
333 a7812ae4 pbrook
{
334 a7812ae4 pbrook
    TCGv_ptr fn;
335 a7812ae4 pbrook
    fn = tcg_const_ptr((tcg_target_long)func);
336 a7812ae4 pbrook
    tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret,
337 a7812ae4 pbrook
                  nargs, args);
338 a7812ae4 pbrook
    tcg_temp_free_ptr(fn);
339 a7812ae4 pbrook
}
340 c896fe29 bellard
341 a7812ae4 pbrook
/* FIXME: Should this be pure?  */
342 a7812ae4 pbrook
static inline void tcg_gen_helper64(void *func, TCGv_i64 ret,
343 a7812ae4 pbrook
                                    TCGv_i64 a, TCGv_i64 b)
344 c896fe29 bellard
{
345 a7812ae4 pbrook
    TCGv_ptr fn;
346 a7812ae4 pbrook
    TCGArg args[2];
347 a7812ae4 pbrook
    fn = tcg_const_ptr((tcg_target_long)func);
348 a7812ae4 pbrook
    args[0] = GET_TCGV_I64(a);
349 a7812ae4 pbrook
    args[1] = GET_TCGV_I64(b);
350 a7812ae4 pbrook
    tcg_gen_callN(&tcg_ctx, fn, 0, 7, GET_TCGV_I64(ret), 2, args);
351 a7812ae4 pbrook
    tcg_temp_free_ptr(fn);
352 f8422f52 blueswir1
}
353 f8422f52 blueswir1
354 c896fe29 bellard
/* 32 bit ops */
355 c896fe29 bellard
356 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
357 c896fe29 bellard
{
358 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
359 c896fe29 bellard
}
360 c896fe29 bellard
361 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
362 c896fe29 bellard
{
363 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
364 c896fe29 bellard
}
365 c896fe29 bellard
366 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
367 c896fe29 bellard
{
368 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
369 c896fe29 bellard
}
370 c896fe29 bellard
371 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
372 c896fe29 bellard
{
373 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
374 c896fe29 bellard
}
375 c896fe29 bellard
376 a7812ae4 pbrook
static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
377 c896fe29 bellard
{
378 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
379 c896fe29 bellard
}
380 c896fe29 bellard
381 a7812ae4 pbrook
static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
382 c896fe29 bellard
{
383 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
384 c896fe29 bellard
}
385 c896fe29 bellard
386 a7812ae4 pbrook
static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
387 c896fe29 bellard
{
388 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
389 c896fe29 bellard
}
390 c896fe29 bellard
391 a7812ae4 pbrook
static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
392 c896fe29 bellard
{
393 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
394 c896fe29 bellard
}
395 c896fe29 bellard
396 a7812ae4 pbrook
static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
397 c896fe29 bellard
{
398 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
399 c896fe29 bellard
}
400 c896fe29 bellard
401 a7812ae4 pbrook
static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
402 c896fe29 bellard
{
403 7089442c blueswir1
    /* some cases can be optimized here */
404 7089442c blueswir1
    if (arg2 == 0) {
405 7089442c blueswir1
        tcg_gen_mov_i32(ret, arg1);
406 7089442c blueswir1
    } else {
407 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
408 e8996ee0 bellard
        tcg_gen_add_i32(ret, arg1, t0);
409 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
410 7089442c blueswir1
    }
411 c896fe29 bellard
}
412 c896fe29 bellard
413 a7812ae4 pbrook
static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
414 c896fe29 bellard
{
415 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
416 c896fe29 bellard
}
417 c896fe29 bellard
418 a7812ae4 pbrook
static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
419 0045734a aurel32
{
420 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg1);
421 0045734a aurel32
    tcg_gen_sub_i32(ret, t0, arg2);
422 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
423 0045734a aurel32
}
424 0045734a aurel32
425 a7812ae4 pbrook
static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
426 c896fe29 bellard
{
427 7089442c blueswir1
    /* some cases can be optimized here */
428 7089442c blueswir1
    if (arg2 == 0) {
429 7089442c blueswir1
        tcg_gen_mov_i32(ret, arg1);
430 7089442c blueswir1
    } else {
431 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
432 e8996ee0 bellard
        tcg_gen_sub_i32(ret, arg1, t0);
433 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
434 7089442c blueswir1
    }
435 c896fe29 bellard
}
436 c896fe29 bellard
437 a7812ae4 pbrook
static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
438 c896fe29 bellard
{
439 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
440 7fc81051 aurel32
        tcg_gen_mov_i32(ret, arg1);
441 7fc81051 aurel32
    } else {
442 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
443 7fc81051 aurel32
    }
444 c896fe29 bellard
}
445 c896fe29 bellard
446 a7812ae4 pbrook
static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
447 c896fe29 bellard
{
448 c896fe29 bellard
    /* some cases can be optimized here */
449 c896fe29 bellard
    if (arg2 == 0) {
450 c896fe29 bellard
        tcg_gen_movi_i32(ret, 0);
451 c896fe29 bellard
    } else if (arg2 == 0xffffffff) {
452 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
453 c896fe29 bellard
    } else {
454 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
455 e8996ee0 bellard
        tcg_gen_and_i32(ret, arg1, t0);
456 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
457 c896fe29 bellard
    }
458 c896fe29 bellard
}
459 c896fe29 bellard
460 a7812ae4 pbrook
static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
461 c896fe29 bellard
{
462 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
463 7fc81051 aurel32
        tcg_gen_mov_i32(ret, arg1);
464 7fc81051 aurel32
    } else {
465 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
466 7fc81051 aurel32
    }
467 c896fe29 bellard
}
468 c896fe29 bellard
469 a7812ae4 pbrook
static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
470 c896fe29 bellard
{
471 c896fe29 bellard
    /* some cases can be optimized here */
472 c896fe29 bellard
    if (arg2 == 0xffffffff) {
473 7089442c blueswir1
        tcg_gen_movi_i32(ret, 0xffffffff);
474 c896fe29 bellard
    } else if (arg2 == 0) {
475 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
476 c896fe29 bellard
    } else {
477 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
478 e8996ee0 bellard
        tcg_gen_or_i32(ret, arg1, t0);
479 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
480 c896fe29 bellard
    }
481 c896fe29 bellard
}
482 c896fe29 bellard
483 a7812ae4 pbrook
static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
484 c896fe29 bellard
{
485 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
486 7fc81051 aurel32
        tcg_gen_movi_i32(ret, 0);
487 7fc81051 aurel32
    } else {
488 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
489 7fc81051 aurel32
    }
490 c896fe29 bellard
}
491 c896fe29 bellard
492 a7812ae4 pbrook
static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
493 c896fe29 bellard
{
494 c896fe29 bellard
    /* some cases can be optimized here */
495 c896fe29 bellard
    if (arg2 == 0) {
496 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
497 c896fe29 bellard
    } else {
498 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
499 e8996ee0 bellard
        tcg_gen_xor_i32(ret, arg1, t0);
500 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
501 c896fe29 bellard
    }
502 c896fe29 bellard
}
503 c896fe29 bellard
504 a7812ae4 pbrook
static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
505 c896fe29 bellard
{
506 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
507 c896fe29 bellard
}
508 c896fe29 bellard
509 a7812ae4 pbrook
static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
510 c896fe29 bellard
{
511 34151a20 bellard
    if (arg2 == 0) {
512 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
513 34151a20 bellard
    } else {
514 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
515 e8996ee0 bellard
        tcg_gen_shl_i32(ret, arg1, t0);
516 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
517 34151a20 bellard
    }
518 c896fe29 bellard
}
519 c896fe29 bellard
520 a7812ae4 pbrook
static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
521 c896fe29 bellard
{
522 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
523 c896fe29 bellard
}
524 c896fe29 bellard
525 a7812ae4 pbrook
static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
526 c896fe29 bellard
{
527 34151a20 bellard
    if (arg2 == 0) {
528 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
529 34151a20 bellard
    } else {
530 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
531 e8996ee0 bellard
        tcg_gen_shr_i32(ret, arg1, t0);
532 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
533 34151a20 bellard
    }
534 c896fe29 bellard
}
535 c896fe29 bellard
536 a7812ae4 pbrook
static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
537 c896fe29 bellard
{
538 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
539 c896fe29 bellard
}
540 c896fe29 bellard
541 a7812ae4 pbrook
static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
542 c896fe29 bellard
{
543 34151a20 bellard
    if (arg2 == 0) {
544 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
545 34151a20 bellard
    } else {
546 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
547 e8996ee0 bellard
        tcg_gen_sar_i32(ret, arg1, t0);
548 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
549 34151a20 bellard
    }
550 c896fe29 bellard
}
551 c896fe29 bellard
552 a7812ae4 pbrook
static inline void tcg_gen_brcond_i32(int cond, TCGv_i32 arg1, TCGv_i32 arg2,
553 c896fe29 bellard
                                      int label_index)
554 c896fe29 bellard
{
555 a7812ae4 pbrook
    tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
556 c896fe29 bellard
}
557 c896fe29 bellard
558 a7812ae4 pbrook
static inline void tcg_gen_brcondi_i32(int cond, TCGv_i32 arg1, int32_t arg2,
559 cb63669a pbrook
                                       int label_index)
560 cb63669a pbrook
{
561 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg2);
562 cb63669a pbrook
    tcg_gen_brcond_i32(cond, arg1, t0, label_index);
563 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
564 cb63669a pbrook
}
565 cb63669a pbrook
566 a7812ae4 pbrook
static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
567 c896fe29 bellard
{
568 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
569 c896fe29 bellard
}
570 c896fe29 bellard
571 a7812ae4 pbrook
static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
572 f730fd27 ths
{
573 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg2);
574 e8996ee0 bellard
    tcg_gen_mul_i32(ret, arg1, t0);
575 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
576 f730fd27 ths
}
577 f730fd27 ths
578 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i32
579 a7812ae4 pbrook
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
580 c896fe29 bellard
{
581 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
582 c896fe29 bellard
}
583 c896fe29 bellard
584 a7812ae4 pbrook
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
585 c896fe29 bellard
{
586 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
587 c896fe29 bellard
}
588 c896fe29 bellard
589 a7812ae4 pbrook
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
590 c896fe29 bellard
{
591 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
592 c896fe29 bellard
}
593 c896fe29 bellard
594 a7812ae4 pbrook
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
595 c896fe29 bellard
{
596 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
597 c896fe29 bellard
}
598 c896fe29 bellard
#else
599 a7812ae4 pbrook
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
600 c896fe29 bellard
{
601 a7812ae4 pbrook
    TCGv_i32 t0;
602 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
603 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
604 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
605 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
606 c896fe29 bellard
}
607 c896fe29 bellard
608 a7812ae4 pbrook
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
609 c896fe29 bellard
{
610 a7812ae4 pbrook
    TCGv_i32 t0;
611 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
612 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
613 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
614 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
615 c896fe29 bellard
}
616 c896fe29 bellard
617 a7812ae4 pbrook
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
618 c896fe29 bellard
{
619 a7812ae4 pbrook
    TCGv_i32 t0;
620 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
621 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
622 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
623 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
624 c896fe29 bellard
}
625 c896fe29 bellard
626 a7812ae4 pbrook
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
627 c896fe29 bellard
{
628 a7812ae4 pbrook
    TCGv_i32 t0;
629 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
630 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
631 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
632 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
633 c896fe29 bellard
}
634 c896fe29 bellard
#endif
635 c896fe29 bellard
636 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
637 c896fe29 bellard
638 a7812ae4 pbrook
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
639 c896fe29 bellard
{
640 fe75bcf7 aurel32
    if (!TCGV_EQUAL_I64(ret, arg)) {
641 a7812ae4 pbrook
        tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
642 4d07272d blueswir1
        tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
643 4d07272d blueswir1
    }
644 c896fe29 bellard
}
645 c896fe29 bellard
646 a7812ae4 pbrook
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
647 c896fe29 bellard
{
648 a7812ae4 pbrook
    tcg_gen_movi_i32(TCGV_LOW(ret), arg);
649 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
650 c896fe29 bellard
}
651 c896fe29 bellard
652 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
653 a7812ae4 pbrook
                                    tcg_target_long offset)
654 c896fe29 bellard
{
655 a7812ae4 pbrook
    tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
656 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
657 c896fe29 bellard
}
658 c896fe29 bellard
659 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
660 a7812ae4 pbrook
                                    tcg_target_long offset)
661 c896fe29 bellard
{
662 a7812ae4 pbrook
    tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
663 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
664 c896fe29 bellard
}
665 c896fe29 bellard
666 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
667 a7812ae4 pbrook
                                     tcg_target_long offset)
668 c896fe29 bellard
{
669 a747723b aurel32
    tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
670 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
671 c896fe29 bellard
}
672 c896fe29 bellard
673 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
674 a7812ae4 pbrook
                                     tcg_target_long offset)
675 c896fe29 bellard
{
676 a7812ae4 pbrook
    tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
677 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
678 c896fe29 bellard
}
679 c896fe29 bellard
680 a7812ae4 pbrook
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
681 a7812ae4 pbrook
                                     tcg_target_long offset)
682 c896fe29 bellard
{
683 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
684 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
685 c896fe29 bellard
}
686 c896fe29 bellard
687 a7812ae4 pbrook
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
688 a7812ae4 pbrook
                                     tcg_target_long offset)
689 c896fe29 bellard
{
690 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
691 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
692 c896fe29 bellard
}
693 c896fe29 bellard
694 a7812ae4 pbrook
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
695 a7812ae4 pbrook
                                  tcg_target_long offset)
696 c896fe29 bellard
{
697 c896fe29 bellard
    /* since arg2 and ret have different types, they cannot be the
698 c896fe29 bellard
       same temporary */
699 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
700 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
701 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
702 c896fe29 bellard
#else
703 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
704 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
705 c896fe29 bellard
#endif
706 c896fe29 bellard
}
707 c896fe29 bellard
708 a7812ae4 pbrook
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
709 a7812ae4 pbrook
                                   tcg_target_long offset)
710 c896fe29 bellard
{
711 a7812ae4 pbrook
    tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
712 c896fe29 bellard
}
713 c896fe29 bellard
714 a7812ae4 pbrook
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
715 a7812ae4 pbrook
                                    tcg_target_long offset)
716 c896fe29 bellard
{
717 a7812ae4 pbrook
    tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
718 c896fe29 bellard
}
719 c896fe29 bellard
720 a7812ae4 pbrook
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
721 a7812ae4 pbrook
                                    tcg_target_long offset)
722 c896fe29 bellard
{
723 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
724 c896fe29 bellard
}
725 c896fe29 bellard
726 a7812ae4 pbrook
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
727 a7812ae4 pbrook
                                  tcg_target_long offset)
728 c896fe29 bellard
{
729 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
730 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
731 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
732 c896fe29 bellard
#else
733 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
734 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
735 c896fe29 bellard
#endif
736 c896fe29 bellard
}
737 c896fe29 bellard
738 a7812ae4 pbrook
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
739 c896fe29 bellard
{
740 a7812ae4 pbrook
    tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
741 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
742 a7812ae4 pbrook
                    TCGV_HIGH(arg2));
743 c896fe29 bellard
}
744 c896fe29 bellard
745 a7812ae4 pbrook
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
746 c896fe29 bellard
{
747 a7812ae4 pbrook
    tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
748 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
749 a7812ae4 pbrook
                    TCGV_HIGH(arg2));
750 c896fe29 bellard
}
751 c896fe29 bellard
752 a7812ae4 pbrook
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
753 c896fe29 bellard
{
754 a7812ae4 pbrook
    tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
755 ac56dd48 pbrook
    tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
756 c896fe29 bellard
}
757 c896fe29 bellard
758 a7812ae4 pbrook
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
759 c896fe29 bellard
{
760 e5105083 aurel32
    tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
761 e5105083 aurel32
    tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
762 c896fe29 bellard
}
763 c896fe29 bellard
764 a7812ae4 pbrook
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
765 c896fe29 bellard
{
766 e5105083 aurel32
    tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
767 e5105083 aurel32
    tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
768 c896fe29 bellard
}
769 c896fe29 bellard
770 a7812ae4 pbrook
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
771 c896fe29 bellard
{
772 a7812ae4 pbrook
    tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
773 ac56dd48 pbrook
    tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
774 c896fe29 bellard
}
775 c896fe29 bellard
776 a7812ae4 pbrook
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
777 c896fe29 bellard
{
778 e5105083 aurel32
    tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
779 e5105083 aurel32
    tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
780 c896fe29 bellard
}
781 c896fe29 bellard
782 a7812ae4 pbrook
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
783 c896fe29 bellard
{
784 a7812ae4 pbrook
    tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
785 ac56dd48 pbrook
    tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
786 c896fe29 bellard
}
787 c896fe29 bellard
788 c896fe29 bellard
/* XXX: use generic code when basic block handling is OK or CPU
789 c896fe29 bellard
   specific code (x86) */
790 a7812ae4 pbrook
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
791 c896fe29 bellard
{
792 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_shl_i64, ret, arg1, arg2);
793 c896fe29 bellard
}
794 c896fe29 bellard
795 a7812ae4 pbrook
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
796 c896fe29 bellard
{
797 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
798 c896fe29 bellard
}
799 c896fe29 bellard
800 a7812ae4 pbrook
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
801 c896fe29 bellard
{
802 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_shr_i64, ret, arg1, arg2);
803 c896fe29 bellard
}
804 c896fe29 bellard
805 a7812ae4 pbrook
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
806 c896fe29 bellard
{
807 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
808 c896fe29 bellard
}
809 c896fe29 bellard
810 a7812ae4 pbrook
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
811 c896fe29 bellard
{
812 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_sar_i64, ret, arg1, arg2);
813 c896fe29 bellard
}
814 c896fe29 bellard
815 a7812ae4 pbrook
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
816 c896fe29 bellard
{
817 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
818 c896fe29 bellard
}
819 c896fe29 bellard
820 a7812ae4 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
821 c896fe29 bellard
                                      int label_index)
822 c896fe29 bellard
{
823 a7812ae4 pbrook
    tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
824 a7812ae4 pbrook
                      TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
825 a7812ae4 pbrook
                      TCGV_HIGH(arg2), cond, label_index);
826 c896fe29 bellard
}
827 c896fe29 bellard
828 a7812ae4 pbrook
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
829 c896fe29 bellard
{
830 a7812ae4 pbrook
    TCGv_i64 t0;
831 a7812ae4 pbrook
    TCGv_i32 t1;
832 c896fe29 bellard
833 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
834 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
835 a7812ae4 pbrook
836 a7812ae4 pbrook
    tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
837 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_LOW(arg2));
838 a7812ae4 pbrook
839 a7812ae4 pbrook
    tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
840 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
841 a7812ae4 pbrook
    tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
842 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
843 a7812ae4 pbrook
844 c896fe29 bellard
    tcg_gen_mov_i64(ret, t0);
845 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
846 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
847 c896fe29 bellard
}
848 c896fe29 bellard
849 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
850 c896fe29 bellard
{
851 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2);
852 c896fe29 bellard
}
853 c896fe29 bellard
854 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
855 c896fe29 bellard
{
856 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2);
857 c896fe29 bellard
}
858 c896fe29 bellard
859 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
860 c896fe29 bellard
{
861 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2);
862 c896fe29 bellard
}
863 c896fe29 bellard
864 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
865 c896fe29 bellard
{
866 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2);
867 c896fe29 bellard
}
868 c896fe29 bellard
869 c896fe29 bellard
#else
870 c896fe29 bellard
871 a7812ae4 pbrook
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
872 c896fe29 bellard
{
873 fe75bcf7 aurel32
    if (!TCGV_EQUAL_I64(ret, arg))
874 a7812ae4 pbrook
        tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
875 c896fe29 bellard
}
876 c896fe29 bellard
877 a7812ae4 pbrook
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
878 c896fe29 bellard
{
879 a7812ae4 pbrook
    tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
880 c896fe29 bellard
}
881 c896fe29 bellard
882 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2,
883 ac56dd48 pbrook
                                    tcg_target_long offset)
884 c896fe29 bellard
{
885 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
886 c896fe29 bellard
}
887 c896fe29 bellard
888 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2,
889 ac56dd48 pbrook
                                    tcg_target_long offset)
890 c896fe29 bellard
{
891 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
892 c896fe29 bellard
}
893 c896fe29 bellard
894 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2,
895 ac56dd48 pbrook
                                     tcg_target_long offset)
896 c896fe29 bellard
{
897 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
898 c896fe29 bellard
}
899 c896fe29 bellard
900 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2,
901 ac56dd48 pbrook
                                     tcg_target_long offset)
902 c896fe29 bellard
{
903 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
904 c896fe29 bellard
}
905 c896fe29 bellard
906 a7812ae4 pbrook
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2,
907 ac56dd48 pbrook
                                     tcg_target_long offset)
908 c896fe29 bellard
{
909 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
910 c896fe29 bellard
}
911 c896fe29 bellard
912 a7812ae4 pbrook
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2,
913 ac56dd48 pbrook
                                     tcg_target_long offset)
914 c896fe29 bellard
{
915 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
916 c896fe29 bellard
}
917 c896fe29 bellard
918 a7812ae4 pbrook
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset)
919 c896fe29 bellard
{
920 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
921 c896fe29 bellard
}
922 c896fe29 bellard
923 a7812ae4 pbrook
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2,
924 ac56dd48 pbrook
                                   tcg_target_long offset)
925 c896fe29 bellard
{
926 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
927 c896fe29 bellard
}
928 c896fe29 bellard
929 a7812ae4 pbrook
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2,
930 ac56dd48 pbrook
                                    tcg_target_long offset)
931 c896fe29 bellard
{
932 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
933 c896fe29 bellard
}
934 c896fe29 bellard
935 a7812ae4 pbrook
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2,
936 ac56dd48 pbrook
                                    tcg_target_long offset)
937 c896fe29 bellard
{
938 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
939 c896fe29 bellard
}
940 c896fe29 bellard
941 a7812ae4 pbrook
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset)
942 c896fe29 bellard
{
943 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
944 c896fe29 bellard
}
945 c896fe29 bellard
946 a7812ae4 pbrook
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
947 c896fe29 bellard
{
948 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
949 c896fe29 bellard
}
950 c896fe29 bellard
951 a7812ae4 pbrook
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
952 c896fe29 bellard
{
953 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
954 c896fe29 bellard
}
955 c896fe29 bellard
956 a7812ae4 pbrook
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
957 c896fe29 bellard
{
958 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
959 7fc81051 aurel32
        tcg_gen_mov_i64(ret, arg1);
960 7fc81051 aurel32
    } else {
961 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
962 7fc81051 aurel32
    }
963 c896fe29 bellard
}
964 c896fe29 bellard
965 a7812ae4 pbrook
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
966 c896fe29 bellard
{
967 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
968 e8996ee0 bellard
    tcg_gen_and_i64(ret, arg1, t0);
969 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
970 c896fe29 bellard
}
971 c896fe29 bellard
972 a7812ae4 pbrook
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
973 c896fe29 bellard
{
974 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
975 7fc81051 aurel32
        tcg_gen_mov_i64(ret, arg1);
976 7fc81051 aurel32
    } else {
977 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
978 7fc81051 aurel32
    }
979 c896fe29 bellard
}
980 c896fe29 bellard
981 a7812ae4 pbrook
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
982 c896fe29 bellard
{
983 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
984 e8996ee0 bellard
    tcg_gen_or_i64(ret, arg1, t0);
985 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
986 c896fe29 bellard
}
987 c896fe29 bellard
988 a7812ae4 pbrook
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
989 c896fe29 bellard
{
990 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
991 7fc81051 aurel32
        tcg_gen_movi_i64(ret, 0);
992 7fc81051 aurel32
    } else {
993 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
994 7fc81051 aurel32
    }
995 c896fe29 bellard
}
996 c896fe29 bellard
997 a7812ae4 pbrook
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
998 c896fe29 bellard
{
999 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1000 e8996ee0 bellard
    tcg_gen_xor_i64(ret, arg1, t0);
1001 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1002 c896fe29 bellard
}
1003 c896fe29 bellard
1004 a7812ae4 pbrook
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1005 c896fe29 bellard
{
1006 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
1007 c896fe29 bellard
}
1008 c896fe29 bellard
1009 a7812ae4 pbrook
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1010 c896fe29 bellard
{
1011 34151a20 bellard
    if (arg2 == 0) {
1012 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1013 34151a20 bellard
    } else {
1014 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1015 e8996ee0 bellard
        tcg_gen_shl_i64(ret, arg1, t0);
1016 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1017 34151a20 bellard
    }
1018 c896fe29 bellard
}
1019 c896fe29 bellard
1020 a7812ae4 pbrook
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1021 c896fe29 bellard
{
1022 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
1023 c896fe29 bellard
}
1024 c896fe29 bellard
1025 a7812ae4 pbrook
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1026 c896fe29 bellard
{
1027 34151a20 bellard
    if (arg2 == 0) {
1028 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1029 34151a20 bellard
    } else {
1030 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1031 e8996ee0 bellard
        tcg_gen_shr_i64(ret, arg1, t0);
1032 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1033 34151a20 bellard
    }
1034 c896fe29 bellard
}
1035 c896fe29 bellard
1036 a7812ae4 pbrook
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1037 c896fe29 bellard
{
1038 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
1039 c896fe29 bellard
}
1040 c896fe29 bellard
1041 a7812ae4 pbrook
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1042 c896fe29 bellard
{
1043 34151a20 bellard
    if (arg2 == 0) {
1044 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1045 34151a20 bellard
    } else {
1046 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1047 e8996ee0 bellard
        tcg_gen_sar_i64(ret, arg1, t0);
1048 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1049 34151a20 bellard
    }
1050 c896fe29 bellard
}
1051 c896fe29 bellard
1052 a7812ae4 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
1053 c896fe29 bellard
                                      int label_index)
1054 c896fe29 bellard
{
1055 a7812ae4 pbrook
    tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1056 c896fe29 bellard
}
1057 c896fe29 bellard
1058 a7812ae4 pbrook
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1059 c896fe29 bellard
{
1060 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
1061 c896fe29 bellard
}
1062 c896fe29 bellard
1063 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i64
1064 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1065 c896fe29 bellard
{
1066 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1067 c896fe29 bellard
}
1068 c896fe29 bellard
1069 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1070 c896fe29 bellard
{
1071 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
1072 c896fe29 bellard
}
1073 c896fe29 bellard
1074 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1075 c896fe29 bellard
{
1076 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1077 c896fe29 bellard
}
1078 c896fe29 bellard
1079 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1080 c896fe29 bellard
{
1081 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
1082 c896fe29 bellard
}
1083 c896fe29 bellard
#else
1084 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1085 c896fe29 bellard
{
1086 a7812ae4 pbrook
    TCGv_i64 t0;
1087 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1088 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
1089 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1090 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1091 c896fe29 bellard
}
1092 c896fe29 bellard
1093 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1094 c896fe29 bellard
{
1095 a7812ae4 pbrook
    TCGv_i64 t0;
1096 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1097 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
1098 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1099 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1100 c896fe29 bellard
}
1101 c896fe29 bellard
1102 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1103 c896fe29 bellard
{
1104 a7812ae4 pbrook
    TCGv_i64 t0;
1105 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1106 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
1107 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1108 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1109 c896fe29 bellard
}
1110 c896fe29 bellard
1111 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1112 c896fe29 bellard
{
1113 a7812ae4 pbrook
    TCGv_i64 t0;
1114 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1115 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
1116 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1117 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1118 c896fe29 bellard
}
1119 c896fe29 bellard
#endif
1120 c896fe29 bellard
1121 c896fe29 bellard
#endif
1122 c896fe29 bellard
1123 a7812ae4 pbrook
static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1124 6359706f aurel32
{
1125 6359706f aurel32
    /* some cases can be optimized here */
1126 6359706f aurel32
    if (arg2 == 0) {
1127 6359706f aurel32
        tcg_gen_mov_i64(ret, arg1);
1128 6359706f aurel32
    } else {
1129 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1130 6359706f aurel32
        tcg_gen_add_i64(ret, arg1, t0);
1131 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1132 6359706f aurel32
    }
1133 6359706f aurel32
}
1134 6359706f aurel32
1135 a7812ae4 pbrook
static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
1136 0045734a aurel32
{
1137 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg1);
1138 0045734a aurel32
    tcg_gen_sub_i64(ret, t0, arg2);
1139 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1140 0045734a aurel32
}
1141 0045734a aurel32
1142 a7812ae4 pbrook
static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1143 6359706f aurel32
{
1144 6359706f aurel32
    /* some cases can be optimized here */
1145 6359706f aurel32
    if (arg2 == 0) {
1146 6359706f aurel32
        tcg_gen_mov_i64(ret, arg1);
1147 6359706f aurel32
    } else {
1148 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1149 6359706f aurel32
        tcg_gen_sub_i64(ret, arg1, t0);
1150 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1151 6359706f aurel32
    }
1152 6359706f aurel32
}
1153 a7812ae4 pbrook
static inline void tcg_gen_brcondi_i64(int cond, TCGv_i64 arg1, int64_t arg2,
1154 f02bb954 aurel32
                                       int label_index)
1155 f02bb954 aurel32
{
1156 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1157 f02bb954 aurel32
    tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1158 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1159 f02bb954 aurel32
}
1160 f02bb954 aurel32
1161 a7812ae4 pbrook
static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1162 f02bb954 aurel32
{
1163 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1164 f02bb954 aurel32
    tcg_gen_mul_i64(ret, arg1, t0);
1165 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1166 f02bb954 aurel32
}
1167 f02bb954 aurel32
1168 6359706f aurel32
1169 c896fe29 bellard
/***************************************/
1170 c896fe29 bellard
/* optional operations */
1171 c896fe29 bellard
1172 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
1173 c896fe29 bellard
{
1174 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i32
1175 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1176 c896fe29 bellard
#else
1177 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 24);
1178 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 24);
1179 c896fe29 bellard
#endif
1180 c896fe29 bellard
}
1181 c896fe29 bellard
1182 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
1183 c896fe29 bellard
{
1184 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i32
1185 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1186 c896fe29 bellard
#else
1187 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 16);
1188 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 16);
1189 c896fe29 bellard
#endif
1190 c896fe29 bellard
}
1191 c896fe29 bellard
1192 86831435 pbrook
/* These are currently just for convenience.
1193 86831435 pbrook
   We assume a target will recognise these automatically .  */
1194 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
1195 86831435 pbrook
{
1196 86831435 pbrook
    tcg_gen_andi_i32(ret, arg, 0xffu);
1197 86831435 pbrook
}
1198 86831435 pbrook
1199 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
1200 86831435 pbrook
{
1201 86831435 pbrook
    tcg_gen_andi_i32(ret, arg, 0xffffu);
1202 86831435 pbrook
}
1203 86831435 pbrook
1204 c896fe29 bellard
/* Note: we assume the two high bytes are set to zero */
1205 a7812ae4 pbrook
static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
1206 c896fe29 bellard
{
1207 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap16_i32
1208 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1209 c896fe29 bellard
#else
1210 dfa1a3f1 aurel32
    TCGv_i32 t0 = tcg_temp_new_i32();
1211 c896fe29 bellard
    
1212 dfa1a3f1 aurel32
    tcg_gen_ext8u_i32(t0, arg);
1213 dfa1a3f1 aurel32
    tcg_gen_shli_i32(t0, t0, 8);
1214 dfa1a3f1 aurel32
    tcg_gen_shri_i32(ret, arg, 8);
1215 dfa1a3f1 aurel32
    tcg_gen_or_i32(ret, ret, t0);
1216 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1217 c896fe29 bellard
#endif
1218 c896fe29 bellard
}
1219 c896fe29 bellard
1220 66896cb8 aurel32
static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
1221 c896fe29 bellard
{
1222 66896cb8 aurel32
#ifdef TCG_TARGET_HAS_bswap32_i32
1223 66896cb8 aurel32
    tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
1224 c896fe29 bellard
#else
1225 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1226 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1227 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1228 c896fe29 bellard
    
1229 c896fe29 bellard
    tcg_gen_shli_i32(t0, arg, 24);
1230 c896fe29 bellard
    
1231 c896fe29 bellard
    tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1232 c896fe29 bellard
    tcg_gen_shli_i32(t1, t1, 8);
1233 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
1234 c896fe29 bellard
    
1235 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 8);
1236 c896fe29 bellard
    tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1237 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
1238 c896fe29 bellard
    
1239 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 24);
1240 c896fe29 bellard
    tcg_gen_or_i32(ret, t0, t1);
1241 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1242 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1243 c896fe29 bellard
#endif
1244 c896fe29 bellard
}
1245 c896fe29 bellard
1246 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1247 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1248 c896fe29 bellard
{
1249 a7812ae4 pbrook
    tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1250 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1251 c896fe29 bellard
}
1252 c896fe29 bellard
1253 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1254 c896fe29 bellard
{
1255 a7812ae4 pbrook
    tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1256 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1257 c896fe29 bellard
}
1258 c896fe29 bellard
1259 a7812ae4 pbrook
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1260 c896fe29 bellard
{
1261 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1262 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1263 c896fe29 bellard
}
1264 c896fe29 bellard
1265 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1266 86831435 pbrook
{
1267 a7812ae4 pbrook
    tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1268 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1269 86831435 pbrook
}
1270 86831435 pbrook
1271 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1272 86831435 pbrook
{
1273 a7812ae4 pbrook
    tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1274 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1275 86831435 pbrook
}
1276 86831435 pbrook
1277 a7812ae4 pbrook
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1278 86831435 pbrook
{
1279 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1280 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1281 86831435 pbrook
}
1282 86831435 pbrook
1283 a7812ae4 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1284 c896fe29 bellard
{
1285 a7812ae4 pbrook
    tcg_gen_mov_i32(ret, TCGV_LOW(arg));
1286 c896fe29 bellard
}
1287 c896fe29 bellard
1288 a7812ae4 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1289 c896fe29 bellard
{
1290 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1291 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1292 c896fe29 bellard
}
1293 c896fe29 bellard
1294 a7812ae4 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1295 c896fe29 bellard
{
1296 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1297 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1298 c896fe29 bellard
}
1299 c896fe29 bellard
1300 9a5c57fd aurel32
/* Note: we assume the six high bytes are set to zero */
1301 9a5c57fd aurel32
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1302 9a5c57fd aurel32
{
1303 9a5c57fd aurel32
    tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1304 9a5c57fd aurel32
    tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1305 9a5c57fd aurel32
}
1306 9a5c57fd aurel32
1307 9a5c57fd aurel32
/* Note: we assume the four high bytes are set to zero */
1308 9a5c57fd aurel32
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1309 9a5c57fd aurel32
{
1310 9a5c57fd aurel32
    tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1311 9a5c57fd aurel32
    tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1312 9a5c57fd aurel32
}
1313 9a5c57fd aurel32
1314 66896cb8 aurel32
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1315 c896fe29 bellard
{
1316 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1317 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1318 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1319 c896fe29 bellard
1320 66896cb8 aurel32
    tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1321 66896cb8 aurel32
    tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
1322 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1323 ac56dd48 pbrook
    tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1324 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1325 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1326 c896fe29 bellard
}
1327 c896fe29 bellard
#else
1328 c896fe29 bellard
1329 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1330 c896fe29 bellard
{
1331 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i64
1332 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1333 c896fe29 bellard
#else
1334 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 56);
1335 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 56);
1336 c896fe29 bellard
#endif
1337 c896fe29 bellard
}
1338 c896fe29 bellard
1339 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1340 c896fe29 bellard
{
1341 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i64
1342 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1343 c896fe29 bellard
#else
1344 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 48);
1345 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 48);
1346 c896fe29 bellard
#endif
1347 c896fe29 bellard
}
1348 c896fe29 bellard
1349 a7812ae4 pbrook
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1350 c896fe29 bellard
{
1351 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext32s_i64
1352 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1353 c896fe29 bellard
#else
1354 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 32);
1355 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 32);
1356 c896fe29 bellard
#endif
1357 c896fe29 bellard
}
1358 c896fe29 bellard
1359 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1360 86831435 pbrook
{
1361 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffu);
1362 86831435 pbrook
}
1363 86831435 pbrook
1364 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1365 86831435 pbrook
{
1366 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffu);
1367 86831435 pbrook
}
1368 86831435 pbrook
1369 a7812ae4 pbrook
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1370 86831435 pbrook
{
1371 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1372 86831435 pbrook
}
1373 86831435 pbrook
1374 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1375 ac56dd48 pbrook
   registers.  This will probably break MIPS64 targets.  */
1376 a7812ae4 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1377 c896fe29 bellard
{
1378 a7812ae4 pbrook
    tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
1379 c896fe29 bellard
}
1380 c896fe29 bellard
1381 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1382 c896fe29 bellard
   registers */
1383 a7812ae4 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1384 c896fe29 bellard
{
1385 a7812ae4 pbrook
    tcg_gen_andi_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)), 0xffffffffu);
1386 c896fe29 bellard
}
1387 c896fe29 bellard
1388 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1389 c896fe29 bellard
   registers */
1390 a7812ae4 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1391 c896fe29 bellard
{
1392 a7812ae4 pbrook
    tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1393 c896fe29 bellard
}
1394 c896fe29 bellard
1395 9a5c57fd aurel32
/* Note: we assume the six high bytes are set to zero */
1396 9a5c57fd aurel32
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1397 9a5c57fd aurel32
{
1398 9a5c57fd aurel32
#ifdef TCG_TARGET_HAS_bswap16_i64
1399 9a5c57fd aurel32
    tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg);
1400 9a5c57fd aurel32
#else
1401 9a5c57fd aurel32
    TCGv_i64 t0 = tcg_temp_new_i64();
1402 9a5c57fd aurel32
1403 9a5c57fd aurel32
    tcg_gen_ext8u_i64(t0, arg);
1404 9a5c57fd aurel32
    tcg_gen_shli_i64(t0, t0, 8);
1405 9a5c57fd aurel32
    tcg_gen_shri_i64(ret, arg, 8);
1406 9a5c57fd aurel32
    tcg_gen_or_i64(ret, ret, t0);
1407 9a5c57fd aurel32
    tcg_temp_free_i64(t0);
1408 9a5c57fd aurel32
#endif
1409 9a5c57fd aurel32
}
1410 9a5c57fd aurel32
1411 9a5c57fd aurel32
/* Note: we assume the four high bytes are set to zero */
1412 9a5c57fd aurel32
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1413 9a5c57fd aurel32
{
1414 9a5c57fd aurel32
#ifdef TCG_TARGET_HAS_bswap32_i64
1415 9a5c57fd aurel32
    tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg);
1416 9a5c57fd aurel32
#else
1417 9a5c57fd aurel32
    TCGv_i64 t0, t1;
1418 9a5c57fd aurel32
    t0 = tcg_temp_new_i64();
1419 9a5c57fd aurel32
    t1 = tcg_temp_new_i64();
1420 9a5c57fd aurel32
1421 9a5c57fd aurel32
    tcg_gen_shli_i64(t0, arg, 24);
1422 9a5c57fd aurel32
    tcg_gen_ext32u_i64(t0, t0);
1423 9a5c57fd aurel32
1424 9a5c57fd aurel32
    tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1425 9a5c57fd aurel32
    tcg_gen_shli_i64(t1, t1, 8);
1426 9a5c57fd aurel32
    tcg_gen_or_i64(t0, t0, t1);
1427 9a5c57fd aurel32
1428 9a5c57fd aurel32
    tcg_gen_shri_i64(t1, arg, 8);
1429 9a5c57fd aurel32
    tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1430 9a5c57fd aurel32
    tcg_gen_or_i64(t0, t0, t1);
1431 9a5c57fd aurel32
1432 9a5c57fd aurel32
    tcg_gen_shri_i64(t1, arg, 24);
1433 9a5c57fd aurel32
    tcg_gen_or_i64(ret, t0, t1);
1434 9a5c57fd aurel32
    tcg_temp_free_i64(t0);
1435 9a5c57fd aurel32
    tcg_temp_free_i64(t1);
1436 9a5c57fd aurel32
#endif
1437 9a5c57fd aurel32
}
1438 9a5c57fd aurel32
1439 66896cb8 aurel32
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1440 c896fe29 bellard
{
1441 66896cb8 aurel32
#ifdef TCG_TARGET_HAS_bswap64_i64
1442 66896cb8 aurel32
    tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
1443 c896fe29 bellard
#else
1444 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1445 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1446 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1447 c896fe29 bellard
    
1448 c896fe29 bellard
    tcg_gen_shli_i64(t0, arg, 56);
1449 c896fe29 bellard
    
1450 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1451 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 40);
1452 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1453 c896fe29 bellard
    
1454 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1455 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 24);
1456 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1457 c896fe29 bellard
1458 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0xff000000);
1459 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 8);
1460 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1461 c896fe29 bellard
1462 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 8);
1463 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0xff000000);
1464 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1465 c896fe29 bellard
    
1466 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 24);
1467 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1468 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1469 c896fe29 bellard
1470 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 40);
1471 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1472 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1473 c896fe29 bellard
1474 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 56);
1475 c896fe29 bellard
    tcg_gen_or_i64(ret, t0, t1);
1476 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1477 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1478 c896fe29 bellard
#endif
1479 c896fe29 bellard
}
1480 c896fe29 bellard
1481 c896fe29 bellard
#endif
1482 c896fe29 bellard
1483 a7812ae4 pbrook
static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
1484 390efc54 pbrook
{
1485 390efc54 pbrook
#ifdef TCG_TARGET_HAS_neg_i32
1486 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1487 390efc54 pbrook
#else
1488 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(0);
1489 e8996ee0 bellard
    tcg_gen_sub_i32(ret, t0, arg);
1490 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1491 390efc54 pbrook
#endif
1492 390efc54 pbrook
}
1493 390efc54 pbrook
1494 a7812ae4 pbrook
static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
1495 390efc54 pbrook
{
1496 390efc54 pbrook
#ifdef TCG_TARGET_HAS_neg_i64
1497 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1498 390efc54 pbrook
#else
1499 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(0);
1500 e8996ee0 bellard
    tcg_gen_sub_i64(ret, t0, arg);
1501 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1502 390efc54 pbrook
#endif
1503 390efc54 pbrook
}
1504 390efc54 pbrook
1505 a7812ae4 pbrook
static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
1506 0b6ce4cf bellard
{
1507 d2604285 aurel32
#ifdef TCG_TARGET_HAS_not_i32
1508 d2604285 aurel32
    tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
1509 d2604285 aurel32
#else
1510 e8996ee0 bellard
    tcg_gen_xori_i32(ret, arg, -1);
1511 d2604285 aurel32
#endif
1512 0b6ce4cf bellard
}
1513 0b6ce4cf bellard
1514 a7812ae4 pbrook
static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
1515 0b6ce4cf bellard
{
1516 d2604285 aurel32
#ifdef TCG_TARGET_HAS_not_i64
1517 43e860ef aurel32
    tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
1518 d2604285 aurel32
#else
1519 e8996ee0 bellard
    tcg_gen_xori_i64(ret, arg, -1);
1520 d2604285 aurel32
#endif
1521 0b6ce4cf bellard
}
1522 5ff9d6a4 bellard
1523 a7812ae4 pbrook
static inline void tcg_gen_discard_i32(TCGv_i32 arg)
1524 5ff9d6a4 bellard
{
1525 a7812ae4 pbrook
    tcg_gen_op1_i32(INDEX_op_discard, arg);
1526 5ff9d6a4 bellard
}
1527 5ff9d6a4 bellard
1528 5ff9d6a4 bellard
#if TCG_TARGET_REG_BITS == 32
1529 a7812ae4 pbrook
static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1530 5ff9d6a4 bellard
{
1531 a7812ae4 pbrook
    tcg_gen_discard_i32(TCGV_LOW(arg));
1532 5ff9d6a4 bellard
    tcg_gen_discard_i32(TCGV_HIGH(arg));
1533 5ff9d6a4 bellard
}
1534 5ff9d6a4 bellard
#else
1535 a7812ae4 pbrook
static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1536 5ff9d6a4 bellard
{
1537 a7812ae4 pbrook
    tcg_gen_op1_i64(INDEX_op_discard, arg);
1538 5ff9d6a4 bellard
}
1539 5ff9d6a4 bellard
#endif
1540 5ff9d6a4 bellard
1541 a7812ae4 pbrook
static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high)
1542 36aa55dc pbrook
{
1543 36aa55dc pbrook
#if TCG_TARGET_REG_BITS == 32
1544 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(dest), low);
1545 36aa55dc pbrook
    tcg_gen_mov_i32(TCGV_HIGH(dest), high);
1546 36aa55dc pbrook
#else
1547 a7812ae4 pbrook
    TCGv_i64 tmp = tcg_temp_new_i64();
1548 36aa55dc pbrook
    /* This extension is only needed for type correctness.
1549 36aa55dc pbrook
       We may be able to do better given target specific information.  */
1550 36aa55dc pbrook
    tcg_gen_extu_i32_i64(tmp, high);
1551 36aa55dc pbrook
    tcg_gen_shli_i64(tmp, tmp, 32);
1552 36aa55dc pbrook
    tcg_gen_extu_i32_i64(dest, low);
1553 36aa55dc pbrook
    tcg_gen_or_i64(dest, dest, tmp);
1554 a7812ae4 pbrook
    tcg_temp_free_i64(tmp);
1555 36aa55dc pbrook
#endif
1556 36aa55dc pbrook
}
1557 36aa55dc pbrook
1558 a7812ae4 pbrook
static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high)
1559 945ca823 blueswir1
{
1560 945ca823 blueswir1
#if TCG_TARGET_REG_BITS == 32
1561 a7812ae4 pbrook
    tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high));
1562 945ca823 blueswir1
#else
1563 a7812ae4 pbrook
    TCGv_i64 tmp = tcg_temp_new_i64();
1564 88422e2e pbrook
    tcg_gen_ext32u_i64(dest, low);
1565 945ca823 blueswir1
    tcg_gen_shli_i64(tmp, high, 32);
1566 88422e2e pbrook
    tcg_gen_or_i64(dest, dest, tmp);
1567 a7812ae4 pbrook
    tcg_temp_free_i64(tmp);
1568 945ca823 blueswir1
#endif
1569 945ca823 blueswir1
}
1570 945ca823 blueswir1
1571 a7812ae4 pbrook
static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1572 f24cb33e aurel32
{
1573 a7812ae4 pbrook
    TCGv_i32 t0;
1574 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1575 f24cb33e aurel32
    tcg_gen_not_i32(t0, arg2);
1576 f24cb33e aurel32
    tcg_gen_and_i32(ret, arg1, t0);
1577 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1578 f24cb33e aurel32
}
1579 f24cb33e aurel32
1580 a7812ae4 pbrook
static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1581 f24cb33e aurel32
{
1582 a7812ae4 pbrook
    TCGv_i64 t0;
1583 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1584 f24cb33e aurel32
    tcg_gen_not_i64(t0, arg2);
1585 f24cb33e aurel32
    tcg_gen_and_i64(ret, arg1, t0);
1586 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1587 f24cb33e aurel32
}
1588 f24cb33e aurel32
1589 a7812ae4 pbrook
static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1590 f24cb33e aurel32
{
1591 7fc81051 aurel32
    tcg_gen_xor_i32(ret, arg1, arg2);
1592 7fc81051 aurel32
    tcg_gen_not_i32(ret, ret);
1593 f24cb33e aurel32
}
1594 f24cb33e aurel32
1595 a7812ae4 pbrook
static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1596 f24cb33e aurel32
{
1597 7fc81051 aurel32
    tcg_gen_xor_i64(ret, arg1, arg2);
1598 7fc81051 aurel32
    tcg_gen_not_i64(ret, ret);
1599 f24cb33e aurel32
}
1600 f24cb33e aurel32
1601 a7812ae4 pbrook
static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1602 f24cb33e aurel32
{
1603 7fc81051 aurel32
    tcg_gen_and_i32(ret, arg1, arg2);
1604 7fc81051 aurel32
    tcg_gen_not_i32(ret, ret);
1605 f24cb33e aurel32
}
1606 f24cb33e aurel32
1607 a7812ae4 pbrook
static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1608 f24cb33e aurel32
{
1609 7fc81051 aurel32
    tcg_gen_and_i64(ret, arg1, arg2);
1610 7fc81051 aurel32
    tcg_gen_not_i64(ret, ret);
1611 f24cb33e aurel32
}
1612 f24cb33e aurel32
1613 a7812ae4 pbrook
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1614 f24cb33e aurel32
{
1615 7fc81051 aurel32
    tcg_gen_or_i32(ret, arg1, arg2);
1616 7fc81051 aurel32
    tcg_gen_not_i32(ret, ret);
1617 f24cb33e aurel32
}
1618 f24cb33e aurel32
1619 a7812ae4 pbrook
static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1620 f24cb33e aurel32
{
1621 7fc81051 aurel32
    tcg_gen_or_i64(ret, arg1, arg2);
1622 7fc81051 aurel32
    tcg_gen_not_i64(ret, ret);
1623 f24cb33e aurel32
}
1624 f24cb33e aurel32
1625 a7812ae4 pbrook
static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1626 f24cb33e aurel32
{
1627 a7812ae4 pbrook
    TCGv_i32 t0;
1628 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1629 f24cb33e aurel32
    tcg_gen_not_i32(t0, arg2);
1630 f24cb33e aurel32
    tcg_gen_or_i32(ret, arg1, t0);
1631 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1632 f24cb33e aurel32
}
1633 f24cb33e aurel32
1634 a7812ae4 pbrook
static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1635 f24cb33e aurel32
{
1636 a7812ae4 pbrook
    TCGv_i64 t0;
1637 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1638 f24cb33e aurel32
    tcg_gen_not_i64(t0, arg2);
1639 f24cb33e aurel32
    tcg_gen_or_i64(ret, arg1, t0);
1640 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1641 f24cb33e aurel32
}
1642 f24cb33e aurel32
1643 a7812ae4 pbrook
static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1644 15824571 aurel32
{
1645 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i32
1646 d42f183c aurel32
    tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
1647 d42f183c aurel32
#else
1648 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1649 15824571 aurel32
1650 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1651 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1652 15824571 aurel32
    tcg_gen_shl_i32(t0, arg1, arg2);
1653 15824571 aurel32
    tcg_gen_subfi_i32(t1, 32, arg2);
1654 15824571 aurel32
    tcg_gen_shr_i32(t1, arg1, t1);
1655 15824571 aurel32
    tcg_gen_or_i32(ret, t0, t1);
1656 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1657 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1658 d42f183c aurel32
#endif
1659 15824571 aurel32
}
1660 15824571 aurel32
1661 a7812ae4 pbrook
static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1662 15824571 aurel32
{
1663 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i64
1664 d42f183c aurel32
    tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
1665 d42f183c aurel32
#else
1666 a7812ae4 pbrook
    TCGv_i64 t0, t1;
1667 15824571 aurel32
1668 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1669 a7812ae4 pbrook
    t1 = tcg_temp_new_i64();
1670 15824571 aurel32
    tcg_gen_shl_i64(t0, arg1, arg2);
1671 15824571 aurel32
    tcg_gen_subfi_i64(t1, 64, arg2);
1672 15824571 aurel32
    tcg_gen_shr_i64(t1, arg1, t1);
1673 15824571 aurel32
    tcg_gen_or_i64(ret, t0, t1);
1674 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1675 a7812ae4 pbrook
    tcg_temp_free_i64(t1);
1676 d42f183c aurel32
#endif
1677 15824571 aurel32
}
1678 15824571 aurel32
1679 a7812ae4 pbrook
static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1680 15824571 aurel32
{
1681 15824571 aurel32
    /* some cases can be optimized here */
1682 15824571 aurel32
    if (arg2 == 0) {
1683 15824571 aurel32
        tcg_gen_mov_i32(ret, arg1);
1684 15824571 aurel32
    } else {
1685 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i32
1686 d42f183c aurel32
        TCGv_i32 t0 = tcg_const_i32(arg2);
1687 d42f183c aurel32
        tcg_gen_rotl_i32(ret, arg1, t0);
1688 d42f183c aurel32
        tcg_temp_free_i32(t0);
1689 d42f183c aurel32
#else
1690 a7812ae4 pbrook
        TCGv_i32 t0, t1;
1691 a7812ae4 pbrook
        t0 = tcg_temp_new_i32();
1692 a7812ae4 pbrook
        t1 = tcg_temp_new_i32();
1693 15824571 aurel32
        tcg_gen_shli_i32(t0, arg1, arg2);
1694 15824571 aurel32
        tcg_gen_shri_i32(t1, arg1, 32 - arg2);
1695 15824571 aurel32
        tcg_gen_or_i32(ret, t0, t1);
1696 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
1697 a7812ae4 pbrook
        tcg_temp_free_i32(t1);
1698 d42f183c aurel32
#endif
1699 15824571 aurel32
    }
1700 15824571 aurel32
}
1701 15824571 aurel32
1702 a7812ae4 pbrook
static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1703 15824571 aurel32
{
1704 15824571 aurel32
    /* some cases can be optimized here */
1705 15824571 aurel32
    if (arg2 == 0) {
1706 15824571 aurel32
        tcg_gen_mov_i64(ret, arg1);
1707 15824571 aurel32
    } else {
1708 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i64
1709 d42f183c aurel32
        TCGv_i64 t0 = tcg_const_i64(arg2);
1710 d42f183c aurel32
        tcg_gen_rotl_i64(ret, arg1, t0);
1711 d42f183c aurel32
        tcg_temp_free_i64(t0);
1712 d42f183c aurel32
#else
1713 a7812ae4 pbrook
        TCGv_i64 t0, t1;
1714 a7812ae4 pbrook
        t0 = tcg_temp_new_i64();
1715 a7812ae4 pbrook
        t1 = tcg_temp_new_i64();
1716 15824571 aurel32
        tcg_gen_shli_i64(t0, arg1, arg2);
1717 15824571 aurel32
        tcg_gen_shri_i64(t1, arg1, 64 - arg2);
1718 15824571 aurel32
        tcg_gen_or_i64(ret, t0, t1);
1719 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1720 a7812ae4 pbrook
        tcg_temp_free_i64(t1);
1721 d42f183c aurel32
#endif
1722 15824571 aurel32
    }
1723 15824571 aurel32
}
1724 15824571 aurel32
1725 a7812ae4 pbrook
static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1726 15824571 aurel32
{
1727 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i32
1728 d42f183c aurel32
    tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
1729 d42f183c aurel32
#else
1730 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1731 15824571 aurel32
1732 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1733 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1734 15824571 aurel32
    tcg_gen_shr_i32(t0, arg1, arg2);
1735 15824571 aurel32
    tcg_gen_subfi_i32(t1, 32, arg2);
1736 15824571 aurel32
    tcg_gen_shl_i32(t1, arg1, t1);
1737 15824571 aurel32
    tcg_gen_or_i32(ret, t0, t1);
1738 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1739 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1740 d42f183c aurel32
#endif
1741 15824571 aurel32
}
1742 15824571 aurel32
1743 a7812ae4 pbrook
static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1744 15824571 aurel32
{
1745 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i64
1746 d42f183c aurel32
    tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
1747 d42f183c aurel32
#else
1748 a7812ae4 pbrook
    TCGv_i64 t0, t1;
1749 15824571 aurel32
1750 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1751 a7812ae4 pbrook
    t1 = tcg_temp_new_i64();
1752 15824571 aurel32
    tcg_gen_shl_i64(t0, arg1, arg2);
1753 15824571 aurel32
    tcg_gen_subfi_i64(t1, 64, arg2);
1754 15824571 aurel32
    tcg_gen_shl_i64(t1, arg1, t1);
1755 15824571 aurel32
    tcg_gen_or_i64(ret, t0, t1);
1756 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1757 a7812ae4 pbrook
    tcg_temp_free_i64(t1);
1758 d42f183c aurel32
#endif
1759 15824571 aurel32
}
1760 15824571 aurel32
1761 a7812ae4 pbrook
static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1762 15824571 aurel32
{
1763 15824571 aurel32
    /* some cases can be optimized here */
1764 15824571 aurel32
    if (arg2 == 0) {
1765 15824571 aurel32
        tcg_gen_mov_i32(ret, arg1);
1766 15824571 aurel32
    } else {
1767 15824571 aurel32
        tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
1768 15824571 aurel32
    }
1769 15824571 aurel32
}
1770 15824571 aurel32
1771 a7812ae4 pbrook
static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1772 15824571 aurel32
{
1773 15824571 aurel32
    /* some cases can be optimized here */
1774 15824571 aurel32
    if (arg2 == 0) {
1775 de3526b2 pbrook
        tcg_gen_mov_i64(ret, arg1);
1776 15824571 aurel32
    } else {
1777 15824571 aurel32
        tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
1778 15824571 aurel32
    }
1779 15824571 aurel32
}
1780 15824571 aurel32
1781 c896fe29 bellard
/***************************************/
1782 c896fe29 bellard
/* QEMU specific operations. Their type depend on the QEMU CPU
1783 c896fe29 bellard
   type. */
1784 c896fe29 bellard
#ifndef TARGET_LONG_BITS
1785 c896fe29 bellard
#error must include QEMU headers
1786 c896fe29 bellard
#endif
1787 c896fe29 bellard
1788 a7812ae4 pbrook
#if TARGET_LONG_BITS == 32
1789 a7812ae4 pbrook
#define TCGv TCGv_i32
1790 a7812ae4 pbrook
#define tcg_temp_new() tcg_temp_new_i32()
1791 a7812ae4 pbrook
#define tcg_global_reg_new tcg_global_reg_new_i32
1792 a7812ae4 pbrook
#define tcg_global_mem_new tcg_global_mem_new_i32
1793 df9247b2 aurel32
#define tcg_temp_local_new() tcg_temp_local_new_i32()
1794 a7812ae4 pbrook
#define tcg_temp_free tcg_temp_free_i32
1795 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
1796 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
1797 a7812ae4 pbrook
#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
1798 fe75bcf7 aurel32
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
1799 a7812ae4 pbrook
#else
1800 a7812ae4 pbrook
#define TCGv TCGv_i64
1801 a7812ae4 pbrook
#define tcg_temp_new() tcg_temp_new_i64()
1802 a7812ae4 pbrook
#define tcg_global_reg_new tcg_global_reg_new_i64
1803 a7812ae4 pbrook
#define tcg_global_mem_new tcg_global_mem_new_i64
1804 df9247b2 aurel32
#define tcg_temp_local_new() tcg_temp_local_new_i64()
1805 a7812ae4 pbrook
#define tcg_temp_free tcg_temp_free_i64
1806 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
1807 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
1808 a7812ae4 pbrook
#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
1809 fe75bcf7 aurel32
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
1810 a7812ae4 pbrook
#endif
1811 a7812ae4 pbrook
1812 7e4597d7 bellard
/* debug info: write the PC of the corresponding QEMU CPU instruction */
1813 7e4597d7 bellard
static inline void tcg_gen_debug_insn_start(uint64_t pc)
1814 7e4597d7 bellard
{
1815 7e4597d7 bellard
    /* XXX: must really use a 32 bit size for TCGArg in all cases */
1816 7e4597d7 bellard
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1817 bcb0126f pbrook
    tcg_gen_op2ii(INDEX_op_debug_insn_start, 
1818 bcb0126f pbrook
                  (uint32_t)(pc), (uint32_t)(pc >> 32));
1819 7e4597d7 bellard
#else
1820 7e4597d7 bellard
    tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
1821 7e4597d7 bellard
#endif
1822 7e4597d7 bellard
}
1823 7e4597d7 bellard
1824 c896fe29 bellard
static inline void tcg_gen_exit_tb(tcg_target_long val)
1825 c896fe29 bellard
{
1826 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_exit_tb, val);
1827 c896fe29 bellard
}
1828 c896fe29 bellard
1829 c896fe29 bellard
static inline void tcg_gen_goto_tb(int idx)
1830 c896fe29 bellard
{
1831 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_goto_tb, idx);
1832 c896fe29 bellard
}
1833 c896fe29 bellard
1834 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1835 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1836 c896fe29 bellard
{
1837 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1838 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1839 c896fe29 bellard
#else
1840 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
1841 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1842 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1843 c896fe29 bellard
#endif
1844 c896fe29 bellard
}
1845 c896fe29 bellard
1846 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1847 c896fe29 bellard
{
1848 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1849 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1850 c896fe29 bellard
#else
1851 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
1852 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1853 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1854 c896fe29 bellard
#endif
1855 c896fe29 bellard
}
1856 c896fe29 bellard
1857 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1858 c896fe29 bellard
{
1859 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1860 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1861 c896fe29 bellard
#else
1862 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
1863 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1864 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1865 c896fe29 bellard
#endif
1866 c896fe29 bellard
}
1867 c896fe29 bellard
1868 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1869 c896fe29 bellard
{
1870 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1871 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1872 c896fe29 bellard
#else
1873 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
1874 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1875 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1876 c896fe29 bellard
#endif
1877 c896fe29 bellard
}
1878 c896fe29 bellard
1879 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1880 c896fe29 bellard
{
1881 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1882 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1883 c896fe29 bellard
#else
1884 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
1885 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1886 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1887 c896fe29 bellard
#endif
1888 c896fe29 bellard
}
1889 c896fe29 bellard
1890 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1891 c896fe29 bellard
{
1892 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1893 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1894 c896fe29 bellard
#else
1895 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
1896 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1897 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1898 c896fe29 bellard
#endif
1899 c896fe29 bellard
}
1900 c896fe29 bellard
1901 a7812ae4 pbrook
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
1902 c896fe29 bellard
{
1903 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1904 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
1905 c896fe29 bellard
#else
1906 a7812ae4 pbrook
    tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
1907 a7812ae4 pbrook
                     TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
1908 c896fe29 bellard
#endif
1909 c896fe29 bellard
}
1910 c896fe29 bellard
1911 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1912 c896fe29 bellard
{
1913 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1914 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index);
1915 c896fe29 bellard
#else
1916 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
1917 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1918 c896fe29 bellard
#endif
1919 c896fe29 bellard
}
1920 c896fe29 bellard
1921 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1922 c896fe29 bellard
{
1923 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1924 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index);
1925 c896fe29 bellard
#else
1926 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
1927 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1928 c896fe29 bellard
#endif
1929 c896fe29 bellard
}
1930 c896fe29 bellard
1931 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1932 c896fe29 bellard
{
1933 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1934 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index);
1935 c896fe29 bellard
#else
1936 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
1937 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1938 c896fe29 bellard
#endif
1939 c896fe29 bellard
}
1940 c896fe29 bellard
1941 a7812ae4 pbrook
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
1942 c896fe29 bellard
{
1943 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1944 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
1945 a7812ae4 pbrook
                     mem_index);
1946 c896fe29 bellard
#else
1947 a7812ae4 pbrook
    tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
1948 a7812ae4 pbrook
                     TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
1949 c896fe29 bellard
#endif
1950 c896fe29 bellard
}
1951 c896fe29 bellard
1952 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i32
1953 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i32
1954 f8422f52 blueswir1
1955 c896fe29 bellard
#else /* TCG_TARGET_REG_BITS == 32 */
1956 c896fe29 bellard
1957 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1958 c896fe29 bellard
{
1959 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1960 c896fe29 bellard
}
1961 c896fe29 bellard
1962 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1963 c896fe29 bellard
{
1964 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1965 c896fe29 bellard
}
1966 c896fe29 bellard
1967 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1968 c896fe29 bellard
{
1969 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1970 c896fe29 bellard
}
1971 c896fe29 bellard
1972 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1973 c896fe29 bellard
{
1974 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1975 c896fe29 bellard
}
1976 c896fe29 bellard
1977 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1978 c896fe29 bellard
{
1979 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1980 c896fe29 bellard
}
1981 c896fe29 bellard
1982 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1983 c896fe29 bellard
{
1984 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index);
1985 c896fe29 bellard
}
1986 c896fe29 bellard
1987 a7812ae4 pbrook
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
1988 c896fe29 bellard
{
1989 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index);
1990 c896fe29 bellard
}
1991 c896fe29 bellard
1992 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1993 c896fe29 bellard
{
1994 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index);
1995 c896fe29 bellard
}
1996 c896fe29 bellard
1997 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1998 c896fe29 bellard
{
1999 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index);
2000 c896fe29 bellard
}
2001 c896fe29 bellard
2002 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2003 c896fe29 bellard
{
2004 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index);
2005 c896fe29 bellard
}
2006 c896fe29 bellard
2007 a7812ae4 pbrook
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2008 c896fe29 bellard
{
2009 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index);
2010 c896fe29 bellard
}
2011 c896fe29 bellard
2012 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i64
2013 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i64
2014 f8422f52 blueswir1
2015 c896fe29 bellard
#endif /* TCG_TARGET_REG_BITS != 32 */
2016 f8422f52 blueswir1
2017 f8422f52 blueswir1
#if TARGET_LONG_BITS == 64
2018 f8422f52 blueswir1
#define TCG_TYPE_TL TCG_TYPE_I64
2019 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i64
2020 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i64
2021 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
2022 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
2023 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
2024 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
2025 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
2026 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
2027 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i64
2028 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i64
2029 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i64
2030 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st32_i64
2031 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i64
2032 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i64
2033 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i64
2034 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i64
2035 390efc54 pbrook
#define tcg_gen_neg_tl tcg_gen_neg_i64
2036 10460c8a pbrook
#define tcg_gen_subfi_tl tcg_gen_subfi_i64
2037 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i64
2038 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i64
2039 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i64
2040 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i64
2041 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i64
2042 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i64
2043 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i64
2044 0b6ce4cf bellard
#define tcg_gen_not_tl tcg_gen_not_i64
2045 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i64
2046 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i64
2047 f8422f52 blueswir1
#define tcg_gen_shr_tl tcg_gen_shr_i64
2048 f8422f52 blueswir1
#define tcg_gen_shri_tl tcg_gen_shri_i64
2049 f8422f52 blueswir1
#define tcg_gen_sar_tl tcg_gen_sar_i64
2050 f8422f52 blueswir1
#define tcg_gen_sari_tl tcg_gen_sari_i64
2051 0cf767d6 blueswir1
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
2052 cb63669a pbrook
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
2053 f730fd27 ths
#define tcg_gen_mul_tl tcg_gen_mul_i64
2054 f730fd27 ths
#define tcg_gen_muli_tl tcg_gen_muli_i64
2055 ab36421e aurel32
#define tcg_gen_div_tl tcg_gen_div_i64
2056 ab36421e aurel32
#define tcg_gen_rem_tl tcg_gen_rem_i64
2057 864951af aurel32
#define tcg_gen_divu_tl tcg_gen_divu_i64
2058 864951af aurel32
#define tcg_gen_remu_tl tcg_gen_remu_i64
2059 a768e4b2 blueswir1
#define tcg_gen_discard_tl tcg_gen_discard_i64
2060 e429073d blueswir1
#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
2061 e429073d blueswir1
#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2062 e429073d blueswir1
#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2063 e429073d blueswir1
#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2064 e429073d blueswir1
#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2065 e429073d blueswir1
#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
2066 0b6ce4cf bellard
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2067 0b6ce4cf bellard
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2068 0b6ce4cf bellard
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2069 0b6ce4cf bellard
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2070 0b6ce4cf bellard
#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2071 0b6ce4cf bellard
#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
2072 911d79ba aurel32
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
2073 911d79ba aurel32
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
2074 911d79ba aurel32
#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
2075 945ca823 blueswir1
#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
2076 f24cb33e aurel32
#define tcg_gen_andc_tl tcg_gen_andc_i64
2077 f24cb33e aurel32
#define tcg_gen_eqv_tl tcg_gen_eqv_i64
2078 f24cb33e aurel32
#define tcg_gen_nand_tl tcg_gen_nand_i64
2079 f24cb33e aurel32
#define tcg_gen_nor_tl tcg_gen_nor_i64
2080 f24cb33e aurel32
#define tcg_gen_orc_tl tcg_gen_orc_i64
2081 15824571 aurel32
#define tcg_gen_rotl_tl tcg_gen_rotl_i64
2082 15824571 aurel32
#define tcg_gen_rotli_tl tcg_gen_rotli_i64
2083 15824571 aurel32
#define tcg_gen_rotr_tl tcg_gen_rotr_i64
2084 15824571 aurel32
#define tcg_gen_rotri_tl tcg_gen_rotri_i64
2085 a98824ac blueswir1
#define tcg_const_tl tcg_const_i64
2086 bdffd4a9 aurel32
#define tcg_const_local_tl tcg_const_local_i64
2087 f8422f52 blueswir1
#else
2088 f8422f52 blueswir1
#define TCG_TYPE_TL TCG_TYPE_I32
2089 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i32
2090 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i32
2091 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2092 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2093 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2094 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2095 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld_i32
2096 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld_i32
2097 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i32
2098 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i32
2099 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i32
2100 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st_i32
2101 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i32
2102 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i32
2103 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i32
2104 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i32
2105 390efc54 pbrook
#define tcg_gen_neg_tl tcg_gen_neg_i32
2106 0045734a aurel32
#define tcg_gen_subfi_tl tcg_gen_subfi_i32
2107 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i32
2108 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i32
2109 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i32
2110 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i32
2111 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i32
2112 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i32
2113 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i32
2114 0b6ce4cf bellard
#define tcg_gen_not_tl tcg_gen_not_i32
2115 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i32
2116 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i32
2117 f8422f52 blueswir1
#define tcg_gen_shr_tl tcg_gen_shr_i32
2118 f8422f52 blueswir1
#define tcg_gen_shri_tl tcg_gen_shri_i32
2119 f8422f52 blueswir1
#define tcg_gen_sar_tl tcg_gen_sar_i32
2120 f8422f52 blueswir1
#define tcg_gen_sari_tl tcg_gen_sari_i32
2121 0cf767d6 blueswir1
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
2122 cb63669a pbrook
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
2123 f730fd27 ths
#define tcg_gen_mul_tl tcg_gen_mul_i32
2124 f730fd27 ths
#define tcg_gen_muli_tl tcg_gen_muli_i32
2125 ab36421e aurel32
#define tcg_gen_div_tl tcg_gen_div_i32
2126 ab36421e aurel32
#define tcg_gen_rem_tl tcg_gen_rem_i32
2127 864951af aurel32
#define tcg_gen_divu_tl tcg_gen_divu_i32
2128 864951af aurel32
#define tcg_gen_remu_tl tcg_gen_remu_i32
2129 a768e4b2 blueswir1
#define tcg_gen_discard_tl tcg_gen_discard_i32
2130 e429073d blueswir1
#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2131 e429073d blueswir1
#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2132 e429073d blueswir1
#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2133 e429073d blueswir1
#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2134 e429073d blueswir1
#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2135 e429073d blueswir1
#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
2136 0b6ce4cf bellard
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2137 0b6ce4cf bellard
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2138 0b6ce4cf bellard
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2139 0b6ce4cf bellard
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2140 0b6ce4cf bellard
#define tcg_gen_ext32u_tl tcg_gen_mov_i32
2141 0b6ce4cf bellard
#define tcg_gen_ext32s_tl tcg_gen_mov_i32
2142 911d79ba aurel32
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
2143 911d79ba aurel32
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
2144 945ca823 blueswir1
#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
2145 f24cb33e aurel32
#define tcg_gen_andc_tl tcg_gen_andc_i32
2146 f24cb33e aurel32
#define tcg_gen_eqv_tl tcg_gen_eqv_i32
2147 f24cb33e aurel32
#define tcg_gen_nand_tl tcg_gen_nand_i32
2148 f24cb33e aurel32
#define tcg_gen_nor_tl tcg_gen_nor_i32
2149 f24cb33e aurel32
#define tcg_gen_orc_tl tcg_gen_orc_i32
2150 15824571 aurel32
#define tcg_gen_rotl_tl tcg_gen_rotl_i32
2151 15824571 aurel32
#define tcg_gen_rotli_tl tcg_gen_rotli_i32
2152 15824571 aurel32
#define tcg_gen_rotr_tl tcg_gen_rotr_i32
2153 15824571 aurel32
#define tcg_gen_rotri_tl tcg_gen_rotri_i32
2154 a98824ac blueswir1
#define tcg_const_tl tcg_const_i32
2155 bdffd4a9 aurel32
#define tcg_const_local_tl tcg_const_local_i32
2156 f8422f52 blueswir1
#endif
2157 6ddbc6e4 pbrook
2158 6ddbc6e4 pbrook
#if TCG_TARGET_REG_BITS == 32
2159 48d38ca5 ths
#define tcg_gen_add_ptr tcg_gen_add_i32
2160 6ddbc6e4 pbrook
#define tcg_gen_addi_ptr tcg_gen_addi_i32
2161 48d38ca5 ths
#define tcg_gen_ext_i32_ptr tcg_gen_mov_i32
2162 6ddbc6e4 pbrook
#else /* TCG_TARGET_REG_BITS == 32 */
2163 48d38ca5 ths
#define tcg_gen_add_ptr tcg_gen_add_i64
2164 6ddbc6e4 pbrook
#define tcg_gen_addi_ptr tcg_gen_addi_i64
2165 48d38ca5 ths
#define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64
2166 6ddbc6e4 pbrook
#endif /* TCG_TARGET_REG_BITS != 32 */