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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#ifndef NDEBUG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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    "%rax",
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    "%rcx",
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    "%rdx",
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    "%rbx",
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    "%rsp",
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    "%rbp",
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    "%rsi",
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    "%rdi",
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    "%r8",
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    "%r9",
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    "%r10",
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    "%r11",
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    "%r12",
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    "%r13",
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    "%r14",
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    "%r15",
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};
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#endif
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static const int tcg_target_reg_alloc_order[] = {
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    TCG_REG_RBP,
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    TCG_REG_RBX,
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    TCG_REG_R12,
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    TCG_REG_R13,
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    TCG_REG_R14,
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    TCG_REG_R15,
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    TCG_REG_R10,
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    TCG_REG_R11,
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    TCG_REG_R9,
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    TCG_REG_R8,
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    TCG_REG_RCX,
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    TCG_REG_RDX,
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    TCG_REG_RSI,
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    TCG_REG_RDI,
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    TCG_REG_RAX,
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};
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static const int tcg_target_call_iarg_regs[6] = {
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    TCG_REG_RDI,
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    TCG_REG_RSI,
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    TCG_REG_RDX,
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    TCG_REG_RCX,
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    TCG_REG_R8,
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    TCG_REG_R9,
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};
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static const int tcg_target_call_oarg_regs[2] = {
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    TCG_REG_RAX, 
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    TCG_REG_RDX 
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};
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static uint8_t *tb_ret_addr;
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static void patch_reloc(uint8_t *code_ptr, int type, 
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                        tcg_target_long value, tcg_target_long addend)
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{
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    value += addend;
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    switch(type) {
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    case R_X86_64_32:
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        if (value != (uint32_t)value)
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            tcg_abort();
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        *(uint32_t *)code_ptr = value;
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        break;
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    case R_X86_64_32S:
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        if (value != (int32_t)value)
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            tcg_abort();
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        *(uint32_t *)code_ptr = value;
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        break;
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    case R_386_PC32:
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        value -= (long)code_ptr;
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        if (value != (int32_t)value)
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            tcg_abort();
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        *(uint32_t *)code_ptr = value;
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        break;
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    default:
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        tcg_abort();
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    }
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}
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/* maximum number of register used for input function arguments */
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static inline int tcg_target_get_call_iarg_regs_count(int flags)
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{
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    return 6;
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}
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/* parse target specific constraints */
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static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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{
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    const char *ct_str;
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    ct_str = *pct_str;
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    switch(ct_str[0]) {
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    case 'a':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX);
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        break;
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    case 'b':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX);
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        break;
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    case 'c':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX);
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        break;
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    case 'd':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX);
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        break;
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    case 'S':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI);
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        break;
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    case 'D':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI);
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        break;
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    case 'q':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, 0xf);
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        break;
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    case 'r':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, 0xffff);
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        break;
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    case 'L': /* qemu_ld/st constraint */
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, 0xffff);
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI);
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI);
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        break;
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    case 'e':
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        ct->ct |= TCG_CT_CONST_S32;
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        break;
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    case 'Z':
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        ct->ct |= TCG_CT_CONST_U32;
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        break;
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    default:
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        return -1;
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    }
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    ct_str++;
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    *pct_str = ct_str;
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    return 0;
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}
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/* test if a constant matches the constraint */
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static inline int tcg_target_const_match(tcg_target_long val,
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                                         const TCGArgConstraint *arg_ct)
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{
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    int ct;
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    ct = arg_ct->ct;
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    if (ct & TCG_CT_CONST)
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        return 1;
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    else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val)
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        return 1;
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    else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val)
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        return 1;
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    else
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        return 0;
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}
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#define ARITH_ADD 0
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#define ARITH_OR  1
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#define ARITH_ADC 2
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#define ARITH_SBB 3
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#define ARITH_AND 4
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#define ARITH_SUB 5
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#define ARITH_XOR 6
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#define ARITH_CMP 7
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#define SHIFT_ROL 0
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#define SHIFT_ROR 1
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#define SHIFT_SHL 4
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#define SHIFT_SHR 5
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#define SHIFT_SAR 7
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#define JCC_JMP (-1)
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#define JCC_JO  0x0
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#define JCC_JNO 0x1
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#define JCC_JB  0x2
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#define JCC_JAE 0x3
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#define JCC_JE  0x4
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#define JCC_JNE 0x5
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#define JCC_JBE 0x6
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#define JCC_JA  0x7
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#define JCC_JS  0x8
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#define JCC_JNS 0x9
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#define JCC_JP  0xa
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#define JCC_JNP 0xb
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#define JCC_JL  0xc
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#define JCC_JGE 0xd
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#define JCC_JLE 0xe
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#define JCC_JG  0xf
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#define P_EXT   0x100 /* 0x0f opcode prefix */
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#define P_REXW  0x200 /* set rex.w = 1 */
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#define P_REXB  0x400 /* force rex use for byte registers */
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static const uint8_t tcg_cond_to_jcc[10] = {
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    [TCG_COND_EQ] = JCC_JE,
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    [TCG_COND_NE] = JCC_JNE,
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    [TCG_COND_LT] = JCC_JL,
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    [TCG_COND_GE] = JCC_JGE,
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    [TCG_COND_LE] = JCC_JLE,
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    [TCG_COND_GT] = JCC_JG,
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    [TCG_COND_LTU] = JCC_JB,
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    [TCG_COND_GEU] = JCC_JAE,
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    [TCG_COND_LEU] = JCC_JBE,
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    [TCG_COND_GTU] = JCC_JA,
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};
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static inline void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
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{
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    int rex;
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    rex = ((opc >> 6) & 0x8) | ((r >> 1) & 0x4) | 
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        ((x >> 2) & 2) | ((rm >> 3) & 1);
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    if (rex || (opc & P_REXB)) {
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        tcg_out8(s, rex | 0x40);
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    }
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    if (opc & P_EXT)
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        tcg_out8(s, 0x0f);
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    tcg_out8(s, opc & 0xff);
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}
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static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
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{
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    tcg_out_opc(s, opc, r, rm, 0);
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    tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7));
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}
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/* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
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static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, 
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                                        tcg_target_long offset)
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{
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    if (rm < 0) {
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        tcg_target_long val;
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        tcg_out_opc(s, opc, r, 0, 0);
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        val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1));
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        if (val == (int32_t)val) {
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            /* eip relative */
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            tcg_out8(s, 0x05 | ((r & 7) << 3));
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            tcg_out32(s, val);
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        } else if (offset == (int32_t)offset) {
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            tcg_out8(s, 0x04 | ((r & 7) << 3));
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            tcg_out8(s, 0x25); /* sib */
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            tcg_out32(s, offset);
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        } else {
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            tcg_abort();
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        }
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    } else if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
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        tcg_out_opc(s, opc, r, rm, 0);
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        if ((rm & 7) == TCG_REG_RSP) {
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            tcg_out8(s, 0x04 | ((r & 7) << 3));
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            tcg_out8(s, 0x24);
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        } else {
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            tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7));
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        }
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    } else if ((int8_t)offset == offset) {
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        tcg_out_opc(s, opc, r, rm, 0);
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        if ((rm & 7) == TCG_REG_RSP) {
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            tcg_out8(s, 0x44 | ((r & 7) << 3));
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            tcg_out8(s, 0x24);
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        } else {
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            tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7));
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        }
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        tcg_out8(s, offset);
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    } else {
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        tcg_out_opc(s, opc, r, rm, 0);
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        if ((rm & 7) == TCG_REG_RSP) {
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            tcg_out8(s, 0x84 | ((r & 7) << 3));
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            tcg_out8(s, 0x24);
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        } else {
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            tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7));
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        }
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        tcg_out32(s, offset);
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    }
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}
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#if defined(CONFIG_SOFTMMU)
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/* XXX: incomplete. index must be different from ESP */
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static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm, 
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                                  int index, int shift,
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                                  tcg_target_long offset)
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{
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    int mod;
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    if (rm == -1)
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        tcg_abort();
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    if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
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        mod = 0;
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    } else if (offset == (int8_t)offset) {
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        mod = 0x40;
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    } else if (offset == (int32_t)offset) {
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        mod = 0x80;
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    } else {
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        tcg_abort();
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    }
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    if (index == -1) {
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        tcg_out_opc(s, opc, r, rm, 0);
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        if ((rm & 7) == TCG_REG_RSP) {
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            tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
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            tcg_out8(s, 0x04 | (rm & 7));
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        } else {
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            tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7));
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        }
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    } else {
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        tcg_out_opc(s, opc, r, rm, index);
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        tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
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        tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7));
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    }
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    if (mod == 0x40) {
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        tcg_out8(s, offset);
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    } else if (mod == 0x80) {
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        tcg_out32(s, offset);
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    }
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}
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#endif
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static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
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{
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    tcg_out_modrm(s, 0x8b | P_REXW, ret, arg);
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}
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static inline void tcg_out_movi(TCGContext *s, TCGType type, 
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                                int ret, tcg_target_long arg)
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{
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    if (arg == 0) {
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        tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */
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    } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) {
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        tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0);
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        tcg_out32(s, arg);
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    } else if (arg == (int32_t)arg) {
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        tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret);
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        tcg_out32(s, arg);
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    } else {
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        tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0);
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        tcg_out32(s, arg);
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        tcg_out32(s, arg >> 32);
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    }
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}
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static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
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                              int arg1, tcg_target_long arg2)
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{
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    if (type == TCG_TYPE_I32)
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        tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */
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    else
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        tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */
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}
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static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
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                              int arg1, tcg_target_long arg2)
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{
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    if (type == TCG_TYPE_I32)
379 e4d5434c blueswir1
        tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */
380 e4d5434c blueswir1
    else
381 e4d5434c blueswir1
        tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */
382 c896fe29 bellard
}
383 c896fe29 bellard
384 c896fe29 bellard
static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val)
385 c896fe29 bellard
{
386 c896fe29 bellard
    if (val == (int8_t)val) {
387 c896fe29 bellard
        tcg_out_modrm(s, 0x83, c, r0);
388 c896fe29 bellard
        tcg_out8(s, val);
389 733fef0e pbrook
    } else if (c == ARITH_AND && val == 0xffu) {
390 733fef0e pbrook
        /* movzbl */
391 733fef0e pbrook
        tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, r0, r0);
392 733fef0e pbrook
    } else if (c == ARITH_AND && val == 0xffffu) {
393 733fef0e pbrook
        /* movzwl */
394 733fef0e pbrook
        tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
395 c896fe29 bellard
    } else {
396 c896fe29 bellard
        tcg_out_modrm(s, 0x81, c, r0);
397 c896fe29 bellard
        tcg_out32(s, val);
398 c896fe29 bellard
    }
399 c896fe29 bellard
}
400 c896fe29 bellard
401 c896fe29 bellard
static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
402 c896fe29 bellard
{
403 c896fe29 bellard
    if (val == (int8_t)val) {
404 c896fe29 bellard
        tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
405 c896fe29 bellard
        tcg_out8(s, val);
406 733fef0e pbrook
    } else if (c == ARITH_AND && val == 0xffu) {
407 733fef0e pbrook
        /* movzbl */
408 733fef0e pbrook
        tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, r0, r0);
409 733fef0e pbrook
    } else if (c == ARITH_AND && val == 0xffffu) {
410 733fef0e pbrook
        /* movzwl */
411 733fef0e pbrook
        tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, r0, r0);
412 733fef0e pbrook
    } else if (c == ARITH_AND && val == 0xffffffffu) {
413 733fef0e pbrook
        /* 32-bit mov zero extends */
414 733fef0e pbrook
        tcg_out_modrm(s, 0x8b, r0, r0);
415 c896fe29 bellard
    } else if (val == (int32_t)val) {
416 c896fe29 bellard
        tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
417 c896fe29 bellard
        tcg_out32(s, val);
418 c896fe29 bellard
    } else if (c == ARITH_AND && val == (uint32_t)val) {
419 c896fe29 bellard
        tcg_out_modrm(s, 0x81, c, r0);
420 c896fe29 bellard
        tcg_out32(s, val);
421 c896fe29 bellard
    } else {
422 c896fe29 bellard
        tcg_abort();
423 c896fe29 bellard
    }
424 c896fe29 bellard
}
425 c896fe29 bellard
426 8fcd3692 blueswir1
static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
427 c896fe29 bellard
{
428 c896fe29 bellard
    if (val != 0)
429 c896fe29 bellard
        tgen_arithi64(s, ARITH_ADD, reg, val);
430 c896fe29 bellard
}
431 c896fe29 bellard
432 c896fe29 bellard
static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
433 c896fe29 bellard
{
434 c896fe29 bellard
    int32_t val, val1;
435 c896fe29 bellard
    TCGLabel *l = &s->labels[label_index];
436 c896fe29 bellard
    
437 c896fe29 bellard
    if (l->has_value) {
438 c896fe29 bellard
        val = l->u.value - (tcg_target_long)s->code_ptr;
439 c896fe29 bellard
        val1 = val - 2;
440 c896fe29 bellard
        if ((int8_t)val1 == val1) {
441 c896fe29 bellard
            if (opc == -1)
442 c896fe29 bellard
                tcg_out8(s, 0xeb);
443 c896fe29 bellard
            else
444 c896fe29 bellard
                tcg_out8(s, 0x70 + opc);
445 c896fe29 bellard
            tcg_out8(s, val1);
446 c896fe29 bellard
        } else {
447 c896fe29 bellard
            if (opc == -1) {
448 c896fe29 bellard
                tcg_out8(s, 0xe9);
449 c896fe29 bellard
                tcg_out32(s, val - 5);
450 c896fe29 bellard
            } else {
451 c896fe29 bellard
                tcg_out8(s, 0x0f);
452 c896fe29 bellard
                tcg_out8(s, 0x80 + opc);
453 c896fe29 bellard
                tcg_out32(s, val - 6);
454 c896fe29 bellard
            }
455 c896fe29 bellard
        }
456 c896fe29 bellard
    } else {
457 c896fe29 bellard
        if (opc == -1) {
458 c896fe29 bellard
            tcg_out8(s, 0xe9);
459 c896fe29 bellard
        } else {
460 c896fe29 bellard
            tcg_out8(s, 0x0f);
461 c896fe29 bellard
            tcg_out8(s, 0x80 + opc);
462 c896fe29 bellard
        }
463 c896fe29 bellard
        tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
464 623e265c pbrook
        s->code_ptr += 4;
465 c896fe29 bellard
    }
466 c896fe29 bellard
}
467 c896fe29 bellard
468 c896fe29 bellard
static void tcg_out_brcond(TCGContext *s, int cond, 
469 c896fe29 bellard
                           TCGArg arg1, TCGArg arg2, int const_arg2,
470 c896fe29 bellard
                           int label_index, int rexw)
471 c896fe29 bellard
{
472 c896fe29 bellard
    if (const_arg2) {
473 c896fe29 bellard
        if (arg2 == 0) {
474 c896fe29 bellard
            /* test r, r */
475 c896fe29 bellard
            tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
476 c896fe29 bellard
        } else {
477 c896fe29 bellard
            if (rexw)
478 c896fe29 bellard
                tgen_arithi64(s, ARITH_CMP, arg1, arg2);
479 c896fe29 bellard
            else
480 c896fe29 bellard
                tgen_arithi32(s, ARITH_CMP, arg1, arg2);
481 c896fe29 bellard
        }
482 c896fe29 bellard
    } else {
483 bb210e78 bellard
        tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1);
484 c896fe29 bellard
    }
485 560f92cc bellard
    tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
486 c896fe29 bellard
}
487 c896fe29 bellard
488 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
489 c896fe29 bellard
490 79383c9c blueswir1
#include "../../softmmu_defs.h"
491 c896fe29 bellard
492 c896fe29 bellard
static void *qemu_ld_helpers[4] = {
493 c896fe29 bellard
    __ldb_mmu,
494 c896fe29 bellard
    __ldw_mmu,
495 c896fe29 bellard
    __ldl_mmu,
496 c896fe29 bellard
    __ldq_mmu,
497 c896fe29 bellard
};
498 c896fe29 bellard
499 c896fe29 bellard
static void *qemu_st_helpers[4] = {
500 c896fe29 bellard
    __stb_mmu,
501 c896fe29 bellard
    __stw_mmu,
502 c896fe29 bellard
    __stl_mmu,
503 c896fe29 bellard
    __stq_mmu,
504 c896fe29 bellard
};
505 c896fe29 bellard
#endif
506 c896fe29 bellard
507 c896fe29 bellard
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
508 c896fe29 bellard
                            int opc)
509 c896fe29 bellard
{
510 c896fe29 bellard
    int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
511 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
512 c896fe29 bellard
    uint8_t *label1_ptr, *label2_ptr;
513 c896fe29 bellard
#endif
514 c896fe29 bellard
515 c896fe29 bellard
    data_reg = *args++;
516 c896fe29 bellard
    addr_reg = *args++;
517 c896fe29 bellard
    mem_index = *args;
518 c896fe29 bellard
    s_bits = opc & 3;
519 c896fe29 bellard
520 c896fe29 bellard
    r0 = TCG_REG_RDI;
521 c896fe29 bellard
    r1 = TCG_REG_RSI;
522 c896fe29 bellard
523 c896fe29 bellard
#if TARGET_LONG_BITS == 32
524 c896fe29 bellard
    rexw = 0;
525 c896fe29 bellard
#else
526 c896fe29 bellard
    rexw = P_REXW;
527 c896fe29 bellard
#endif
528 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
529 c896fe29 bellard
    /* mov */
530 c896fe29 bellard
    tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
531 c896fe29 bellard
532 c896fe29 bellard
    /* mov */
533 c896fe29 bellard
    tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
534 c896fe29 bellard
 
535 c896fe29 bellard
    tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
536 c896fe29 bellard
    tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 
537 c896fe29 bellard
    
538 c896fe29 bellard
    tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
539 c896fe29 bellard
    tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
540 c896fe29 bellard
    
541 c896fe29 bellard
    tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
542 c896fe29 bellard
    tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
543 c896fe29 bellard
544 c896fe29 bellard
    /* lea offset(r1, env), r1 */
545 c896fe29 bellard
    tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
546 c896fe29 bellard
                          offsetof(CPUState, tlb_table[mem_index][0].addr_read));
547 c896fe29 bellard
548 c896fe29 bellard
    /* cmp 0(r1), r0 */
549 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
550 c896fe29 bellard
    
551 c896fe29 bellard
    /* mov */
552 c896fe29 bellard
    tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
553 c896fe29 bellard
    
554 c896fe29 bellard
    /* je label1 */
555 c896fe29 bellard
    tcg_out8(s, 0x70 + JCC_JE);
556 c896fe29 bellard
    label1_ptr = s->code_ptr;
557 c896fe29 bellard
    s->code_ptr++;
558 c896fe29 bellard
559 c896fe29 bellard
    /* XXX: move that code at the end of the TB */
560 c896fe29 bellard
    tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index);
561 c896fe29 bellard
    tcg_out8(s, 0xe8);
562 c896fe29 bellard
    tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] - 
563 c896fe29 bellard
              (tcg_target_long)s->code_ptr - 4);
564 c896fe29 bellard
565 c896fe29 bellard
    switch(opc) {
566 c896fe29 bellard
    case 0 | 4:
567 c896fe29 bellard
        /* movsbq */
568 c896fe29 bellard
        tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
569 c896fe29 bellard
        break;
570 c896fe29 bellard
    case 1 | 4:
571 c896fe29 bellard
        /* movswq */
572 c896fe29 bellard
        tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
573 c896fe29 bellard
        break;
574 c896fe29 bellard
    case 2 | 4:
575 c896fe29 bellard
        /* movslq */
576 c896fe29 bellard
        tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
577 c896fe29 bellard
        break;
578 c896fe29 bellard
    case 0:
579 9db3ba4d aurel32
        /* movzbq */
580 9db3ba4d aurel32
        tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
581 9db3ba4d aurel32
        break;
582 c896fe29 bellard
    case 1:
583 9db3ba4d aurel32
        /* movzwq */
584 9db3ba4d aurel32
        tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
585 9db3ba4d aurel32
        break;
586 c896fe29 bellard
    case 2:
587 c896fe29 bellard
    default:
588 c896fe29 bellard
        /* movl */
589 c896fe29 bellard
        tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
590 c896fe29 bellard
        break;
591 c896fe29 bellard
    case 3:
592 c896fe29 bellard
        tcg_out_mov(s, data_reg, TCG_REG_RAX);
593 c896fe29 bellard
        break;
594 c896fe29 bellard
    }
595 c896fe29 bellard
596 c896fe29 bellard
    /* jmp label2 */
597 c896fe29 bellard
    tcg_out8(s, 0xeb);
598 c896fe29 bellard
    label2_ptr = s->code_ptr;
599 c896fe29 bellard
    s->code_ptr++;
600 c896fe29 bellard
    
601 c896fe29 bellard
    /* label1: */
602 c896fe29 bellard
    *label1_ptr = s->code_ptr - label1_ptr - 1;
603 c896fe29 bellard
604 c896fe29 bellard
    /* add x(r1), r0 */
605 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) - 
606 c896fe29 bellard
                         offsetof(CPUTLBEntry, addr_read));
607 c896fe29 bellard
#else
608 c896fe29 bellard
    r0 = addr_reg;
609 c896fe29 bellard
#endif    
610 c896fe29 bellard
611 c896fe29 bellard
#ifdef TARGET_WORDS_BIGENDIAN
612 c896fe29 bellard
    bswap = 1;
613 c896fe29 bellard
#else
614 c896fe29 bellard
    bswap = 0;
615 c896fe29 bellard
#endif
616 c896fe29 bellard
    switch(opc) {
617 c896fe29 bellard
    case 0:
618 c896fe29 bellard
        /* movzbl */
619 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, 0);
620 c896fe29 bellard
        break;
621 c896fe29 bellard
    case 0 | 4:
622 c896fe29 bellard
        /* movsbX */
623 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, 0);
624 c896fe29 bellard
        break;
625 c896fe29 bellard
    case 1:
626 c896fe29 bellard
        /* movzwl */
627 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
628 c896fe29 bellard
        if (bswap) {
629 c896fe29 bellard
            /* rolw $8, data_reg */
630 c896fe29 bellard
            tcg_out8(s, 0x66); 
631 c896fe29 bellard
            tcg_out_modrm(s, 0xc1, 0, data_reg);
632 c896fe29 bellard
            tcg_out8(s, 8);
633 c896fe29 bellard
        }
634 c896fe29 bellard
        break;
635 c896fe29 bellard
    case 1 | 4:
636 c896fe29 bellard
        if (bswap) {
637 c896fe29 bellard
            /* movzwl */
638 c896fe29 bellard
            tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
639 c896fe29 bellard
            /* rolw $8, data_reg */
640 c896fe29 bellard
            tcg_out8(s, 0x66); 
641 c896fe29 bellard
            tcg_out_modrm(s, 0xc1, 0, data_reg);
642 c896fe29 bellard
            tcg_out8(s, 8);
643 c896fe29 bellard
644 c896fe29 bellard
            /* movswX data_reg, data_reg */
645 c896fe29 bellard
            tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
646 c896fe29 bellard
        } else {
647 c896fe29 bellard
            /* movswX */
648 c896fe29 bellard
            tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, 0);
649 c896fe29 bellard
        }
650 c896fe29 bellard
        break;
651 c896fe29 bellard
    case 2:
652 c896fe29 bellard
        /* movl (r0), data_reg */
653 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
654 c896fe29 bellard
        if (bswap) {
655 c896fe29 bellard
            /* bswap */
656 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
657 c896fe29 bellard
        }
658 c896fe29 bellard
        break;
659 c896fe29 bellard
    case 2 | 4:
660 c896fe29 bellard
        if (bswap) {
661 c896fe29 bellard
            /* movl (r0), data_reg */
662 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
663 c896fe29 bellard
            /* bswap */
664 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
665 c896fe29 bellard
            /* movslq */
666 c896fe29 bellard
            tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
667 c896fe29 bellard
        } else {
668 c896fe29 bellard
            /* movslq */
669 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, 0);
670 c896fe29 bellard
        }
671 c896fe29 bellard
        break;
672 c896fe29 bellard
    case 3:
673 c896fe29 bellard
        /* movq (r0), data_reg */
674 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, 0);
675 c896fe29 bellard
        if (bswap) {
676 c896fe29 bellard
            /* bswap */
677 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0);
678 c896fe29 bellard
        }
679 c896fe29 bellard
        break;
680 c896fe29 bellard
    default:
681 c896fe29 bellard
        tcg_abort();
682 c896fe29 bellard
    }
683 c896fe29 bellard
684 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
685 c896fe29 bellard
    /* label2: */
686 c896fe29 bellard
    *label2_ptr = s->code_ptr - label2_ptr - 1;
687 c896fe29 bellard
#endif
688 c896fe29 bellard
}
689 c896fe29 bellard
690 c896fe29 bellard
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
691 c896fe29 bellard
                            int opc)
692 c896fe29 bellard
{
693 c896fe29 bellard
    int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
694 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
695 c896fe29 bellard
    uint8_t *label1_ptr, *label2_ptr;
696 c896fe29 bellard
#endif
697 c896fe29 bellard
698 c896fe29 bellard
    data_reg = *args++;
699 c896fe29 bellard
    addr_reg = *args++;
700 c896fe29 bellard
    mem_index = *args;
701 c896fe29 bellard
702 c896fe29 bellard
    s_bits = opc;
703 c896fe29 bellard
704 c896fe29 bellard
    r0 = TCG_REG_RDI;
705 c896fe29 bellard
    r1 = TCG_REG_RSI;
706 c896fe29 bellard
707 c896fe29 bellard
#if TARGET_LONG_BITS == 32
708 c896fe29 bellard
    rexw = 0;
709 c896fe29 bellard
#else
710 c896fe29 bellard
    rexw = P_REXW;
711 c896fe29 bellard
#endif
712 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
713 c896fe29 bellard
    /* mov */
714 c896fe29 bellard
    tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
715 c896fe29 bellard
716 c896fe29 bellard
    /* mov */
717 c896fe29 bellard
    tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
718 c896fe29 bellard
 
719 c896fe29 bellard
    tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
720 c896fe29 bellard
    tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 
721 c896fe29 bellard
    
722 c896fe29 bellard
    tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
723 c896fe29 bellard
    tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
724 c896fe29 bellard
    
725 c896fe29 bellard
    tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
726 c896fe29 bellard
    tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
727 c896fe29 bellard
728 c896fe29 bellard
    /* lea offset(r1, env), r1 */
729 c896fe29 bellard
    tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
730 c896fe29 bellard
                          offsetof(CPUState, tlb_table[mem_index][0].addr_write));
731 c896fe29 bellard
732 c896fe29 bellard
    /* cmp 0(r1), r0 */
733 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
734 c896fe29 bellard
    
735 c896fe29 bellard
    /* mov */
736 c896fe29 bellard
    tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
737 c896fe29 bellard
    
738 c896fe29 bellard
    /* je label1 */
739 c896fe29 bellard
    tcg_out8(s, 0x70 + JCC_JE);
740 c896fe29 bellard
    label1_ptr = s->code_ptr;
741 c896fe29 bellard
    s->code_ptr++;
742 c896fe29 bellard
743 c896fe29 bellard
    /* XXX: move that code at the end of the TB */
744 c896fe29 bellard
    switch(opc) {
745 c896fe29 bellard
    case 0:
746 c896fe29 bellard
        /* movzbl */
747 3c3a1d20 bellard
        tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, TCG_REG_RSI, data_reg);
748 c896fe29 bellard
        break;
749 c896fe29 bellard
    case 1:
750 c896fe29 bellard
        /* movzwl */
751 c896fe29 bellard
        tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
752 c896fe29 bellard
        break;
753 c896fe29 bellard
    case 2:
754 c896fe29 bellard
        /* movl */
755 c896fe29 bellard
        tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
756 c896fe29 bellard
        break;
757 c896fe29 bellard
    default:
758 c896fe29 bellard
    case 3:
759 c896fe29 bellard
        tcg_out_mov(s, TCG_REG_RSI, data_reg);
760 c896fe29 bellard
        break;
761 c896fe29 bellard
    }
762 c896fe29 bellard
    tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
763 c896fe29 bellard
    tcg_out8(s, 0xe8);
764 c896fe29 bellard
    tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - 
765 c896fe29 bellard
              (tcg_target_long)s->code_ptr - 4);
766 c896fe29 bellard
767 c896fe29 bellard
    /* jmp label2 */
768 c896fe29 bellard
    tcg_out8(s, 0xeb);
769 c896fe29 bellard
    label2_ptr = s->code_ptr;
770 c896fe29 bellard
    s->code_ptr++;
771 c896fe29 bellard
    
772 c896fe29 bellard
    /* label1: */
773 c896fe29 bellard
    *label1_ptr = s->code_ptr - label1_ptr - 1;
774 c896fe29 bellard
775 c896fe29 bellard
    /* add x(r1), r0 */
776 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) - 
777 c896fe29 bellard
                         offsetof(CPUTLBEntry, addr_write));
778 c896fe29 bellard
#else
779 c896fe29 bellard
    r0 = addr_reg;
780 c896fe29 bellard
#endif
781 c896fe29 bellard
782 c896fe29 bellard
#ifdef TARGET_WORDS_BIGENDIAN
783 c896fe29 bellard
    bswap = 1;
784 c896fe29 bellard
#else
785 c896fe29 bellard
    bswap = 0;
786 c896fe29 bellard
#endif
787 c896fe29 bellard
    switch(opc) {
788 c896fe29 bellard
    case 0:
789 c896fe29 bellard
        /* movb */
790 3c3a1d20 bellard
        tcg_out_modrm_offset(s, 0x88 | P_REXB, data_reg, r0, 0);
791 c896fe29 bellard
        break;
792 c896fe29 bellard
    case 1:
793 c896fe29 bellard
        if (bswap) {
794 c896fe29 bellard
            tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
795 c896fe29 bellard
            tcg_out8(s, 0x66); /* rolw $8, %ecx */
796 c896fe29 bellard
            tcg_out_modrm(s, 0xc1, 0, r1);
797 c896fe29 bellard
            tcg_out8(s, 8);
798 c896fe29 bellard
            data_reg = r1;
799 c896fe29 bellard
        }
800 c896fe29 bellard
        /* movw */
801 c896fe29 bellard
        tcg_out8(s, 0x66);
802 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
803 c896fe29 bellard
        break;
804 c896fe29 bellard
    case 2:
805 c896fe29 bellard
        if (bswap) {
806 c896fe29 bellard
            tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
807 c896fe29 bellard
            /* bswap data_reg */
808 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0);
809 c896fe29 bellard
            data_reg = r1;
810 c896fe29 bellard
        }
811 c896fe29 bellard
        /* movl */
812 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
813 c896fe29 bellard
        break;
814 c896fe29 bellard
    case 3:
815 c896fe29 bellard
        if (bswap) {
816 c896fe29 bellard
            tcg_out_mov(s, r1, data_reg);
817 c896fe29 bellard
            /* bswap data_reg */
818 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0);
819 c896fe29 bellard
            data_reg = r1;
820 c896fe29 bellard
        }
821 c896fe29 bellard
        /* movq */
822 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, 0);
823 c896fe29 bellard
        break;
824 c896fe29 bellard
    default:
825 c896fe29 bellard
        tcg_abort();
826 c896fe29 bellard
    }
827 c896fe29 bellard
828 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
829 c896fe29 bellard
    /* label2: */
830 c896fe29 bellard
    *label2_ptr = s->code_ptr - label2_ptr - 1;
831 c896fe29 bellard
#endif
832 c896fe29 bellard
}
833 c896fe29 bellard
834 c896fe29 bellard
static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
835 c896fe29 bellard
                              const int *const_args)
836 c896fe29 bellard
{
837 c896fe29 bellard
    int c;
838 c896fe29 bellard
    
839 c896fe29 bellard
    switch(opc) {
840 c896fe29 bellard
    case INDEX_op_exit_tb:
841 c896fe29 bellard
        tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
842 b03cce8e bellard
        tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
843 b03cce8e bellard
        tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
844 c896fe29 bellard
        break;
845 c896fe29 bellard
    case INDEX_op_goto_tb:
846 c896fe29 bellard
        if (s->tb_jmp_offset) {
847 c896fe29 bellard
            /* direct jump method */
848 c896fe29 bellard
            tcg_out8(s, 0xe9); /* jmp im */
849 c896fe29 bellard
            s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
850 c896fe29 bellard
            tcg_out32(s, 0);
851 c896fe29 bellard
        } else {
852 c896fe29 bellard
            /* indirect jump method */
853 c896fe29 bellard
            /* jmp Ev */
854 c896fe29 bellard
            tcg_out_modrm_offset(s, 0xff, 4, -1, 
855 c896fe29 bellard
                                 (tcg_target_long)(s->tb_next + 
856 c896fe29 bellard
                                                   args[0]));
857 c896fe29 bellard
        }
858 c896fe29 bellard
        s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
859 c896fe29 bellard
        break;
860 c896fe29 bellard
    case INDEX_op_call:
861 c896fe29 bellard
        if (const_args[0]) {
862 c896fe29 bellard
            tcg_out8(s, 0xe8);
863 c896fe29 bellard
            tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
864 c896fe29 bellard
        } else {
865 c896fe29 bellard
            tcg_out_modrm(s, 0xff, 2, args[0]);
866 c896fe29 bellard
        }
867 c896fe29 bellard
        break;
868 c896fe29 bellard
    case INDEX_op_jmp:
869 c896fe29 bellard
        if (const_args[0]) {
870 c896fe29 bellard
            tcg_out8(s, 0xe9);
871 c896fe29 bellard
            tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
872 c896fe29 bellard
        } else {
873 c896fe29 bellard
            tcg_out_modrm(s, 0xff, 4, args[0]);
874 c896fe29 bellard
        }
875 c896fe29 bellard
        break;
876 c896fe29 bellard
    case INDEX_op_br:
877 c896fe29 bellard
        tcg_out_jxx(s, JCC_JMP, args[0]);
878 c896fe29 bellard
        break;
879 c896fe29 bellard
    case INDEX_op_movi_i32:
880 c896fe29 bellard
        tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
881 c896fe29 bellard
        break;
882 c896fe29 bellard
    case INDEX_op_movi_i64:
883 c896fe29 bellard
        tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
884 c896fe29 bellard
        break;
885 c896fe29 bellard
    case INDEX_op_ld8u_i32:
886 c896fe29 bellard
    case INDEX_op_ld8u_i64:
887 c896fe29 bellard
        /* movzbl */
888 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]);
889 c896fe29 bellard
        break;
890 c896fe29 bellard
    case INDEX_op_ld8s_i32:
891 c896fe29 bellard
        /* movsbl */
892 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]);
893 c896fe29 bellard
        break;
894 c896fe29 bellard
    case INDEX_op_ld8s_i64:
895 c896fe29 bellard
        /* movsbq */
896 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]);
897 c896fe29 bellard
        break;
898 c896fe29 bellard
    case INDEX_op_ld16u_i32:
899 c896fe29 bellard
    case INDEX_op_ld16u_i64:
900 c896fe29 bellard
        /* movzwl */
901 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]);
902 c896fe29 bellard
        break;
903 c896fe29 bellard
    case INDEX_op_ld16s_i32:
904 c896fe29 bellard
        /* movswl */
905 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]);
906 c896fe29 bellard
        break;
907 c896fe29 bellard
    case INDEX_op_ld16s_i64:
908 c896fe29 bellard
        /* movswq */
909 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]);
910 c896fe29 bellard
        break;
911 c896fe29 bellard
    case INDEX_op_ld_i32:
912 c896fe29 bellard
    case INDEX_op_ld32u_i64:
913 c896fe29 bellard
        /* movl */
914 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
915 c896fe29 bellard
        break;
916 c896fe29 bellard
    case INDEX_op_ld32s_i64:
917 c896fe29 bellard
        /* movslq */
918 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]);
919 c896fe29 bellard
        break;
920 c896fe29 bellard
    case INDEX_op_ld_i64:
921 c896fe29 bellard
        /* movq */
922 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]);
923 c896fe29 bellard
        break;
924 c896fe29 bellard
        
925 c896fe29 bellard
    case INDEX_op_st8_i32:
926 c896fe29 bellard
    case INDEX_op_st8_i64:
927 c896fe29 bellard
        /* movb */
928 3c3a1d20 bellard
        tcg_out_modrm_offset(s, 0x88 | P_REXB, args[0], args[1], args[2]);
929 c896fe29 bellard
        break;
930 c896fe29 bellard
    case INDEX_op_st16_i32:
931 c896fe29 bellard
    case INDEX_op_st16_i64:
932 c896fe29 bellard
        /* movw */
933 c896fe29 bellard
        tcg_out8(s, 0x66);
934 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
935 c896fe29 bellard
        break;
936 c896fe29 bellard
    case INDEX_op_st_i32:
937 c896fe29 bellard
    case INDEX_op_st32_i64:
938 c896fe29 bellard
        /* movl */
939 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
940 c896fe29 bellard
        break;
941 c896fe29 bellard
    case INDEX_op_st_i64:
942 c896fe29 bellard
        /* movq */
943 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]);
944 c896fe29 bellard
        break;
945 c896fe29 bellard
946 c896fe29 bellard
    case INDEX_op_sub_i32:
947 c896fe29 bellard
        c = ARITH_SUB;
948 c896fe29 bellard
        goto gen_arith32;
949 c896fe29 bellard
    case INDEX_op_and_i32:
950 c896fe29 bellard
        c = ARITH_AND;
951 c896fe29 bellard
        goto gen_arith32;
952 c896fe29 bellard
    case INDEX_op_or_i32:
953 c896fe29 bellard
        c = ARITH_OR;
954 c896fe29 bellard
        goto gen_arith32;
955 c896fe29 bellard
    case INDEX_op_xor_i32:
956 c896fe29 bellard
        c = ARITH_XOR;
957 c896fe29 bellard
        goto gen_arith32;
958 c896fe29 bellard
    case INDEX_op_add_i32:
959 c896fe29 bellard
        c = ARITH_ADD;
960 c896fe29 bellard
    gen_arith32:
961 c896fe29 bellard
        if (const_args[2]) {
962 c896fe29 bellard
            tgen_arithi32(s, c, args[0], args[2]);
963 c896fe29 bellard
        } else {
964 c896fe29 bellard
            tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]);
965 c896fe29 bellard
        }
966 c896fe29 bellard
        break;
967 c896fe29 bellard
968 c896fe29 bellard
    case INDEX_op_sub_i64:
969 c896fe29 bellard
        c = ARITH_SUB;
970 c896fe29 bellard
        goto gen_arith64;
971 c896fe29 bellard
    case INDEX_op_and_i64:
972 c896fe29 bellard
        c = ARITH_AND;
973 c896fe29 bellard
        goto gen_arith64;
974 c896fe29 bellard
    case INDEX_op_or_i64:
975 c896fe29 bellard
        c = ARITH_OR;
976 c896fe29 bellard
        goto gen_arith64;
977 c896fe29 bellard
    case INDEX_op_xor_i64:
978 c896fe29 bellard
        c = ARITH_XOR;
979 c896fe29 bellard
        goto gen_arith64;
980 c896fe29 bellard
    case INDEX_op_add_i64:
981 c896fe29 bellard
        c = ARITH_ADD;
982 c896fe29 bellard
    gen_arith64:
983 c896fe29 bellard
        if (const_args[2]) {
984 c896fe29 bellard
            tgen_arithi64(s, c, args[0], args[2]);
985 c896fe29 bellard
        } else {
986 c896fe29 bellard
            tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]);
987 c896fe29 bellard
        }
988 c896fe29 bellard
        break;
989 c896fe29 bellard
990 c896fe29 bellard
    case INDEX_op_mul_i32:
991 c896fe29 bellard
        if (const_args[2]) {
992 c896fe29 bellard
            int32_t val;
993 c896fe29 bellard
            val = args[2];
994 c896fe29 bellard
            if (val == (int8_t)val) {
995 c896fe29 bellard
                tcg_out_modrm(s, 0x6b, args[0], args[0]);
996 c896fe29 bellard
                tcg_out8(s, val);
997 c896fe29 bellard
            } else {
998 c896fe29 bellard
                tcg_out_modrm(s, 0x69, args[0], args[0]);
999 c896fe29 bellard
                tcg_out32(s, val);
1000 c896fe29 bellard
            }
1001 c896fe29 bellard
        } else {
1002 c896fe29 bellard
            tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]);
1003 c896fe29 bellard
        }
1004 c896fe29 bellard
        break;
1005 c896fe29 bellard
    case INDEX_op_mul_i64:
1006 c896fe29 bellard
        if (const_args[2]) {
1007 c896fe29 bellard
            int32_t val;
1008 c896fe29 bellard
            val = args[2];
1009 c896fe29 bellard
            if (val == (int8_t)val) {
1010 c896fe29 bellard
                tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]);
1011 c896fe29 bellard
                tcg_out8(s, val);
1012 c896fe29 bellard
            } else {
1013 c896fe29 bellard
                tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]);
1014 c896fe29 bellard
                tcg_out32(s, val);
1015 c896fe29 bellard
            }
1016 c896fe29 bellard
        } else {
1017 c896fe29 bellard
            tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]);
1018 c896fe29 bellard
        }
1019 c896fe29 bellard
        break;
1020 c896fe29 bellard
    case INDEX_op_div2_i32:
1021 c896fe29 bellard
        tcg_out_modrm(s, 0xf7, 7, args[4]);
1022 c896fe29 bellard
        break;
1023 c896fe29 bellard
    case INDEX_op_divu2_i32:
1024 c896fe29 bellard
        tcg_out_modrm(s, 0xf7, 6, args[4]);
1025 c896fe29 bellard
        break;
1026 c896fe29 bellard
    case INDEX_op_div2_i64:
1027 c896fe29 bellard
        tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]);
1028 c896fe29 bellard
        break;
1029 c896fe29 bellard
    case INDEX_op_divu2_i64:
1030 c896fe29 bellard
        tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]);
1031 c896fe29 bellard
        break;
1032 c896fe29 bellard
1033 c896fe29 bellard
    case INDEX_op_shl_i32:
1034 c896fe29 bellard
        c = SHIFT_SHL;
1035 c896fe29 bellard
    gen_shift32:
1036 c896fe29 bellard
        if (const_args[2]) {
1037 c896fe29 bellard
            if (args[2] == 1) {
1038 c896fe29 bellard
                tcg_out_modrm(s, 0xd1, c, args[0]);
1039 c896fe29 bellard
            } else {
1040 c896fe29 bellard
                tcg_out_modrm(s, 0xc1, c, args[0]);
1041 c896fe29 bellard
                tcg_out8(s, args[2]);
1042 c896fe29 bellard
            }
1043 c896fe29 bellard
        } else {
1044 c896fe29 bellard
            tcg_out_modrm(s, 0xd3, c, args[0]);
1045 c896fe29 bellard
        }
1046 c896fe29 bellard
        break;
1047 c896fe29 bellard
    case INDEX_op_shr_i32:
1048 c896fe29 bellard
        c = SHIFT_SHR;
1049 c896fe29 bellard
        goto gen_shift32;
1050 c896fe29 bellard
    case INDEX_op_sar_i32:
1051 c896fe29 bellard
        c = SHIFT_SAR;
1052 c896fe29 bellard
        goto gen_shift32;
1053 d42f183c aurel32
    case INDEX_op_rotl_i32:
1054 d42f183c aurel32
        c = SHIFT_ROL;
1055 d42f183c aurel32
        goto gen_shift32;
1056 d42f183c aurel32
    case INDEX_op_rotr_i32:
1057 d42f183c aurel32
        c = SHIFT_ROR;
1058 d42f183c aurel32
        goto gen_shift32;
1059 d42f183c aurel32
1060 c896fe29 bellard
    case INDEX_op_shl_i64:
1061 c896fe29 bellard
        c = SHIFT_SHL;
1062 c896fe29 bellard
    gen_shift64:
1063 c896fe29 bellard
        if (const_args[2]) {
1064 c896fe29 bellard
            if (args[2] == 1) {
1065 c896fe29 bellard
                tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]);
1066 c896fe29 bellard
            } else {
1067 c896fe29 bellard
                tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]);
1068 c896fe29 bellard
                tcg_out8(s, args[2]);
1069 c896fe29 bellard
            }
1070 c896fe29 bellard
        } else {
1071 c896fe29 bellard
            tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]);
1072 c896fe29 bellard
        }
1073 c896fe29 bellard
        break;
1074 c896fe29 bellard
    case INDEX_op_shr_i64:
1075 c896fe29 bellard
        c = SHIFT_SHR;
1076 c896fe29 bellard
        goto gen_shift64;
1077 c896fe29 bellard
    case INDEX_op_sar_i64:
1078 c896fe29 bellard
        c = SHIFT_SAR;
1079 c896fe29 bellard
        goto gen_shift64;
1080 d42f183c aurel32
    case INDEX_op_rotl_i64:
1081 d42f183c aurel32
        c = SHIFT_ROL;
1082 d42f183c aurel32
        goto gen_shift64;
1083 d42f183c aurel32
    case INDEX_op_rotr_i64:
1084 d42f183c aurel32
        c = SHIFT_ROR;
1085 d42f183c aurel32
        goto gen_shift64;
1086 d42f183c aurel32
1087 c896fe29 bellard
    case INDEX_op_brcond_i32:
1088 c896fe29 bellard
        tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], 
1089 c896fe29 bellard
                       args[3], 0);
1090 c896fe29 bellard
        break;
1091 c896fe29 bellard
    case INDEX_op_brcond_i64:
1092 c896fe29 bellard
        tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], 
1093 c896fe29 bellard
                       args[3], P_REXW);
1094 c896fe29 bellard
        break;
1095 c896fe29 bellard
1096 86dbdd40 aurel32
    case INDEX_op_bswap16_i32:
1097 86dbdd40 aurel32
    case INDEX_op_bswap16_i64:
1098 86dbdd40 aurel32
        tcg_out8(s, 0x66);
1099 86dbdd40 aurel32
        tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]);
1100 86dbdd40 aurel32
        tcg_out8(s, 8);
1101 86dbdd40 aurel32
        break;
1102 66896cb8 aurel32
    case INDEX_op_bswap32_i32:
1103 86dbdd40 aurel32
    case INDEX_op_bswap32_i64:
1104 c896fe29 bellard
        tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0);
1105 c896fe29 bellard
        break;
1106 66896cb8 aurel32
    case INDEX_op_bswap64_i64:
1107 c896fe29 bellard
        tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0);
1108 c896fe29 bellard
        break;
1109 c896fe29 bellard
1110 390efc54 pbrook
    case INDEX_op_neg_i32:
1111 390efc54 pbrook
        tcg_out_modrm(s, 0xf7, 3, args[0]);
1112 390efc54 pbrook
        break;
1113 390efc54 pbrook
    case INDEX_op_neg_i64:
1114 390efc54 pbrook
        tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]);
1115 390efc54 pbrook
        break;
1116 390efc54 pbrook
1117 d2604285 aurel32
    case INDEX_op_not_i32:
1118 d2604285 aurel32
        tcg_out_modrm(s, 0xf7, 2, args[0]);
1119 d2604285 aurel32
        break;
1120 d2604285 aurel32
    case INDEX_op_not_i64:
1121 d2604285 aurel32
        tcg_out_modrm(s, 0xf7 | P_REXW, 2, args[0]);
1122 d2604285 aurel32
        break;
1123 d2604285 aurel32
1124 b6d17150 pbrook
    case INDEX_op_ext8s_i32:
1125 b6d17150 pbrook
        tcg_out_modrm(s, 0xbe | P_EXT | P_REXB, args[0], args[1]);
1126 b6d17150 pbrook
        break;
1127 b6d17150 pbrook
    case INDEX_op_ext16s_i32:
1128 b6d17150 pbrook
        tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]);
1129 b6d17150 pbrook
        break;
1130 b6d17150 pbrook
    case INDEX_op_ext8s_i64:
1131 b6d17150 pbrook
        tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, args[0], args[1]);
1132 b6d17150 pbrook
        break;
1133 b6d17150 pbrook
    case INDEX_op_ext16s_i64:
1134 b6d17150 pbrook
        tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, args[0], args[1]);
1135 b6d17150 pbrook
        break;
1136 b6d17150 pbrook
    case INDEX_op_ext32s_i64:
1137 b6d17150 pbrook
        tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]);
1138 b6d17150 pbrook
        break;
1139 b6d17150 pbrook
1140 c896fe29 bellard
    case INDEX_op_qemu_ld8u:
1141 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 0);
1142 c896fe29 bellard
        break;
1143 c896fe29 bellard
    case INDEX_op_qemu_ld8s:
1144 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 0 | 4);
1145 c896fe29 bellard
        break;
1146 c896fe29 bellard
    case INDEX_op_qemu_ld16u:
1147 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 1);
1148 c896fe29 bellard
        break;
1149 c896fe29 bellard
    case INDEX_op_qemu_ld16s:
1150 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 1 | 4);
1151 c896fe29 bellard
        break;
1152 c896fe29 bellard
    case INDEX_op_qemu_ld32u:
1153 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 2);
1154 c896fe29 bellard
        break;
1155 c896fe29 bellard
    case INDEX_op_qemu_ld32s:
1156 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 2 | 4);
1157 c896fe29 bellard
        break;
1158 c896fe29 bellard
    case INDEX_op_qemu_ld64:
1159 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 3);
1160 c896fe29 bellard
        break;
1161 c896fe29 bellard
        
1162 c896fe29 bellard
    case INDEX_op_qemu_st8:
1163 c896fe29 bellard
        tcg_out_qemu_st(s, args, 0);
1164 c896fe29 bellard
        break;
1165 c896fe29 bellard
    case INDEX_op_qemu_st16:
1166 c896fe29 bellard
        tcg_out_qemu_st(s, args, 1);
1167 c896fe29 bellard
        break;
1168 c896fe29 bellard
    case INDEX_op_qemu_st32:
1169 c896fe29 bellard
        tcg_out_qemu_st(s, args, 2);
1170 c896fe29 bellard
        break;
1171 c896fe29 bellard
    case INDEX_op_qemu_st64:
1172 c896fe29 bellard
        tcg_out_qemu_st(s, args, 3);
1173 c896fe29 bellard
        break;
1174 c896fe29 bellard
1175 c896fe29 bellard
    default:
1176 c896fe29 bellard
        tcg_abort();
1177 c896fe29 bellard
    }
1178 c896fe29 bellard
}
1179 c896fe29 bellard
1180 b03cce8e bellard
static int tcg_target_callee_save_regs[] = {
1181 b03cce8e bellard
    TCG_REG_RBP,
1182 b03cce8e bellard
    TCG_REG_RBX,
1183 b03cce8e bellard
    TCG_REG_R12,
1184 b03cce8e bellard
    TCG_REG_R13,
1185 b03cce8e bellard
    /*    TCG_REG_R14, */ /* currently used for the global env, so no
1186 b03cce8e bellard
                             need to save */
1187 b03cce8e bellard
    TCG_REG_R15,
1188 b03cce8e bellard
};
1189 b03cce8e bellard
1190 b03cce8e bellard
static inline void tcg_out_push(TCGContext *s, int reg)
1191 b03cce8e bellard
{
1192 b03cce8e bellard
    tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0);
1193 b03cce8e bellard
}
1194 b03cce8e bellard
1195 b03cce8e bellard
static inline void tcg_out_pop(TCGContext *s, int reg)
1196 b03cce8e bellard
{
1197 b03cce8e bellard
    tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0);
1198 b03cce8e bellard
}
1199 b03cce8e bellard
1200 b03cce8e bellard
/* Generate global QEMU prologue and epilogue code */
1201 b03cce8e bellard
void tcg_target_qemu_prologue(TCGContext *s)
1202 b03cce8e bellard
{
1203 b03cce8e bellard
    int i, frame_size, push_size, stack_addend;
1204 b03cce8e bellard
1205 b03cce8e bellard
    /* TB prologue */
1206 b03cce8e bellard
    /* save all callee saved registers */
1207 b03cce8e bellard
    for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1208 b03cce8e bellard
        tcg_out_push(s, tcg_target_callee_save_regs[i]);
1209 b03cce8e bellard
1210 b03cce8e bellard
    }
1211 b03cce8e bellard
    /* reserve some stack space */
1212 b03cce8e bellard
    push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8;
1213 b03cce8e bellard
    frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1214 b03cce8e bellard
    frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) & 
1215 b03cce8e bellard
        ~(TCG_TARGET_STACK_ALIGN - 1);
1216 b03cce8e bellard
    stack_addend = frame_size - push_size;
1217 b03cce8e bellard
    tcg_out_addi(s, TCG_REG_RSP, -stack_addend);
1218 b03cce8e bellard
1219 b03cce8e bellard
    tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp *%rdi */
1220 b03cce8e bellard
    
1221 b03cce8e bellard
    /* TB epilogue */
1222 b03cce8e bellard
    tb_ret_addr = s->code_ptr;
1223 b03cce8e bellard
    tcg_out_addi(s, TCG_REG_RSP, stack_addend);
1224 b03cce8e bellard
    for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1225 b03cce8e bellard
        tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1226 b03cce8e bellard
    }
1227 b03cce8e bellard
    tcg_out8(s, 0xc3); /* ret */
1228 b03cce8e bellard
}
1229 b03cce8e bellard
1230 c896fe29 bellard
static const TCGTargetOpDef x86_64_op_defs[] = {
1231 c896fe29 bellard
    { INDEX_op_exit_tb, { } },
1232 c896fe29 bellard
    { INDEX_op_goto_tb, { } },
1233 c896fe29 bellard
    { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */
1234 c896fe29 bellard
    { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */
1235 c896fe29 bellard
    { INDEX_op_br, { } },
1236 c896fe29 bellard
1237 c896fe29 bellard
    { INDEX_op_mov_i32, { "r", "r" } },
1238 c896fe29 bellard
    { INDEX_op_movi_i32, { "r" } },
1239 c896fe29 bellard
    { INDEX_op_ld8u_i32, { "r", "r" } },
1240 c896fe29 bellard
    { INDEX_op_ld8s_i32, { "r", "r" } },
1241 c896fe29 bellard
    { INDEX_op_ld16u_i32, { "r", "r" } },
1242 c896fe29 bellard
    { INDEX_op_ld16s_i32, { "r", "r" } },
1243 c896fe29 bellard
    { INDEX_op_ld_i32, { "r", "r" } },
1244 c896fe29 bellard
    { INDEX_op_st8_i32, { "r", "r" } },
1245 c896fe29 bellard
    { INDEX_op_st16_i32, { "r", "r" } },
1246 c896fe29 bellard
    { INDEX_op_st_i32, { "r", "r" } },
1247 c896fe29 bellard
1248 c896fe29 bellard
    { INDEX_op_add_i32, { "r", "0", "ri" } },
1249 c896fe29 bellard
    { INDEX_op_mul_i32, { "r", "0", "ri" } },
1250 c896fe29 bellard
    { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1251 c896fe29 bellard
    { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1252 c896fe29 bellard
    { INDEX_op_sub_i32, { "r", "0", "ri" } },
1253 c896fe29 bellard
    { INDEX_op_and_i32, { "r", "0", "ri" } },
1254 c896fe29 bellard
    { INDEX_op_or_i32, { "r", "0", "ri" } },
1255 c896fe29 bellard
    { INDEX_op_xor_i32, { "r", "0", "ri" } },
1256 c896fe29 bellard
1257 c896fe29 bellard
    { INDEX_op_shl_i32, { "r", "0", "ci" } },
1258 c896fe29 bellard
    { INDEX_op_shr_i32, { "r", "0", "ci" } },
1259 c896fe29 bellard
    { INDEX_op_sar_i32, { "r", "0", "ci" } },
1260 d42f183c aurel32
    { INDEX_op_rotl_i32, { "r", "0", "ci" } },
1261 d42f183c aurel32
    { INDEX_op_rotr_i32, { "r", "0", "ci" } },
1262 c896fe29 bellard
1263 c896fe29 bellard
    { INDEX_op_brcond_i32, { "r", "ri" } },
1264 c896fe29 bellard
1265 c896fe29 bellard
    { INDEX_op_mov_i64, { "r", "r" } },
1266 c896fe29 bellard
    { INDEX_op_movi_i64, { "r" } },
1267 c896fe29 bellard
    { INDEX_op_ld8u_i64, { "r", "r" } },
1268 c896fe29 bellard
    { INDEX_op_ld8s_i64, { "r", "r" } },
1269 c896fe29 bellard
    { INDEX_op_ld16u_i64, { "r", "r" } },
1270 c896fe29 bellard
    { INDEX_op_ld16s_i64, { "r", "r" } },
1271 c896fe29 bellard
    { INDEX_op_ld32u_i64, { "r", "r" } },
1272 c896fe29 bellard
    { INDEX_op_ld32s_i64, { "r", "r" } },
1273 c896fe29 bellard
    { INDEX_op_ld_i64, { "r", "r" } },
1274 c896fe29 bellard
    { INDEX_op_st8_i64, { "r", "r" } },
1275 c896fe29 bellard
    { INDEX_op_st16_i64, { "r", "r" } },
1276 c896fe29 bellard
    { INDEX_op_st32_i64, { "r", "r" } },
1277 c896fe29 bellard
    { INDEX_op_st_i64, { "r", "r" } },
1278 c896fe29 bellard
1279 c896fe29 bellard
    { INDEX_op_add_i64, { "r", "0", "re" } },
1280 c896fe29 bellard
    { INDEX_op_mul_i64, { "r", "0", "re" } },
1281 c896fe29 bellard
    { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } },
1282 c896fe29 bellard
    { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } },
1283 c896fe29 bellard
    { INDEX_op_sub_i64, { "r", "0", "re" } },
1284 c896fe29 bellard
    { INDEX_op_and_i64, { "r", "0", "reZ" } },
1285 c896fe29 bellard
    { INDEX_op_or_i64, { "r", "0", "re" } },
1286 c896fe29 bellard
    { INDEX_op_xor_i64, { "r", "0", "re" } },
1287 c896fe29 bellard
1288 c896fe29 bellard
    { INDEX_op_shl_i64, { "r", "0", "ci" } },
1289 c896fe29 bellard
    { INDEX_op_shr_i64, { "r", "0", "ci" } },
1290 c896fe29 bellard
    { INDEX_op_sar_i64, { "r", "0", "ci" } },
1291 d42f183c aurel32
    { INDEX_op_rotl_i64, { "r", "0", "ci" } },
1292 d42f183c aurel32
    { INDEX_op_rotr_i64, { "r", "0", "ci" } },
1293 c896fe29 bellard
1294 c896fe29 bellard
    { INDEX_op_brcond_i64, { "r", "re" } },
1295 c896fe29 bellard
1296 86dbdd40 aurel32
    { INDEX_op_bswap16_i32, { "r", "0" } },
1297 86dbdd40 aurel32
    { INDEX_op_bswap16_i64, { "r", "0" } },
1298 66896cb8 aurel32
    { INDEX_op_bswap32_i32, { "r", "0" } },
1299 86dbdd40 aurel32
    { INDEX_op_bswap32_i64, { "r", "0" } },
1300 66896cb8 aurel32
    { INDEX_op_bswap64_i64, { "r", "0" } },
1301 c896fe29 bellard
1302 390efc54 pbrook
    { INDEX_op_neg_i32, { "r", "0" } },
1303 390efc54 pbrook
    { INDEX_op_neg_i64, { "r", "0" } },
1304 390efc54 pbrook
1305 d2604285 aurel32
    { INDEX_op_not_i32, { "r", "0" } },
1306 d2604285 aurel32
    { INDEX_op_not_i64, { "r", "0" } },
1307 d2604285 aurel32
1308 b6d17150 pbrook
    { INDEX_op_ext8s_i32, { "r", "r"} },
1309 b6d17150 pbrook
    { INDEX_op_ext16s_i32, { "r", "r"} },
1310 b6d17150 pbrook
    { INDEX_op_ext8s_i64, { "r", "r"} },
1311 b6d17150 pbrook
    { INDEX_op_ext16s_i64, { "r", "r"} },
1312 b6d17150 pbrook
    { INDEX_op_ext32s_i64, { "r", "r"} },
1313 b6d17150 pbrook
1314 c896fe29 bellard
    { INDEX_op_qemu_ld8u, { "r", "L" } },
1315 c896fe29 bellard
    { INDEX_op_qemu_ld8s, { "r", "L" } },
1316 c896fe29 bellard
    { INDEX_op_qemu_ld16u, { "r", "L" } },
1317 c896fe29 bellard
    { INDEX_op_qemu_ld16s, { "r", "L" } },
1318 c896fe29 bellard
    { INDEX_op_qemu_ld32u, { "r", "L" } },
1319 c896fe29 bellard
    { INDEX_op_qemu_ld32s, { "r", "L" } },
1320 c896fe29 bellard
    { INDEX_op_qemu_ld64, { "r", "L" } },
1321 c896fe29 bellard
1322 c896fe29 bellard
    { INDEX_op_qemu_st8, { "L", "L" } },
1323 c896fe29 bellard
    { INDEX_op_qemu_st16, { "L", "L" } },
1324 c896fe29 bellard
    { INDEX_op_qemu_st32, { "L", "L" } },
1325 c896fe29 bellard
    { INDEX_op_qemu_st64, { "L", "L", "L" } },
1326 c896fe29 bellard
1327 c896fe29 bellard
    { -1 },
1328 c896fe29 bellard
};
1329 c896fe29 bellard
1330 c896fe29 bellard
void tcg_target_init(TCGContext *s)
1331 c896fe29 bellard
{
1332 b03cce8e bellard
    /* fail safe */
1333 b03cce8e bellard
    if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1334 b03cce8e bellard
        tcg_abort();
1335 b03cce8e bellard
1336 c896fe29 bellard
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
1337 c896fe29 bellard
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
1338 c896fe29 bellard
    tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1339 c896fe29 bellard
                     (1 << TCG_REG_RDI) | 
1340 c896fe29 bellard
                     (1 << TCG_REG_RSI) | 
1341 c896fe29 bellard
                     (1 << TCG_REG_RDX) |
1342 c896fe29 bellard
                     (1 << TCG_REG_RCX) |
1343 c896fe29 bellard
                     (1 << TCG_REG_R8) |
1344 c896fe29 bellard
                     (1 << TCG_REG_R9) |
1345 c896fe29 bellard
                     (1 << TCG_REG_RAX) |
1346 c896fe29 bellard
                     (1 << TCG_REG_R10) |
1347 c896fe29 bellard
                     (1 << TCG_REG_R11));
1348 c896fe29 bellard
    
1349 c896fe29 bellard
    tcg_regset_clear(s->reserved_regs);
1350 c896fe29 bellard
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP);
1351 3c3a1d20 bellard
1352 c896fe29 bellard
    tcg_add_target_add_op_defs(x86_64_op_defs);
1353 c896fe29 bellard
}