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root / target-ppc @ 79d342dc

Name Size
STATUS 10.6 kB
cpu.h 59.3 kB
exec.h 1.5 kB
helper.c 93.8 kB
helper.h 13.7 kB
helper_regs.h 3.4 kB
kvm.c 4.8 kB
kvm_ppc.c 2.6 kB
kvm_ppc.h 434 Bytes
machine.c 5.8 kB
mfrom_table.c 3.3 kB
mfrom_table_gen.c 652 Bytes
op_helper.c 123.8 kB
translate.c 307.8 kB
translate_init.c 413.3 kB

Latest revisions

# Date Author Comment
bf1752ef 03/29/2009 04:36 pm aurel32

target-ppc: Explain why the whole TLB is flushed on SR write

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6947 c046a42c-6fe2-441c-8c8c-71466251a162

af4b6c54 03/29/2009 04:18 am aurel32

target-ppc: avoid nop to override next instruction

While searching PC, always store the pc of a new instruction.
Instructions that didn't generate tcg code (such as nop) prevented the
next one to be referenced.

Based on patch for target-alpha, r6930.

Signed-off-by: Aurelien Jarno <>...

7f70c937 03/13/2009 11:16 pm blueswir1

Make the ELF loader aware of backwards compatibility

Most 64 bit architectures I'm aware of support running 32 bit code
of the same architecture as well.

So x86_64 can run i386 code easily and ppc64 can run ppc code.

Unfortunately, the current checks are pretty strict. So you can only...

fa3966a3 03/13/2009 11:35 am aurel32

target-ppc: use the new bswap* TCG ops

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6835 c046a42c-6fe2-441c-8c8c-71466251a162

66896cb8 03/13/2009 11:34 am aurel32

tcg: rename bswap_i32/i64 functions

Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162

515e2f7e 03/10/2009 09:37 pm aurel32

target-ppc: fix commit r6789

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6804 c046a42c-6fe2-441c-8c8c-71466251a162

651721b2 03/09/2009 08:50 pm aurel32

targe-ppc: optimize mfcr and mtcrf

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6793 c046a42c-6fe2-441c-8c8c-71466251a162

69bd5820 03/09/2009 08:27 am aurel32

target-ppc: free a tcg temp variable

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6790 c046a42c-6fe2-441c-8c8c-71466251a162

d34defbc 03/09/2009 08:27 am aurel32

target-ppc: add support for reading/writing spefscr

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6789 c046a42c-6fe2-441c-8c8c-71466251a162

70976a79 03/08/2009 12:00 am aurel32

Fix off-by-one errors for Altivec and SPE registers

Altivec and SPE both have 34 registers in their register sets, not 35
with a missing register 32.

GDB would ask for register 32 of the Altivec (resp. SPE) registers and
the code would claim it had zero width. The QEMU GDB stub code would...

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