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/*
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* i386 virtual CPU header
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef CPU_I386_H
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#define CPU_I386_H
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#include "config.h" |
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#ifdef TARGET_X86_64
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#define TARGET_LONG_BITS 64 |
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#else
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#define TARGET_LONG_BITS 32 |
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#endif
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/* target supports implicit self modifying code */
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#define TARGET_HAS_SMC
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/* support for self modifying code even if the modified instruction is
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close to the modifying instruction */
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#define TARGET_HAS_PRECISE_SMC
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#include "cpu-defs.h" |
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#include "softfloat.h" |
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#if defined(__i386__) && !defined(CONFIG_SOFTMMU)
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#define USE_CODE_COPY
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#endif
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#define R_EAX 0 |
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#define R_ECX 1 |
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#define R_EDX 2 |
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#define R_EBX 3 |
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#define R_ESP 4 |
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#define R_EBP 5 |
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#define R_ESI 6 |
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#define R_EDI 7 |
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#define R_AL 0 |
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#define R_CL 1 |
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#define R_DL 2 |
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#define R_BL 3 |
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#define R_AH 4 |
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#define R_CH 5 |
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#define R_DH 6 |
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#define R_BH 7 |
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#define R_ES 0 |
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#define R_CS 1 |
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#define R_SS 2 |
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#define R_DS 3 |
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#define R_FS 4 |
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#define R_GS 5 |
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/* segment descriptor fields */
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#define DESC_G_MASK (1 << 23) |
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#define DESC_B_SHIFT 22 |
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#define DESC_B_MASK (1 << DESC_B_SHIFT) |
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#define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
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#define DESC_L_MASK (1 << DESC_L_SHIFT) |
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#define DESC_AVL_MASK (1 << 20) |
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#define DESC_P_MASK (1 << 15) |
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#define DESC_DPL_SHIFT 13 |
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#define DESC_S_MASK (1 << 12) |
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#define DESC_TYPE_SHIFT 8 |
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#define DESC_A_MASK (1 << 8) |
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#define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
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#define DESC_C_MASK (1 << 10) /* code: conforming */ |
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#define DESC_R_MASK (1 << 9) /* code: readable */ |
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#define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
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#define DESC_W_MASK (1 << 9) /* data: writable */ |
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#define DESC_TSS_BUSY_MASK (1 << 9) |
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/* eflags masks */
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#define CC_C 0x0001 |
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#define CC_P 0x0004 |
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#define CC_A 0x0010 |
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#define CC_Z 0x0040 |
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#define CC_S 0x0080 |
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#define CC_O 0x0800 |
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#define TF_SHIFT 8 |
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#define IOPL_SHIFT 12 |
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#define VM_SHIFT 17 |
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#define TF_MASK 0x00000100 |
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#define IF_MASK 0x00000200 |
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#define DF_MASK 0x00000400 |
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#define IOPL_MASK 0x00003000 |
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#define NT_MASK 0x00004000 |
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#define RF_MASK 0x00010000 |
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#define VM_MASK 0x00020000 |
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#define AC_MASK 0x00040000 |
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#define VIF_MASK 0x00080000 |
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#define VIP_MASK 0x00100000 |
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#define ID_MASK 0x00200000 |
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/* hidden flags - used internally by qemu to represent additionnal cpu
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states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
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using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
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with eflags. */
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/* current cpl */
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#define HF_CPL_SHIFT 0 |
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/* true if soft mmu is being used */
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#define HF_SOFTMMU_SHIFT 2 |
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/* true if hardware interrupts must be disabled for next instruction */
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#define HF_INHIBIT_IRQ_SHIFT 3 |
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/* 16 or 32 segments */
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#define HF_CS32_SHIFT 4 |
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#define HF_SS32_SHIFT 5 |
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/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
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#define HF_ADDSEG_SHIFT 6 |
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/* copy of CR0.PE (protected mode) */
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#define HF_PE_SHIFT 7 |
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#define HF_TF_SHIFT 8 /* must be same as eflags */ |
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#define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
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#define HF_EM_SHIFT 10 |
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#define HF_TS_SHIFT 11 |
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#define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
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#define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
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#define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ |
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#define HF_OSFXSR_SHIFT 16 /* CR4.OSFXSR */ |
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#define HF_VM_SHIFT 17 /* must be same as eflags */ |
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#define HF_CPL_MASK (3 << HF_CPL_SHIFT) |
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#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) |
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#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) |
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#define HF_CS32_MASK (1 << HF_CS32_SHIFT) |
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#define HF_SS32_MASK (1 << HF_SS32_SHIFT) |
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#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) |
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#define HF_PE_MASK (1 << HF_PE_SHIFT) |
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#define HF_TF_MASK (1 << HF_TF_SHIFT) |
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#define HF_MP_MASK (1 << HF_MP_SHIFT) |
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#define HF_EM_MASK (1 << HF_EM_SHIFT) |
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#define HF_TS_MASK (1 << HF_TS_SHIFT) |
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#define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
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#define HF_CS64_MASK (1 << HF_CS64_SHIFT) |
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#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
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#define CR0_PE_MASK (1 << 0) |
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#define CR0_MP_MASK (1 << 1) |
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#define CR0_EM_MASK (1 << 2) |
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#define CR0_TS_MASK (1 << 3) |
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#define CR0_ET_MASK (1 << 4) |
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#define CR0_NE_MASK (1 << 5) |
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#define CR0_WP_MASK (1 << 16) |
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#define CR0_AM_MASK (1 << 18) |
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#define CR0_PG_MASK (1 << 31) |
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#define CR4_VME_MASK (1 << 0) |
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#define CR4_PVI_MASK (1 << 1) |
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#define CR4_TSD_MASK (1 << 2) |
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#define CR4_DE_MASK (1 << 3) |
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#define CR4_PSE_MASK (1 << 4) |
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#define CR4_PAE_MASK (1 << 5) |
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#define CR4_PGE_MASK (1 << 7) |
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#define CR4_PCE_MASK (1 << 8) |
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#define CR4_OSFXSR_MASK (1 << 9) |
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#define CR4_OSXMMEXCPT_MASK (1 << 10) |
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#define PG_PRESENT_BIT 0 |
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#define PG_RW_BIT 1 |
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#define PG_USER_BIT 2 |
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#define PG_PWT_BIT 3 |
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#define PG_PCD_BIT 4 |
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#define PG_ACCESSED_BIT 5 |
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#define PG_DIRTY_BIT 6 |
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#define PG_PSE_BIT 7 |
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#define PG_GLOBAL_BIT 8 |
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#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) |
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#define PG_RW_MASK (1 << PG_RW_BIT) |
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#define PG_USER_MASK (1 << PG_USER_BIT) |
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#define PG_PWT_MASK (1 << PG_PWT_BIT) |
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#define PG_PCD_MASK (1 << PG_PCD_BIT) |
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#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
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#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
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#define PG_PSE_MASK (1 << PG_PSE_BIT) |
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#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) |
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#define PG_ERROR_W_BIT 1 |
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#define PG_ERROR_P_MASK 0x01 |
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#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) |
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#define PG_ERROR_U_MASK 0x04 |
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#define PG_ERROR_RSVD_MASK 0x08 |
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#define MSR_IA32_APICBASE 0x1b |
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#define MSR_IA32_APICBASE_BSP (1<<8) |
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#define MSR_IA32_APICBASE_ENABLE (1<<11) |
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#define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
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#define MSR_IA32_SYSENTER_CS 0x174 |
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#define MSR_IA32_SYSENTER_ESP 0x175 |
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#define MSR_IA32_SYSENTER_EIP 0x176 |
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#define MSR_EFER 0xc0000080 |
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#define MSR_EFER_SCE (1 << 0) |
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#define MSR_EFER_LME (1 << 8) |
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#define MSR_EFER_LMA (1 << 10) |
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#define MSR_EFER_NXE (1 << 11) |
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#define MSR_EFER_FFXSR (1 << 14) |
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#define MSR_STAR 0xc0000081 |
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#define MSR_LSTAR 0xc0000082 |
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#define MSR_CSTAR 0xc0000083 |
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#define MSR_FMASK 0xc0000084 |
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#define MSR_FSBASE 0xc0000100 |
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#define MSR_GSBASE 0xc0000101 |
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#define MSR_KERNELGSBASE 0xc0000102 |
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/* cpuid_features bits */
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#define CPUID_FP87 (1 << 0) |
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#define CPUID_VME (1 << 1) |
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#define CPUID_DE (1 << 2) |
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#define CPUID_PSE (1 << 3) |
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#define CPUID_TSC (1 << 4) |
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#define CPUID_MSR (1 << 5) |
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#define CPUID_PAE (1 << 6) |
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#define CPUID_MCE (1 << 7) |
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#define CPUID_CX8 (1 << 8) |
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#define CPUID_APIC (1 << 9) |
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#define CPUID_SEP (1 << 11) /* sysenter/sysexit */ |
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#define CPUID_MTRR (1 << 12) |
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#define CPUID_PGE (1 << 13) |
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#define CPUID_MCA (1 << 14) |
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#define CPUID_CMOV (1 << 15) |
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/* ... */
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#define CPUID_MMX (1 << 23) |
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#define CPUID_FXSR (1 << 24) |
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#define CPUID_SSE (1 << 25) |
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#define CPUID_SSE2 (1 << 26) |
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#define CPUID_EXT_SS3 (1 << 0) |
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#define CPUID_EXT_MONITOR (1 << 3) |
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#define CPUID_EXT_CX16 (1 << 13) |
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#define CPUID_EXT2_SYSCALL (1 << 11) |
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#define CPUID_EXT2_NX (1 << 20) |
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#define CPUID_EXT2_LM (1 << 29) |
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#define EXCP00_DIVZ 0 |
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#define EXCP01_SSTP 1 |
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#define EXCP02_NMI 2 |
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#define EXCP03_INT3 3 |
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#define EXCP04_INTO 4 |
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#define EXCP05_BOUND 5 |
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#define EXCP06_ILLOP 6 |
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#define EXCP07_PREX 7 |
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#define EXCP08_DBLE 8 |
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#define EXCP09_XERR 9 |
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#define EXCP0A_TSS 10 |
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#define EXCP0B_NOSEG 11 |
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#define EXCP0C_STACK 12 |
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#define EXCP0D_GPF 13 |
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#define EXCP0E_PAGE 14 |
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#define EXCP10_COPR 16 |
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#define EXCP11_ALGN 17 |
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#define EXCP12_MCHK 18 |
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enum {
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CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
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CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
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CC_OP_MULW, |
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CC_OP_MULL, |
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CC_OP_MULQ, |
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CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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CC_OP_ADDW, |
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CC_OP_ADDL, |
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CC_OP_ADDQ, |
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CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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CC_OP_ADCW, |
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CC_OP_ADCL, |
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CC_OP_ADCQ, |
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CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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CC_OP_SUBW, |
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CC_OP_SUBL, |
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CC_OP_SUBQ, |
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CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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CC_OP_SBBW, |
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CC_OP_SBBL, |
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CC_OP_SBBQ, |
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CC_OP_LOGICB, /* modify all flags, CC_DST = res */
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CC_OP_LOGICW, |
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CC_OP_LOGICL, |
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CC_OP_LOGICQ, |
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CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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CC_OP_INCW, |
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CC_OP_INCL, |
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CC_OP_INCQ, |
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CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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CC_OP_DECW, |
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CC_OP_DECL, |
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CC_OP_DECQ, |
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CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
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CC_OP_SHLW, |
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CC_OP_SHLL, |
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CC_OP_SHLQ, |
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CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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CC_OP_SARW, |
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CC_OP_SARL, |
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CC_OP_SARQ, |
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CC_OP_NB, |
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}; |
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#ifdef FLOATX80
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#define USE_X86LDOUBLE
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#endif
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#ifdef USE_X86LDOUBLE
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typedef floatx80 CPU86_LDouble;
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#else
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typedef float64 CPU86_LDouble;
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#endif
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typedef struct SegmentCache { |
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uint32_t selector; |
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target_ulong base; |
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uint32_t limit; |
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uint32_t flags; |
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} SegmentCache; |
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typedef union { |
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uint8_t _b[16];
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uint16_t _w[8];
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uint32_t _l[4];
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uint64_t _q[2];
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float32 _s[4];
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float64 _d[2];
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} XMMReg; |
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typedef union { |
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uint8_t _b[8];
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uint16_t _w[2];
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uint32_t _l[1];
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uint64_t q; |
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} MMXReg; |
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#ifdef WORDS_BIGENDIAN
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#define XMM_B(n) _b[15 - (n)] |
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#define XMM_W(n) _w[7 - (n)] |
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#define XMM_L(n) _l[3 - (n)] |
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#define XMM_S(n) _s[3 - (n)] |
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#define XMM_Q(n) _q[1 - (n)] |
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#define XMM_D(n) _d[1 - (n)] |
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#define MMX_B(n) _b[7 - (n)] |
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#define MMX_W(n) _w[3 - (n)] |
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#define MMX_L(n) _l[1 - (n)] |
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#else
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#define XMM_B(n) _b[n]
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#define XMM_W(n) _w[n]
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#define XMM_L(n) _l[n]
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#define XMM_S(n) _s[n]
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#define XMM_Q(n) _q[n]
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#define XMM_D(n) _d[n]
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#define MMX_B(n) _b[n]
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#define MMX_W(n) _w[n]
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#define MMX_L(n) _l[n]
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#endif
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#define MMX_Q(n) q
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#ifdef TARGET_X86_64
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#define CPU_NB_REGS 16 |
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#else
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#define CPU_NB_REGS 8 |
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#endif
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typedef struct CPUX86State { |
402 |
#if TARGET_LONG_BITS > HOST_LONG_BITS
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/* temporaries if we cannot store them in host registers */
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target_ulong t0, t1, t2; |
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#endif
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/* standard registers */
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target_ulong regs[CPU_NB_REGS]; |
409 |
target_ulong eip; |
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target_ulong eflags; /* eflags register. During CPU emulation, CC
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flags and DF are set to zero because they are
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stored elsewhere */
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/* emulator internal eflags handling */
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target_ulong cc_src; |
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target_ulong cc_dst; |
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uint32_t cc_op; |
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int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
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uint32_t hflags; /* hidden flags, see HF_xxx constants */
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/* segments */
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SegmentCache segs[6]; /* selector values */ |
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SegmentCache ldt; |
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SegmentCache tr; |
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SegmentCache gdt; /* only base and limit are used */
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SegmentCache idt; /* only base and limit are used */
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target_ulong cr[5]; /* NOTE: cr1 is unused */ |
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uint32_t a20_mask; |
430 |
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/* FPU state */
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unsigned int fpstt; /* top of stack index */ |
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unsigned int fpus; |
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unsigned int fpuc; |
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uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
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union {
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#ifdef USE_X86LDOUBLE
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CPU86_LDouble d __attribute__((aligned(16)));
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#else
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CPU86_LDouble d; |
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#endif
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MMXReg mmx; |
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} fpregs[8];
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|
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/* emulator internal variables */
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float_status fp_status; |
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CPU86_LDouble ft0; |
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union {
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float f;
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double d;
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int i32;
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int64_t i64; |
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} fp_convert; |
454 |
|
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float_status sse_status; |
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uint32_t mxcsr; |
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XMMReg xmm_regs[CPU_NB_REGS]; |
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XMMReg xmm_t0; |
459 |
MMXReg mmx_t0; |
460 |
|
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/* sysenter registers */
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uint32_t sysenter_cs; |
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uint32_t sysenter_esp; |
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uint32_t sysenter_eip; |
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#ifdef TARGET_X86_64
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target_ulong efer; |
467 |
target_ulong star; |
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target_ulong lstar; |
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target_ulong cstar; |
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target_ulong fmask; |
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target_ulong kernelgsbase; |
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#endif
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|
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/* temporary data for USE_CODE_COPY mode */
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#ifdef USE_CODE_COPY
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uint32_t tmp0; |
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uint32_t saved_esp; |
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int native_fp_regs; /* if true, the FPU state is in the native CPU regs */ |
479 |
#endif
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|
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/* exception/interrupt handling */
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jmp_buf jmp_env; |
483 |
int exception_index;
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int error_code;
|
485 |
int exception_is_int;
|
486 |
target_ulong exception_next_eip; |
487 |
struct TranslationBlock *current_tb; /* currently executing TB */ |
488 |
target_ulong dr[8]; /* debug registers */ |
489 |
int interrupt_request;
|
490 |
int user_mode_only; /* user mode only simulation */ |
491 |
|
492 |
/* soft mmu support */
|
493 |
/* in order to avoid passing too many arguments to the memory
|
494 |
write helpers, we store some rarely used information in the CPU
|
495 |
context) */
|
496 |
unsigned long mem_write_pc; /* host pc at which the memory was |
497 |
written */
|
498 |
target_ulong mem_write_vaddr; /* target virtual addr at which the
|
499 |
memory was written */
|
500 |
/* 0 = kernel, 1 = user */
|
501 |
CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
|
502 |
CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
|
503 |
|
504 |
/* from this point: preserved by CPU reset */
|
505 |
/* ice debug support */
|
506 |
target_ulong breakpoints[MAX_BREAKPOINTS]; |
507 |
int nb_breakpoints;
|
508 |
int singlestep_enabled;
|
509 |
|
510 |
/* processor features (e.g. for CPUID insn) */
|
511 |
uint32_t cpuid_vendor1; |
512 |
uint32_t cpuid_vendor2; |
513 |
uint32_t cpuid_vendor3; |
514 |
uint32_t cpuid_version; |
515 |
uint32_t cpuid_features; |
516 |
uint32_t cpuid_ext_features; |
517 |
|
518 |
#ifdef USE_KQEMU
|
519 |
int kqemu_enabled;
|
520 |
#endif
|
521 |
/* in order to simplify APIC support, we leave this pointer to the
|
522 |
user */
|
523 |
struct APICState *apic_state;
|
524 |
/* user data */
|
525 |
void *opaque;
|
526 |
} CPUX86State; |
527 |
|
528 |
CPUX86State *cpu_x86_init(void);
|
529 |
int cpu_x86_exec(CPUX86State *s);
|
530 |
void cpu_x86_close(CPUX86State *s);
|
531 |
int cpu_get_pic_interrupt(CPUX86State *s);
|
532 |
/* MSDOS compatibility mode FPU exception support */
|
533 |
void cpu_set_ferr(CPUX86State *s);
|
534 |
|
535 |
/* this function must always be used to load data in the segment
|
536 |
cache: it synchronizes the hflags with the segment cache values */
|
537 |
static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
538 |
int seg_reg, unsigned int selector, |
539 |
uint32_t base, unsigned int limit, |
540 |
unsigned int flags) |
541 |
{ |
542 |
SegmentCache *sc; |
543 |
unsigned int new_hflags; |
544 |
|
545 |
sc = &env->segs[seg_reg]; |
546 |
sc->selector = selector; |
547 |
sc->base = base; |
548 |
sc->limit = limit; |
549 |
sc->flags = flags; |
550 |
|
551 |
/* update the hidden flags */
|
552 |
{ |
553 |
if (seg_reg == R_CS) {
|
554 |
#ifdef TARGET_X86_64
|
555 |
if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
|
556 |
/* long mode */
|
557 |
env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; |
558 |
env->hflags &= ~(HF_ADDSEG_MASK); |
559 |
} else
|
560 |
#endif
|
561 |
{ |
562 |
/* legacy / compatibility case */
|
563 |
new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) |
564 |
>> (DESC_B_SHIFT - HF_CS32_SHIFT); |
565 |
env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | |
566 |
new_hflags; |
567 |
} |
568 |
} |
569 |
new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) |
570 |
>> (DESC_B_SHIFT - HF_SS32_SHIFT); |
571 |
if (env->hflags & HF_CS64_MASK) {
|
572 |
/* zero base assumed for DS, ES and SS in long mode */
|
573 |
} else if (!(env->cr[0] & CR0_PE_MASK) || |
574 |
(env->eflags & VM_MASK) || |
575 |
!(env->hflags & HF_CS32_MASK)) { |
576 |
/* XXX: try to avoid this test. The problem comes from the
|
577 |
fact that is real mode or vm86 mode we only modify the
|
578 |
'base' and 'selector' fields of the segment cache to go
|
579 |
faster. A solution may be to force addseg to one in
|
580 |
translate-i386.c. */
|
581 |
new_hflags |= HF_ADDSEG_MASK; |
582 |
} else {
|
583 |
new_hflags |= ((env->segs[R_DS].base | |
584 |
env->segs[R_ES].base | |
585 |
env->segs[R_SS].base) != 0) <<
|
586 |
HF_ADDSEG_SHIFT; |
587 |
} |
588 |
env->hflags = (env->hflags & |
589 |
~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
590 |
} |
591 |
} |
592 |
|
593 |
/* wrapper, just in case memory mappings must be changed */
|
594 |
static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl) |
595 |
{ |
596 |
#if HF_CPL_MASK == 3 |
597 |
s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl; |
598 |
#else
|
599 |
#error HF_CPL_MASK is hardcoded
|
600 |
#endif
|
601 |
} |
602 |
|
603 |
/* used for debug or cpu save/restore */
|
604 |
void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
|
605 |
CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper); |
606 |
|
607 |
/* the following helpers are only usable in user mode simulation as
|
608 |
they can trigger unexpected exceptions */
|
609 |
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); |
610 |
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32); |
611 |
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32); |
612 |
|
613 |
/* you can call this signal handler from your SIGBUS and SIGSEGV
|
614 |
signal handlers to inform the virtual CPU of exceptions. non zero
|
615 |
is returned if the signal was handled by the virtual CPU. */
|
616 |
struct siginfo;
|
617 |
int cpu_x86_signal_handler(int host_signum, struct siginfo *info, |
618 |
void *puc);
|
619 |
void cpu_x86_set_a20(CPUX86State *env, int a20_state); |
620 |
|
621 |
uint64_t cpu_get_tsc(CPUX86State *env); |
622 |
|
623 |
void cpu_set_apic_base(CPUX86State *env, uint64_t val);
|
624 |
uint64_t cpu_get_apic_base(CPUX86State *env); |
625 |
void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
|
626 |
#ifndef NO_CPU_IO_DEFS
|
627 |
uint8_t cpu_get_apic_tpr(CPUX86State *env); |
628 |
#endif
|
629 |
|
630 |
/* will be suppressed */
|
631 |
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
|
632 |
|
633 |
/* used to debug */
|
634 |
#define X86_DUMP_FPU 0x0001 /* dump FPU state too */ |
635 |
#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */ |
636 |
|
637 |
#define TARGET_PAGE_BITS 12 |
638 |
#include "cpu-all.h" |
639 |
|
640 |
#endif /* CPU_I386_H */ |