root / target-sparc / op_helper.c @ 7a0e1f41
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#include "exec.h" |
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//#define DEBUG_MMU
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void raise_exception(int tt) |
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{
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env->exception_index = tt; |
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cpu_loop_exit(); |
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} |
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#ifdef USE_INT_TO_FLOAT_HELPERS
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void do_fitos(void) |
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{
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FT0 = (float) *((int32_t *)&FT1);
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} |
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void do_fitod(void) |
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{
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DT0 = (double) *((int32_t *)&FT1);
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} |
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#endif
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void do_fabss(void) |
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{
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FT0 = float32_abs(FT1); |
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} |
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void do_fsqrts(void) |
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{
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FT0 = float32_sqrt(FT1, &env->fp_status); |
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} |
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void do_fsqrtd(void) |
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{
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DT0 = float64_sqrt(DT1, &env->fp_status); |
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} |
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void do_fcmps (void) |
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{
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if (isnan(FT0) || isnan(FT1)) {
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T0 = FSR_FCC1 | FSR_FCC0; |
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env->fsr &= ~(FSR_FCC1 | FSR_FCC0); |
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env->fsr |= T0; |
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if (env->fsr & FSR_NVM) {
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (FT0 < FT1) { |
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T0 = FSR_FCC0; |
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} else if (FT0 > FT1) { |
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T0 = FSR_FCC1; |
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} else {
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T0 = 0;
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} |
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env->fsr = T0; |
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} |
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void do_fcmpd (void) |
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{
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if (isnan(DT0) || isnan(DT1)) {
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T0 = FSR_FCC1 | FSR_FCC0; |
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env->fsr &= ~(FSR_FCC1 | FSR_FCC0); |
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env->fsr |= T0; |
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if (env->fsr & FSR_NVM) {
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (DT0 < DT1) { |
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T0 = FSR_FCC0; |
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} else if (DT0 > DT1) { |
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T0 = FSR_FCC1; |
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} else {
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T0 = 0;
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} |
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env->fsr = T0; |
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} |
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void helper_ld_asi(int asi, int size, int sign) |
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{
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uint32_t ret; |
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switch (asi) {
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case 3: /* MMU probe */ |
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{
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int mmulev;
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mmulev = (T0 >> 8) & 15; |
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if (mmulev > 4) |
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ret = 0;
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else {
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ret = mmu_probe(T0, mmulev); |
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//bswap32s(&ret);
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} |
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#ifdef DEBUG_MMU
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printf("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
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#endif
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} |
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break;
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case 4: /* read MMU regs */ |
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{
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int reg = (T0 >> 8) & 0xf; |
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ret = env->mmuregs[reg]; |
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if (reg == 3) /* Fault status cleared on read */ |
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env->mmuregs[reg] = 0;
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#ifdef DEBUG_MMU
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printf("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
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#endif
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} |
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break;
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case 0x20 ... 0x2f: /* MMU passthrough */ |
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cpu_physical_memory_read(T0, (void *) &ret, size);
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if (size == 4) |
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tswap32s(&ret); |
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else if (size == 2) |
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tswap16s((uint16_t *)&ret); |
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break;
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default:
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ret = 0;
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break;
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} |
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T1 = ret; |
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} |
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void helper_st_asi(int asi, int size, int sign) |
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{
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switch(asi) {
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case 3: /* MMU flush */ |
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{
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int mmulev;
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mmulev = (T0 >> 8) & 15; |
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#ifdef DEBUG_MMU
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printf("mmu flush level %d\n", mmulev);
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#endif
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switch (mmulev) {
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case 0: // flush page |
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tlb_flush_page(env, T0 & 0xfffff000);
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break;
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case 1: // flush segment (256k) |
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case 2: // flush region (16M) |
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case 3: // flush context (4G) |
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case 4: // flush entire |
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tlb_flush(env, 1);
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break;
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default:
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break;
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} |
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#ifdef DEBUG_MMU
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dump_mmu(); |
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#endif
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return;
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} |
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case 4: /* write MMU regs */ |
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{
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int reg = (T0 >> 8) & 0xf, oldreg; |
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oldreg = env->mmuregs[reg]; |
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switch(reg) {
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case 0: |
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env->mmuregs[reg] &= ~(MMU_E | MMU_NF); |
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env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF); |
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// Mappings generated during no-fault mode or MMU
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// disabled mode are invalid in normal mode
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if (oldreg != env->mmuregs[reg])
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tlb_flush(env, 1);
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break;
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case 2: |
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env->mmuregs[reg] = T1; |
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if (oldreg != env->mmuregs[reg]) {
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/* we flush when the MMU context changes because
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QEMU has no MMU context support */
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tlb_flush(env, 1);
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} |
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break;
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case 3: |
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case 4: |
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break;
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default:
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env->mmuregs[reg] = T1; |
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break;
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} |
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#ifdef DEBUG_MMU
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if (oldreg != env->mmuregs[reg]) {
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printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
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} |
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dump_mmu(); |
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#endif
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return;
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} |
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case 0x17: /* Block copy, sta access */ |
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{
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// value (T1) = src
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// address (T0) = dst
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// copy 32 bytes
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int src = T1, dst = T0;
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uint8_t temp[32];
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tswap32s(&src); |
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cpu_physical_memory_read(src, (void *) &temp, 32); |
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cpu_physical_memory_write(dst, (void *) &temp, 32); |
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} |
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return;
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case 0x1f: /* Block fill, stda access */ |
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{
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// value (T1, T2)
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// address (T0) = dst
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// fill 32 bytes
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int i, dst = T0;
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uint64_t val; |
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val = (((uint64_t)T1) << 32) | T2;
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tswap64s(&val); |
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for (i = 0; i < 32; i += 8, dst += 8) { |
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cpu_physical_memory_write(dst, (void *) &val, 8); |
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} |
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} |
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return;
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case 0x20 ... 0x2f: /* MMU passthrough */ |
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{
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int temp = T1;
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if (size == 4) |
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tswap32s(&temp); |
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else if (size == 2) |
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tswap16s((uint16_t *)&temp); |
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cpu_physical_memory_write(T0, (void *) &temp, size);
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} |
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return;
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default:
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return;
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} |
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} |
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void helper_rett()
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{
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unsigned int cwp; |
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env->psret = 1;
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cwp = (env->cwp + 1) & (NWINDOWS - 1); |
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if (env->wim & (1 << cwp)) { |
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raise_exception(TT_WIN_UNF); |
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} |
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set_cwp(cwp); |
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env->psrs = env->psrps; |
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} |
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void helper_ldfsr(void) |
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{
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int rnd_mode;
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switch (env->fsr & FSR_RD_MASK) {
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case FSR_RD_NEAREST:
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rnd_mode = float_round_nearest_even; |
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break;
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case FSR_RD_ZERO:
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rnd_mode = float_round_to_zero; |
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break;
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case FSR_RD_POS:
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rnd_mode = float_round_up; |
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break;
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case FSR_RD_NEG:
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rnd_mode = float_round_down; |
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break;
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} |
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set_float_rounding_mode(rnd_mode, &env->fp_status); |
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} |
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void cpu_get_fp64(uint64_t *pmant, uint16_t *pexp, double f) |
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{
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int exptemp;
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*pmant = ldexp(frexp(f, &exptemp), 53);
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*pexp = exptemp; |
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} |
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double cpu_put_fp64(uint64_t mant, uint16_t exp)
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{
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return ldexp((double) mant, exp - 53); |
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} |
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void helper_debug()
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{
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env->exception_index = EXCP_DEBUG; |
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cpu_loop_exit(); |
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} |
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void do_wrpsr()
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{
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PUT_PSR(env, T0); |
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} |
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void do_rdpsr()
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{
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T0 = GET_PSR(env); |
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} |