Revision 7a387fff
| b/target-mips/cpu.h | ||
|---|---|---|
| 99 | 99 |
#endif |
| 100 | 100 |
uint32_t CP0_index; |
| 101 | 101 |
uint32_t CP0_random; |
| 102 |
uint32_t CP0_EntryLo0;
|
|
| 103 |
uint32_t CP0_EntryLo1;
|
|
| 104 |
uint32_t CP0_Context;
|
|
| 102 |
uint64_t CP0_EntryLo0;
|
|
| 103 |
uint64_t CP0_EntryLo1;
|
|
| 104 |
uint64_t CP0_Context;
|
|
| 105 | 105 |
uint32_t CP0_PageMask; |
| 106 |
uint32_t CP0_PageGrain; |
|
| 106 | 107 |
uint32_t CP0_Wired; |
| 108 |
uint32_t CP0_HWREna; |
|
| 107 | 109 |
uint32_t CP0_BadVAddr; |
| 108 | 110 |
uint32_t CP0_Count; |
| 109 |
uint32_t CP0_EntryHi;
|
|
| 111 |
uint64_t CP0_EntryHi;
|
|
| 110 | 112 |
uint32_t CP0_Compare; |
| 111 | 113 |
uint32_t CP0_Status; |
| 112 | 114 |
#define CP0St_CU3 31 |
| ... | ... | |
| 116 | 118 |
#define CP0St_RP 27 |
| 117 | 119 |
#define CP0St_FR 26 |
| 118 | 120 |
#define CP0St_RE 25 |
| 121 |
#define CP0St_MX 24 |
|
| 122 |
#define CP0St_PX 23 |
|
| 119 | 123 |
#define CP0St_BEV 22 |
| 120 | 124 |
#define CP0St_TS 21 |
| 121 | 125 |
#define CP0St_SR 20 |
| 122 | 126 |
#define CP0St_NMI 19 |
| 123 | 127 |
#define CP0St_IM 8 |
| 128 |
#define CP0St_KX 7 |
|
| 129 |
#define CP0St_SX 6 |
|
| 130 |
#define CP0St_UX 5 |
|
| 124 | 131 |
#define CP0St_UM 4 |
| 132 |
#define CP0St_R0 3 |
|
| 125 | 133 |
#define CP0St_ERL 2 |
| 126 | 134 |
#define CP0St_EXL 1 |
| 127 | 135 |
#define CP0St_IE 0 |
| 136 |
uint32_t CP0_IntCtl; |
|
| 137 |
uint32_t CP0_SRSCtl; |
|
| 128 | 138 |
uint32_t CP0_Cause; |
| 139 |
#define CP0Ca_BD 31 |
|
| 140 |
#define CP0Ca_TI 30 |
|
| 141 |
#define CP0Ca_CE 28 |
|
| 142 |
#define CP0Ca_DC 27 |
|
| 143 |
#define CP0Ca_PCI 26 |
|
| 129 | 144 |
#define CP0Ca_IV 23 |
| 145 |
#define CP0Ca_WP 22 |
|
| 146 |
#define CP0Ca_IP 8 |
|
| 147 |
#define CP0Ca_EC 2 |
|
| 130 | 148 |
uint32_t CP0_EPC; |
| 131 | 149 |
uint32_t CP0_PRid; |
| 150 |
uint32_t CP0_EBase; |
|
| 132 | 151 |
uint32_t CP0_Config0; |
| 133 | 152 |
#define CP0C0_M 31 |
| 134 | 153 |
#define CP0C0_K23 28 |
| ... | ... | |
| 140 | 159 |
#define CP0C0_AT 13 |
| 141 | 160 |
#define CP0C0_AR 10 |
| 142 | 161 |
#define CP0C0_MT 7 |
| 162 |
#define CP0C0_VI 3 |
|
| 143 | 163 |
#define CP0C0_K0 0 |
| 144 | 164 |
uint32_t CP0_Config1; |
| 165 |
#define CP0C1_M 31 |
|
| 145 | 166 |
#define CP0C1_MMU 25 |
| 146 | 167 |
#define CP0C1_IS 22 |
| 147 | 168 |
#define CP0C1_IL 19 |
| ... | ... | |
| 149 | 170 |
#define CP0C1_DS 13 |
| 150 | 171 |
#define CP0C1_DL 10 |
| 151 | 172 |
#define CP0C1_DA 7 |
| 173 |
#define CP0C1_C2 6 |
|
| 174 |
#define CP0C1_MD 5 |
|
| 152 | 175 |
#define CP0C1_PC 4 |
| 153 | 176 |
#define CP0C1_WR 3 |
| 154 | 177 |
#define CP0C1_CA 2 |
| 155 | 178 |
#define CP0C1_EP 1 |
| 156 | 179 |
#define CP0C1_FP 0 |
| 180 |
uint32_t CP0_Config2; |
|
| 181 |
#define CP0C2_M 31 |
|
| 182 |
#define CP0C2_TU 28 |
|
| 183 |
#define CP0C2_TS 24 |
|
| 184 |
#define CP0C2_TL 20 |
|
| 185 |
#define CP0C2_TA 16 |
|
| 186 |
#define CP0C2_SU 12 |
|
| 187 |
#define CP0C2_SS 8 |
|
| 188 |
#define CP0C2_SL 4 |
|
| 189 |
#define CP0C2_SA 0 |
|
| 190 |
uint32_t CP0_Config3; |
|
| 191 |
#define CP0C3_M 31 |
|
| 192 |
#define CP0C3_DSPP 10 |
|
| 193 |
#define CP0C3_LPA 7 |
|
| 194 |
#define CP0C3_VEIC 6 |
|
| 195 |
#define CP0C3_VInt 5 |
|
| 196 |
#define CP0C3_SP 4 |
|
| 197 |
#define CP0C3_MT 2 |
|
| 198 |
#define CP0C3_SM 1 |
|
| 199 |
#define CP0C3_TL 0 |
|
| 157 | 200 |
uint32_t CP0_LLAddr; |
| 158 | 201 |
uint32_t CP0_WatchLo; |
| 159 | 202 |
uint32_t CP0_WatchHi; |
| 203 |
uint32_t CP0_XContext; |
|
| 204 |
uint32_t CP0_Framemask; |
|
| 160 | 205 |
uint32_t CP0_Debug; |
| 161 | 206 |
#define CPDB_DBD 31 |
| 162 | 207 |
#define CP0DB_DM 30 |
| ... | ... | |
| 177 | 222 |
#define CP0DB_DBp 1 |
| 178 | 223 |
#define CP0DB_DSS 0 |
| 179 | 224 |
uint32_t CP0_DEPC; |
| 225 |
uint32_t CP0_Performance0; |
|
| 180 | 226 |
uint32_t CP0_TagLo; |
| 181 | 227 |
uint32_t CP0_DataLo; |
| 228 |
uint32_t CP0_TagHi; |
|
| 229 |
uint32_t CP0_DataHi; |
|
| 182 | 230 |
uint32_t CP0_ErrorEPC; |
| 183 | 231 |
uint32_t CP0_DESAVE; |
| 184 | 232 |
/* Qemu */ |
| ... | ... | |
| 211 | 259 |
|
| 212 | 260 |
int halted; /* TRUE if the CPU is in suspend state */ |
| 213 | 261 |
|
| 262 |
int SYNCI_Step; /* Address step size for SYNCI */ |
|
| 263 |
int CCRes; /* Cycle count resolution/divisor */ |
|
| 264 |
|
|
| 214 | 265 |
CPU_COMMON |
| 215 | 266 |
|
| 216 | 267 |
int ram_size; |
| b/target-mips/exec.h | ||
|---|---|---|
| 68 | 68 |
#endif |
| 69 | 69 |
void do_mfc0_random(void); |
| 70 | 70 |
void do_mfc0_count(void); |
| 71 |
void do_mtc0_entryhi(uint32_t in); |
|
| 71 | 72 |
void do_mtc0_status_debug(uint32_t old, uint32_t val); |
| 72 | 73 |
void do_mtc0_status_irqraise_debug(void); |
| 73 | 74 |
void do_tlbwi (void); |
| b/target-mips/helper.c | ||
|---|---|---|
| 302 | 302 |
#endif |
| 303 | 303 |
env->CP0_Wired = 0; |
| 304 | 304 |
env->CP0_Config0 = MIPS_CONFIG0; |
| 305 |
#if defined (MIPS_CONFIG1) |
|
| 306 | 305 |
env->CP0_Config1 = MIPS_CONFIG1; |
| 307 |
#endif |
|
| 308 |
#if defined (MIPS_CONFIG2) |
|
| 309 | 306 |
env->CP0_Config2 = MIPS_CONFIG2; |
| 310 |
#endif |
|
| 311 |
#if defined (MIPS_CONFIG3) |
|
| 312 | 307 |
env->CP0_Config3 = MIPS_CONFIG3; |
| 313 |
#endif |
|
| 314 | 308 |
env->CP0_WatchLo = 0; |
| 315 | 309 |
env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV); |
| 316 | 310 |
goto set_error_EPC; |
| b/target-mips/mips-defs.h | ||
|---|---|---|
| 29 | 29 |
* Define a major version 1, minor version 0. |
| 30 | 30 |
*/ |
| 31 | 31 |
#define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0) |
| 32 |
/* Have config1, uses TLB */ |
|
| 33 |
#define MIPS_CONFIG0_1 \ |
|
| 34 |
((1 << CP0C0_M) | (0 << CP0C0_K23) | (0 << CP0C0_KU) | \ |
|
| 35 |
(1 << CP0C0_MT) | (2 << CP0C0_K0)) |
|
| 32 |
/* Have config1, is MIPS32R1, uses TLB, no virtual icache, |
|
| 33 |
uncached coherency */ |
|
| 34 |
#define MIPS_CONFIG0_1 \ |
|
| 35 |
((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \ |
|
| 36 |
(0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \ |
|
| 37 |
(0x2 << CP0C0_K0)) |
|
| 36 | 38 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 37 | 39 |
#define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE)) |
| 38 | 40 |
#else |
| 39 | 41 |
#define MIPS_CONFIG0 MIPS_CONFIG0_1 |
| 40 | 42 |
#endif |
| 41 |
/* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache, |
|
| 42 |
* 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache, |
|
| 43 |
* no performance counters, watch registers present, no code compression, |
|
| 44 |
* EJTAG present, FPU enable bit depending on MIPS_USES_FPU |
|
| 45 |
*/ |
|
| 46 |
#define MIPS_CONFIG1 \ |
|
| 47 |
((15 << CP0C1_MMU) | \ |
|
| 48 |
(0x000 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x01 << CP0C1_IA) | \ |
|
| 49 |
(0x000 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x01 << CP0C1_DA) | \ |
|
| 50 |
(0 << CP0C1_PC) | (1 << CP0C1_WR) | (0 << CP0C1_CA) | \ |
|
| 51 |
(1 << CP0C1_EP) | (MIPS_USES_FPU << CP0C1_FP)) |
|
| 43 |
/* Have config2, 16 TLB entries, 64 sets Icache, 16 bytes Icache line, |
|
| 44 |
2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache, |
|
| 45 |
no coprocessor2 attached, no MDMX support attached, |
|
| 46 |
no performance counters, watch registers present, |
|
| 47 |
no code compression, EJTAG present, FPU enable bit depending on |
|
| 48 |
MIPS_USES_FPU */ |
|
| 49 |
#define MIPS_CONFIG1_1 \ |
|
| 50 |
((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) | \ |
|
| 51 |
(0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \ |
|
| 52 |
(0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \ |
|
| 53 |
(0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ |
|
| 54 |
(1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP)) |
|
| 55 |
#ifdef MIPS_USES_FPU |
|
| 56 |
#define MIPS_CONFIG1 (MIPS_CONFIG1_1 | (1 << CP0C1_FP)) |
|
| 57 |
#else |
|
| 58 |
#define MIPS_CONFIG1 (MIPS_CONFIG1_1 | (0 << CP0C1_FP)) |
|
| 59 |
#endif |
|
| 60 |
/* Have config3, no tertiary/secondary caches implemented */ |
|
| 61 |
#define MIPS_CONFIG2 \ |
|
| 62 |
((1 << CP0C2_M)) |
|
| 63 |
/* No config4, no DSP ASE, no large physaddr, |
|
| 64 |
no external interrupt controller, no vectored interupts, |
|
| 65 |
no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */ |
|
| 66 |
#define MIPS_CONFIG3 \ |
|
| 67 |
((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ |
|
| 68 |
(0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ |
|
| 69 |
(0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL)) |
|
| 52 | 70 |
#elif (MIPS_CPU == MIPS_R4Kp) |
| 53 | 71 |
/* 32 bits target */ |
| 54 | 72 |
#define TARGET_LONG_BITS 32 |
| ... | ... | |
| 60 | 78 |
#define MIPS_USES_R4K_FPM |
| 61 | 79 |
#else |
| 62 | 80 |
#error "MIPS CPU not defined" |
| 63 |
/* Remainder for other flags */
|
|
| 81 |
/* Reminder for other flags */ |
|
| 64 | 82 |
//#define TARGET_MIPS64 |
| 65 | 83 |
//#define MIPS_USES_FPU |
| 66 | 84 |
#endif |
| b/target-mips/op.c | ||
|---|---|---|
| 437 | 437 |
RETURN(); |
| 438 | 438 |
} |
| 439 | 439 |
|
| 440 |
void op_rotr (void) |
|
| 441 |
{
|
|
| 442 |
target_ulong tmp; |
|
| 443 |
|
|
| 444 |
if (T1) {
|
|
| 445 |
tmp = T0 << (0x20 - T1); |
|
| 446 |
T0 = (T0 >> T1) | tmp; |
|
| 447 |
} else |
|
| 448 |
T0 = T1; |
|
| 449 |
RETURN(); |
|
| 450 |
} |
|
| 451 |
|
|
| 440 | 452 |
void op_sllv (void) |
| 441 | 453 |
{
|
| 442 | 454 |
T0 = T1 << (T0 & 0x1F); |
| ... | ... | |
| 455 | 467 |
RETURN(); |
| 456 | 468 |
} |
| 457 | 469 |
|
| 470 |
void op_rotrv (void) |
|
| 471 |
{
|
|
| 472 |
target_ulong tmp; |
|
| 473 |
|
|
| 474 |
T0 &= 0x1F; |
|
| 475 |
if (T0) {
|
|
| 476 |
tmp = T1 << (0x20 - T0); |
|
| 477 |
T0 = (T1 >> T0) | tmp; |
|
| 478 |
} else |
|
| 479 |
T0 = T1; |
|
| 480 |
RETURN(); |
|
| 481 |
} |
|
| 482 |
|
|
| 458 | 483 |
void op_clo (void) |
| 459 | 484 |
{
|
| 460 | 485 |
int n; |
| ... | ... | |
| 602 | 627 |
RETURN(); |
| 603 | 628 |
} |
| 604 | 629 |
|
| 630 |
void op_movf (void) |
|
| 631 |
{
|
|
| 632 |
if (!(env->fcr31 & PARAM1)) |
|
| 633 |
env->gpr[PARAM2] = env->gpr[PARAM3]; |
|
| 634 |
RETURN(); |
|
| 635 |
} |
|
| 636 |
|
|
| 637 |
void op_movt (void) |
|
| 638 |
{
|
|
| 639 |
if (env->fcr31 & PARAM1) |
|
| 640 |
env->gpr[PARAM2] = env->gpr[PARAM3]; |
|
| 641 |
RETURN(); |
|
| 642 |
} |
|
| 643 |
|
|
| 605 | 644 |
/* Tests */ |
| 606 | 645 |
#define OP_COND(name, cond) \ |
| 607 | 646 |
void glue(op_, name) (void) \ |
| ... | ... | |
| 625 | 664 |
OP_COND(lez, (int32_t)T0 <= 0); |
| 626 | 665 |
OP_COND(ltz, (int32_t)T0 < 0); |
| 627 | 666 |
|
| 628 |
/* Branchs */ |
|
| 667 |
/* Branches */
|
|
| 629 | 668 |
//#undef USE_DIRECT_JUMP |
| 630 | 669 |
|
| 631 | 670 |
void OPPROTO op_goto_tb0(void) |
| 632 | 671 |
{
|
| 633 | 672 |
GOTO_TB(op_goto_tb0, PARAM1, 0); |
| 673 |
RETURN(); |
|
| 634 | 674 |
} |
| 635 | 675 |
|
| 636 | 676 |
void OPPROTO op_goto_tb1(void) |
| 637 | 677 |
{
|
| 638 | 678 |
GOTO_TB(op_goto_tb1, PARAM1, 1); |
| 679 |
RETURN(); |
|
| 639 | 680 |
} |
| 640 | 681 |
|
| 641 | 682 |
/* Branch to register */ |
| 642 | 683 |
void op_save_breg_target (void) |
| 643 | 684 |
{
|
| 644 | 685 |
env->btarget = T2; |
| 686 |
RETURN(); |
|
| 645 | 687 |
} |
| 646 | 688 |
|
| 647 | 689 |
void op_restore_breg_target (void) |
| 648 | 690 |
{
|
| 649 | 691 |
T2 = env->btarget; |
| 692 |
RETURN(); |
|
| 650 | 693 |
} |
| 651 | 694 |
|
| 652 | 695 |
void op_breg (void) |
| ... | ... | |
| 724 | 767 |
RETURN(); |
| 725 | 768 |
} |
| 726 | 769 |
|
| 770 |
void op_mfc0_pagegrain (void) |
|
| 771 |
{
|
|
| 772 |
T0 = env->CP0_PageGrain; |
|
| 773 |
RETURN(); |
|
| 774 |
} |
|
| 775 |
|
|
| 727 | 776 |
void op_mfc0_wired (void) |
| 728 | 777 |
{
|
| 729 | 778 |
T0 = env->CP0_Wired; |
| 730 | 779 |
RETURN(); |
| 731 | 780 |
} |
| 732 | 781 |
|
| 782 |
void op_mfc0_hwrena (void) |
|
| 783 |
{
|
|
| 784 |
T0 = env->CP0_HWREna; |
|
| 785 |
RETURN(); |
|
| 786 |
} |
|
| 787 |
|
|
| 733 | 788 |
void op_mfc0_badvaddr (void) |
| 734 | 789 |
{
|
| 735 | 790 |
T0 = env->CP0_BadVAddr; |
| ... | ... | |
| 766 | 821 |
RETURN(); |
| 767 | 822 |
} |
| 768 | 823 |
|
| 824 |
void op_mfc0_intctl (void) |
|
| 825 |
{
|
|
| 826 |
T0 = env->CP0_IntCtl; |
|
| 827 |
RETURN(); |
|
| 828 |
} |
|
| 829 |
|
|
| 830 |
void op_mfc0_srsctl (void) |
|
| 831 |
{
|
|
| 832 |
T0 = env->CP0_SRSCtl; |
|
| 833 |
RETURN(); |
|
| 834 |
} |
|
| 835 |
|
|
| 769 | 836 |
void op_mfc0_cause (void) |
| 770 | 837 |
{
|
| 771 | 838 |
T0 = env->CP0_Cause; |
| ... | ... | |
| 784 | 851 |
RETURN(); |
| 785 | 852 |
} |
| 786 | 853 |
|
| 854 |
void op_mfc0_ebase (void) |
|
| 855 |
{
|
|
| 856 |
T0 = env->CP0_EBase; |
|
| 857 |
RETURN(); |
|
| 858 |
} |
|
| 859 |
|
|
| 787 | 860 |
void op_mfc0_config0 (void) |
| 788 | 861 |
{
|
| 789 | 862 |
T0 = env->CP0_Config0; |
| ... | ... | |
| 796 | 869 |
RETURN(); |
| 797 | 870 |
} |
| 798 | 871 |
|
| 872 |
void op_mfc0_config2 (void) |
|
| 873 |
{
|
|
| 874 |
T0 = env->CP0_Config2; |
|
| 875 |
RETURN(); |
|
| 876 |
} |
|
| 877 |
|
|
| 878 |
void op_mfc0_config3 (void) |
|
| 879 |
{
|
|
| 880 |
T0 = env->CP0_Config3; |
|
| 881 |
RETURN(); |
|
| 882 |
} |
|
| 883 |
|
|
| 799 | 884 |
void op_mfc0_lladdr (void) |
| 800 | 885 |
{
|
| 801 | 886 |
T0 = env->CP0_LLAddr >> 4; |
| 802 | 887 |
RETURN(); |
| 803 | 888 |
} |
| 804 | 889 |
|
| 805 |
void op_mfc0_watchlo (void) |
|
| 890 |
void op_mfc0_watchlo0 (void)
|
|
| 806 | 891 |
{
|
| 807 | 892 |
T0 = env->CP0_WatchLo; |
| 808 | 893 |
RETURN(); |
| 809 | 894 |
} |
| 810 | 895 |
|
| 811 |
void op_mfc0_watchhi (void) |
|
| 896 |
void op_mfc0_watchhi0 (void)
|
|
| 812 | 897 |
{
|
| 813 | 898 |
T0 = env->CP0_WatchHi; |
| 814 | 899 |
RETURN(); |
| 815 | 900 |
} |
| 816 | 901 |
|
| 902 |
void op_mfc0_xcontext (void) |
|
| 903 |
{
|
|
| 904 |
T0 = env->CP0_XContext; |
|
| 905 |
RETURN(); |
|
| 906 |
} |
|
| 907 |
|
|
| 908 |
void op_mfc0_framemask (void) |
|
| 909 |
{
|
|
| 910 |
T0 = env->CP0_Framemask; |
|
| 911 |
RETURN(); |
|
| 912 |
} |
|
| 913 |
|
|
| 817 | 914 |
void op_mfc0_debug (void) |
| 818 | 915 |
{
|
| 819 | 916 |
T0 = env->CP0_Debug; |
| ... | ... | |
| 828 | 925 |
RETURN(); |
| 829 | 926 |
} |
| 830 | 927 |
|
| 928 |
void op_mfc0_performance0 (void) |
|
| 929 |
{
|
|
| 930 |
T0 = env->CP0_Performance0; |
|
| 931 |
RETURN(); |
|
| 932 |
} |
|
| 933 |
|
|
| 831 | 934 |
void op_mfc0_taglo (void) |
| 832 | 935 |
{
|
| 833 | 936 |
T0 = env->CP0_TagLo; |
| ... | ... | |
| 840 | 943 |
RETURN(); |
| 841 | 944 |
} |
| 842 | 945 |
|
| 946 |
void op_mfc0_taghi (void) |
|
| 947 |
{
|
|
| 948 |
T0 = env->CP0_TagHi; |
|
| 949 |
RETURN(); |
|
| 950 |
} |
|
| 951 |
|
|
| 952 |
void op_mfc0_datahi (void) |
|
| 953 |
{
|
|
| 954 |
T0 = env->CP0_DataHi; |
|
| 955 |
RETURN(); |
|
| 956 |
} |
|
| 957 |
|
|
| 843 | 958 |
void op_mfc0_errorepc (void) |
| 844 | 959 |
{
|
| 845 | 960 |
T0 = env->CP0_ErrorEPC; |
| ... | ... | |
| 854 | 969 |
|
| 855 | 970 |
void op_mtc0_index (void) |
| 856 | 971 |
{
|
| 857 |
env->CP0_index = (env->CP0_index & 0x80000000) | (T0 & 0x0000000F);
|
|
| 972 |
env->CP0_index = (env->CP0_index & 0x80000000) | (T0 & (MIPS_TLB_NB - 1));
|
|
| 858 | 973 |
RETURN(); |
| 859 | 974 |
} |
| 860 | 975 |
|
| 861 | 976 |
void op_mtc0_entrylo0 (void) |
| 862 | 977 |
{
|
| 863 |
env->CP0_EntryLo0 = T0 & 0x3FFFFFFF; |
|
| 978 |
/* Large physaddr not implemented */ |
|
| 979 |
/* 1k pages not implemented */ |
|
| 980 |
env->CP0_EntryLo0 = T0 & 0x3FFFFFFFUL; |
|
| 864 | 981 |
RETURN(); |
| 865 | 982 |
} |
| 866 | 983 |
|
| 867 | 984 |
void op_mtc0_entrylo1 (void) |
| 868 | 985 |
{
|
| 869 |
env->CP0_EntryLo1 = T0 & 0x3FFFFFFF; |
|
| 986 |
/* Large physaddr not implemented */ |
|
| 987 |
/* 1k pages not implemented */ |
|
| 988 |
env->CP0_EntryLo1 = T0 & 0x3FFFFFFFUL; |
|
| 870 | 989 |
RETURN(); |
| 871 | 990 |
} |
| 872 | 991 |
|
| 873 | 992 |
void op_mtc0_context (void) |
| 874 | 993 |
{
|
| 875 |
env->CP0_Context = (env->CP0_Context & 0xFF800000) | (T0 & 0x007FFFF0);
|
|
| 994 |
env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
|
|
| 876 | 995 |
RETURN(); |
| 877 | 996 |
} |
| 878 | 997 |
|
| 879 | 998 |
void op_mtc0_pagemask (void) |
| 880 | 999 |
{
|
| 881 |
env->CP0_PageMask = T0 & 0x01FFE000; |
|
| 1000 |
/* 1k pages not implemented */ |
|
| 1001 |
env->CP0_PageMask = T0 & 0x1FFFE000; |
|
| 1002 |
RETURN(); |
|
| 1003 |
} |
|
| 1004 |
|
|
| 1005 |
void op_mtc0_pagegrain (void) |
|
| 1006 |
{
|
|
| 1007 |
/* SmartMIPS not implemented */ |
|
| 1008 |
/* Large physaddr not implemented */ |
|
| 1009 |
/* 1k pages not implemented */ |
|
| 1010 |
env->CP0_PageGrain = 0; |
|
| 882 | 1011 |
RETURN(); |
| 883 | 1012 |
} |
| 884 | 1013 |
|
| 885 | 1014 |
void op_mtc0_wired (void) |
| 886 | 1015 |
{
|
| 887 |
env->CP0_Wired = T0 & 0x0000000F; |
|
| 1016 |
env->CP0_Wired = T0 & (MIPS_TLB_NB - 1); |
|
| 1017 |
RETURN(); |
|
| 1018 |
} |
|
| 1019 |
|
|
| 1020 |
void op_mtc0_hwrena (void) |
|
| 1021 |
{
|
|
| 1022 |
env->CP0_HWREna = T0 & 0x0000000F; |
|
| 888 | 1023 |
RETURN(); |
| 889 | 1024 |
} |
| 890 | 1025 |
|
| ... | ... | |
| 898 | 1033 |
{
|
| 899 | 1034 |
uint32_t old, val; |
| 900 | 1035 |
|
| 1036 |
/* 1k pages not implemented */ |
|
| 1037 |
/* Ignore MIPS64 TLB for now */ |
|
| 901 | 1038 |
val = T0 & 0xFFFFE0FF; |
| 902 | 1039 |
old = env->CP0_EntryHi; |
| 903 | 1040 |
env->CP0_EntryHi = val; |
| ... | ... | |
| 950 | 1087 |
RETURN(); |
| 951 | 1088 |
} |
| 952 | 1089 |
|
| 1090 |
void op_mtc0_intctl (void) |
|
| 1091 |
{
|
|
| 1092 |
/* vectored interrupts not implemented */ |
|
| 1093 |
env->CP0_IntCtl = 0; |
|
| 1094 |
RETURN(); |
|
| 1095 |
} |
|
| 1096 |
|
|
| 1097 |
void op_mtc0_srsctl (void) |
|
| 1098 |
{
|
|
| 1099 |
/* shadow registers not implemented */ |
|
| 1100 |
env->CP0_SRSCtl = 0; |
|
| 1101 |
RETURN(); |
|
| 1102 |
} |
|
| 1103 |
|
|
| 953 | 1104 |
void op_mtc0_cause (void) |
| 954 | 1105 |
{
|
| 955 | 1106 |
uint32_t val, old; |
| ... | ... | |
| 960 | 1111 |
#if 0 |
| 961 | 1112 |
{
|
| 962 | 1113 |
int i, mask; |
| 963 |
|
|
| 964 | 1114 |
/* Check if we ever asserted a software IRQ */ |
| 965 | 1115 |
for (i = 0; i < 2; i++) {
|
| 966 | 1116 |
mask = 0x100 << i; |
| ... | ... | |
| 978 | 1128 |
RETURN(); |
| 979 | 1129 |
} |
| 980 | 1130 |
|
| 1131 |
void op_mtc0_ebase (void) |
|
| 1132 |
{
|
|
| 1133 |
/* vectored interrupts not implemented */ |
|
| 1134 |
/* Multi-CPU not implemented */ |
|
| 1135 |
env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000); |
|
| 1136 |
RETURN(); |
|
| 1137 |
} |
|
| 1138 |
|
|
| 981 | 1139 |
void op_mtc0_config0 (void) |
| 982 | 1140 |
{
|
| 983 | 1141 |
#if defined(MIPS_USES_R4K_TLB) |
| 984 |
env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF80) | (T0 & 0x7E000001); |
|
| 1142 |
/* Fixed mapping MMU not implemented */ |
|
| 1143 |
env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF88) | (T0 & 0x00000001); |
|
| 985 | 1144 |
#else |
| 986 |
env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF80) | (T0 & 0x00000001);
|
|
| 1145 |
env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF88) | (T0 & 0x00000001);
|
|
| 987 | 1146 |
#endif |
| 988 | 1147 |
RETURN(); |
| 989 | 1148 |
} |
| 990 | 1149 |
|
| 991 |
void op_mtc0_watchlo (void) |
|
| 1150 |
void op_mtc0_config2 (void) |
|
| 1151 |
{
|
|
| 1152 |
/* tertiary/secondary caches not implemented */ |
|
| 1153 |
env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); |
|
| 1154 |
RETURN(); |
|
| 1155 |
} |
|
| 1156 |
|
|
| 1157 |
void op_mtc0_watchlo0 (void) |
|
| 992 | 1158 |
{
|
| 993 | 1159 |
env->CP0_WatchLo = T0; |
| 994 | 1160 |
RETURN(); |
| 995 | 1161 |
} |
| 996 | 1162 |
|
| 997 |
void op_mtc0_watchhi (void) |
|
| 1163 |
void op_mtc0_watchhi0 (void)
|
|
| 998 | 1164 |
{
|
| 999 | 1165 |
env->CP0_WatchHi = T0 & 0x40FF0FF8; |
| 1000 | 1166 |
RETURN(); |
| 1001 | 1167 |
} |
| 1002 | 1168 |
|
| 1169 |
void op_mtc0_xcontext (void) |
|
| 1170 |
{
|
|
| 1171 |
env->CP0_XContext = T0; /* XXX */ |
|
| 1172 |
RETURN(); |
|
| 1173 |
} |
|
| 1174 |
|
|
| 1175 |
void op_mtc0_framemask (void) |
|
| 1176 |
{
|
|
| 1177 |
env->CP0_Framemask = T0; /* XXX */ |
|
| 1178 |
RETURN(); |
|
| 1179 |
} |
|
| 1180 |
|
|
| 1003 | 1181 |
void op_mtc0_debug (void) |
| 1004 | 1182 |
{
|
| 1005 | 1183 |
env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); |
| ... | ... | |
| 1016 | 1194 |
RETURN(); |
| 1017 | 1195 |
} |
| 1018 | 1196 |
|
| 1197 |
void op_mtc0_performance0 (void) |
|
| 1198 |
{
|
|
| 1199 |
env->CP0_Performance0 = T0; /* XXX */ |
|
| 1200 |
RETURN(); |
|
| 1201 |
} |
|
| 1202 |
|
|
| 1019 | 1203 |
void op_mtc0_taglo (void) |
| 1020 | 1204 |
{
|
| 1021 | 1205 |
env->CP0_TagLo = T0 & 0xFFFFFCF6; |
| 1022 | 1206 |
RETURN(); |
| 1023 | 1207 |
} |
| 1024 | 1208 |
|
| 1209 |
void op_mtc0_datalo (void) |
|
| 1210 |
{
|
|
| 1211 |
env->CP0_DataLo = T0; /* XXX */ |
|
| 1212 |
RETURN(); |
|
| 1213 |
} |
|
| 1214 |
|
|
| 1215 |
void op_mtc0_taghi (void) |
|
| 1216 |
{
|
|
| 1217 |
env->CP0_TagHi = T0; /* XXX */ |
|
| 1218 |
RETURN(); |
|
| 1219 |
} |
|
| 1220 |
|
|
| 1221 |
void op_mtc0_datahi (void) |
|
| 1222 |
{
|
|
| 1223 |
env->CP0_DataHi = T0; /* XXX */ |
|
| 1224 |
RETURN(); |
|
| 1225 |
} |
|
| 1226 |
|
|
| 1025 | 1227 |
void op_mtc0_errorepc (void) |
| 1026 | 1228 |
{
|
| 1027 | 1229 |
env->CP0_ErrorEPC = T0; |
| ... | ... | |
| 1422 | 1624 |
void op_pmon (void) |
| 1423 | 1625 |
{
|
| 1424 | 1626 |
CALL_FROM_TB1(do_pmon, PARAM1); |
| 1627 |
RETURN(); |
|
| 1628 |
} |
|
| 1629 |
|
|
| 1630 |
void op_di (void) |
|
| 1631 |
{
|
|
| 1632 |
uint32_t val; |
|
| 1633 |
|
|
| 1634 |
T0 = env->CP0_Status; |
|
| 1635 |
val = T0 & ~(1 << CP0St_IE); |
|
| 1636 |
if (val != T0) {
|
|
| 1637 |
env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
|
| 1638 |
env->CP0_Status = val; |
|
| 1639 |
} |
|
| 1640 |
RETURN(); |
|
| 1641 |
} |
|
| 1642 |
|
|
| 1643 |
void op_ei (void) |
|
| 1644 |
{
|
|
| 1645 |
uint32_t val; |
|
| 1646 |
|
|
| 1647 |
T0 = env->CP0_Status; |
|
| 1648 |
val = T0 | (1 << CP0St_IE); |
|
| 1649 |
if (val != T0) {
|
|
| 1650 |
const uint32_t mask = 0x0000FF00; |
|
| 1651 |
|
|
| 1652 |
env->CP0_Status = val; |
|
| 1653 |
if (!(env->hflags & MIPS_HFLAG_EXL) && |
|
| 1654 |
!(env->hflags & MIPS_HFLAG_ERL) && |
|
| 1655 |
!(env->hflags & MIPS_HFLAG_DM) && |
|
| 1656 |
(env->CP0_Status & env->CP0_Cause & mask)) {
|
|
| 1657 |
env->interrupt_request |= CPU_INTERRUPT_HARD; |
|
| 1658 |
if (logfile) |
|
| 1659 |
CALL_FROM_TB0(do_mtc0_status_irqraise_debug); |
|
| 1660 |
} |
|
| 1661 |
} |
|
| 1662 |
RETURN(); |
|
| 1425 | 1663 |
} |
| 1426 | 1664 |
|
| 1427 | 1665 |
void op_trap (void) |
| ... | ... | |
| 1434 | 1672 |
|
| 1435 | 1673 |
void op_debug (void) |
| 1436 | 1674 |
{
|
| 1437 |
CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG); |
|
| 1675 |
CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG); |
|
| 1676 |
RETURN(); |
|
| 1438 | 1677 |
} |
| 1439 | 1678 |
|
| 1440 | 1679 |
void op_set_lladdr (void) |
| 1441 | 1680 |
{
|
| 1442 | 1681 |
env->CP0_LLAddr = T2; |
| 1682 |
RETURN(); |
|
| 1443 | 1683 |
} |
| 1444 | 1684 |
|
| 1445 | 1685 |
void debug_eret (void); |
| ... | ... | |
| 1456 | 1696 |
env->CP0_Status &= ~(1 << CP0St_EXL); |
| 1457 | 1697 |
} |
| 1458 | 1698 |
env->CP0_LLAddr = 1; |
| 1699 |
RETURN(); |
|
| 1459 | 1700 |
} |
| 1460 | 1701 |
|
| 1461 | 1702 |
void op_deret (void) |
| 1462 | 1703 |
{
|
| 1463 | 1704 |
CALL_FROM_TB0(debug_eret); |
| 1464 | 1705 |
env->PC = env->CP0_DEPC; |
| 1706 |
RETURN(); |
|
| 1707 |
} |
|
| 1708 |
|
|
| 1709 |
void op_rdhwr_cpunum(void) |
|
| 1710 |
{
|
|
| 1711 |
if (env->CP0_HWREna & (1 << 0)) |
|
| 1712 |
T0 = env->CP0_EBase & 0x2ff; |
|
| 1713 |
else |
|
| 1714 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI); |
|
| 1715 |
RETURN(); |
|
| 1716 |
} |
|
| 1717 |
|
|
| 1718 |
void op_rdhwr_synci_step(void) |
|
| 1719 |
{
|
|
| 1720 |
if (env->CP0_HWREna & (1 << 1)) |
|
| 1721 |
T0 = env->SYNCI_Step; |
|
| 1722 |
else |
|
| 1723 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI); |
|
| 1724 |
RETURN(); |
|
| 1725 |
} |
|
| 1726 |
|
|
| 1727 |
void op_rdhwr_cc(void) |
|
| 1728 |
{
|
|
| 1729 |
if (env->CP0_HWREna & (1 << 2)) |
|
| 1730 |
T0 = env->CP0_Count; |
|
| 1731 |
else |
|
| 1732 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI); |
|
| 1733 |
RETURN(); |
|
| 1734 |
} |
|
| 1735 |
|
|
| 1736 |
void op_rdhwr_ccres(void) |
|
| 1737 |
{
|
|
| 1738 |
if (env->CP0_HWREna & (1 << 3)) |
|
| 1739 |
T0 = env->CCRes; |
|
| 1740 |
else |
|
| 1741 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI); |
|
| 1742 |
RETURN(); |
|
| 1465 | 1743 |
} |
| 1466 | 1744 |
|
| 1467 | 1745 |
void op_save_state (void) |
| ... | ... | |
| 1491 | 1769 |
void op_exit_tb (void) |
| 1492 | 1770 |
{
|
| 1493 | 1771 |
EXIT_TB(); |
| 1772 |
RETURN(); |
|
| 1494 | 1773 |
} |
| 1495 | 1774 |
|
| 1496 | 1775 |
void op_wait (void) |
| 1497 | 1776 |
{
|
| 1498 | 1777 |
env->halted = 1; |
| 1499 | 1778 |
CALL_FROM_TB1(do_raise_exception, EXCP_HLT); |
| 1779 |
RETURN(); |
|
| 1780 |
} |
|
| 1781 |
|
|
| 1782 |
/* Bitfield operations. */ |
|
| 1783 |
void op_ext(void) |
|
| 1784 |
{
|
|
| 1785 |
unsigned int pos = PARAM1; |
|
| 1786 |
unsigned int size = PARAM2; |
|
| 1787 |
|
|
| 1788 |
T0 = (T1 >> pos) & ((1 << size) - 1); |
|
| 1789 |
RETURN(); |
|
| 1790 |
} |
|
| 1791 |
|
|
| 1792 |
void op_ins(void) |
|
| 1793 |
{
|
|
| 1794 |
unsigned int pos = PARAM1; |
|
| 1795 |
unsigned int size = PARAM2; |
|
| 1796 |
target_ulong mask = ((1 << size) - 1) << pos; |
|
| 1797 |
|
|
| 1798 |
T0 = (T2 & ~mask) | ((T1 << pos) & mask); |
|
| 1799 |
RETURN(); |
|
| 1800 |
} |
|
| 1801 |
|
|
| 1802 |
void op_wsbh(void) |
|
| 1803 |
{
|
|
| 1804 |
T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF); |
|
| 1805 |
RETURN(); |
|
| 1806 |
} |
|
| 1807 |
|
|
| 1808 |
void op_dsbh(void) |
|
| 1809 |
{
|
|
| 1810 |
T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL); |
|
| 1811 |
RETURN(); |
|
| 1812 |
} |
|
| 1813 |
|
|
| 1814 |
void op_dshd(void) |
|
| 1815 |
{
|
|
| 1816 |
T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL); |
|
| 1817 |
RETURN(); |
|
| 1818 |
} |
|
| 1819 |
|
|
| 1820 |
void op_seb(void) |
|
| 1821 |
{
|
|
| 1822 |
T0 = ((T1 & 0xFF) ^ 0x80) - 0x80; |
|
| 1823 |
RETURN(); |
|
| 1824 |
} |
|
| 1825 |
|
|
| 1826 |
void op_seh(void) |
|
| 1827 |
{
|
|
| 1828 |
T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000; |
|
| 1829 |
RETURN(); |
|
| 1500 | 1830 |
} |
| b/target-mips/op_helper.c | ||
|---|---|---|
| 153 | 153 |
|
| 154 | 154 |
void do_mtc0_status_debug(uint32_t old, uint32_t val) |
| 155 | 155 |
{
|
| 156 |
cpu_abort(env, "mtc0 status\n"); |
|
| 156 |
cpu_abort(env, "mtc0 status debug\n");
|
|
| 157 | 157 |
} |
| 158 | 158 |
|
| 159 |
void do_mtc0_status_irqraise_debug(void) |
|
| 159 |
void do_mtc0_status_irqraise_debug (void)
|
|
| 160 | 160 |
{
|
| 161 |
cpu_abort(env, "mtc0 status\n"); |
|
| 161 |
cpu_abort(env, "mtc0 status irqraise debug\n");
|
|
| 162 | 162 |
} |
| 163 | 163 |
|
| 164 | 164 |
void do_tlbwi (void) |
| b/target-mips/translate.c | ||
|---|---|---|
| 50 | 50 |
|
| 51 | 51 |
#include "gen-op.h" |
| 52 | 52 |
|
| 53 |
/* MIPS opcodes */ |
|
| 54 |
#define EXT_SPECIAL 0x100 |
|
| 55 |
#define EXT_SPECIAL2 0x200 |
|
| 56 |
#define EXT_REGIMM 0x300 |
|
| 57 |
#define EXT_CP0 0x400 |
|
| 58 |
#define EXT_CP1 0x500 |
|
| 59 |
#define EXT_CP2 0x600 |
|
| 60 |
#define EXT_CP3 0x700 |
|
| 53 |
/* MIPS major opcodes */ |
|
| 54 |
#define MASK_OP_MAJOR(op) (op & (0x3F << 26)) |
|
| 61 | 55 |
|
| 62 | 56 |
enum {
|
| 63 | 57 |
/* indirect opcode tables */ |
| 64 |
OPC_SPECIAL = 0x00, |
|
| 65 |
OPC_BREGIMM = 0x01, |
|
| 66 |
OPC_CP0 = 0x10, |
|
| 67 |
OPC_CP1 = 0x11, |
|
| 68 |
OPC_CP2 = 0x12, |
|
| 69 |
OPC_CP3 = 0x13, |
|
| 70 |
OPC_SPECIAL2 = 0x1C, |
|
| 58 |
OPC_SPECIAL = (0x00 << 26), |
|
| 59 |
OPC_REGIMM = (0x01 << 26), |
|
| 60 |
OPC_CP0 = (0x10 << 26), |
|
| 61 |
OPC_CP1 = (0x11 << 26), |
|
| 62 |
OPC_CP2 = (0x12 << 26), |
|
| 63 |
OPC_CP3 = (0x13 << 26), |
|
| 64 |
OPC_SPECIAL2 = (0x1C << 26), |
|
| 65 |
OPC_SPECIAL3 = (0x1F << 26), |
|
| 71 | 66 |
/* arithmetic with immediate */ |
| 72 |
OPC_ADDI = 0x08, |
|
| 73 |
OPC_ADDIU = 0x09, |
|
| 74 |
OPC_SLTI = 0x0A, |
|
| 75 |
OPC_SLTIU = 0x0B, |
|
| 76 |
OPC_ANDI = 0x0C, |
|
| 77 |
OPC_ORI = 0x0D, |
|
| 78 |
OPC_XORI = 0x0E, |
|
| 79 |
OPC_LUI = 0x0F, |
|
| 67 |
OPC_ADDI = (0x08 << 26), |
|
| 68 |
OPC_ADDIU = (0x09 << 26), |
|
| 69 |
OPC_SLTI = (0x0A << 26), |
|
| 70 |
OPC_SLTIU = (0x0B << 26), |
|
| 71 |
OPC_ANDI = (0x0C << 26), |
|
| 72 |
OPC_ORI = (0x0D << 26), |
|
| 73 |
OPC_XORI = (0x0E << 26), |
|
| 74 |
OPC_LUI = (0x0F << 26), |
|
| 75 |
OPC_DADDI = (0x18 << 26), |
|
| 76 |
OPC_DADDIU = (0x19 << 26), |
|
| 80 | 77 |
/* Jump and branches */ |
| 81 |
OPC_J = 0x02,
|
|
| 82 |
OPC_JAL = 0x03,
|
|
| 83 |
OPC_BEQ = 0x04, /* Unconditional if rs = rt = 0 (B) */
|
|
| 84 |
OPC_BEQL = 0x14,
|
|
| 85 |
OPC_BNE = 0x05,
|
|
| 86 |
OPC_BNEL = 0x15,
|
|
| 87 |
OPC_BLEZ = 0x06,
|
|
| 88 |
OPC_BLEZL = 0x16,
|
|
| 89 |
OPC_BGTZ = 0x07,
|
|
| 90 |
OPC_BGTZL = 0x17,
|
|
| 91 |
OPC_JALX = 0x1D, /* MIPS 16 only */
|
|
| 78 |
OPC_J = (0x02 << 26),
|
|
| 79 |
OPC_JAL = (0x03 << 26),
|
|
| 80 |
OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
|
|
| 81 |
OPC_BEQL = (0x14 << 26),
|
|
| 82 |
OPC_BNE = (0x05 << 26),
|
|
| 83 |
OPC_BNEL = (0x15 << 26),
|
|
| 84 |
OPC_BLEZ = (0x06 << 26),
|
|
| 85 |
OPC_BLEZL = (0x16 << 26),
|
|
| 86 |
OPC_BGTZ = (0x07 << 26),
|
|
| 87 |
OPC_BGTZL = (0x17 << 26),
|
|
| 88 |
OPC_JALX = (0x1D << 26), /* MIPS 16 only */
|
|
| 92 | 89 |
/* Load and stores */ |
| 93 |
OPC_LB = 0x20, |
|
| 94 |
OPC_LH = 0x21, |
|
| 95 |
OPC_LWL = 0x22, |
|
| 96 |
OPC_LW = 0x23, |
|
| 97 |
OPC_LBU = 0x24, |
|
| 98 |
OPC_LHU = 0x25, |
|
| 99 |
OPC_LWR = 0x26, |
|
| 100 |
OPC_LWU = 0x27, |
|
| 101 |
OPC_SB = 0x28, |
|
| 102 |
OPC_SH = 0x29, |
|
| 103 |
OPC_SWL = 0x2A, |
|
| 104 |
OPC_SW = 0x2B, |
|
| 105 |
OPC_SWR = 0x2E, |
|
| 106 |
OPC_LL = 0x30, |
|
| 107 |
OPC_SC = 0x38, |
|
| 90 |
OPC_LDL = (0x1A << 26), |
|
| 91 |
OPC_LDR = (0x1B << 26), |
|
| 92 |
OPC_LB = (0x20 << 26), |
|
| 93 |
OPC_LH = (0x21 << 26), |
|
| 94 |
OPC_LWL = (0x22 << 26), |
|
| 95 |
OPC_LW = (0x23 << 26), |
|
| 96 |
OPC_LBU = (0x24 << 26), |
|
| 97 |
OPC_LHU = (0x25 << 26), |
|
| 98 |
OPC_LWR = (0x26 << 26), |
|
| 99 |
OPC_LWU = (0x27 << 26), |
|
| 100 |
OPC_SB = (0x28 << 26), |
|
| 101 |
OPC_SH = (0x29 << 26), |
|
| 102 |
OPC_SWL = (0x2A << 26), |
|
| 103 |
OPC_SW = (0x2B << 26), |
|
| 104 |
OPC_SDL = (0x2C << 26), |
|
| 105 |
OPC_SDR = (0x2D << 26), |
|
| 106 |
OPC_SWR = (0x2E << 26), |
|
| 107 |
OPC_LL = (0x30 << 26), |
|
| 108 |
OPC_LLD = (0x34 << 26), |
|
| 109 |
OPC_LD = (0x37 << 26), |
|
| 110 |
OPC_SC = (0x38 << 26), |
|
| 111 |
OPC_SCD = (0x3C << 26), |
|
| 112 |
OPC_SD = (0x3F << 26), |
|
| 108 | 113 |
/* Floating point load/store */ |
| 109 |
OPC_LWC1 = 0x31, |
|
| 110 |
OPC_LWC2 = 0x32, |
|
| 111 |
OPC_LDC1 = 0x35, |
|
| 112 |
OPC_LDC2 = 0x36, |
|
| 113 |
OPC_SWC1 = 0x39, |
|
| 114 |
OPC_SWC2 = 0x3A, |
|
| 115 |
OPC_SDC1 = 0x3D, |
|
| 116 |
OPC_SDC2 = 0x3E, |
|
| 114 |
OPC_LWC1 = (0x31 << 26), |
|
| 115 |
OPC_LWC2 = (0x32 << 26), |
|
| 116 |
OPC_LDC1 = (0x35 << 26), |
|
| 117 |
OPC_LDC2 = (0x36 << 26), |
|
| 118 |
OPC_SWC1 = (0x39 << 26), |
|
| 119 |
OPC_SWC2 = (0x3A << 26), |
|
| 120 |
OPC_SDC1 = (0x3D << 26), |
|
| 121 |
OPC_SDC2 = (0x3E << 26), |
|
| 122 |
/* MDMX ASE specific */ |
|
| 123 |
OPC_MDMX = (0x1E << 26), |
|
| 117 | 124 |
/* Cache and prefetch */ |
| 118 |
OPC_CACHE = 0x2F, |
|
| 119 |
OPC_PREF = 0x33, |
|
| 125 |
OPC_CACHE = (0x2F << 26), |
|
| 126 |
OPC_PREF = (0x33 << 26), |
|
| 127 |
/* Reserved major opcode */ |
|
| 128 |
OPC_MAJOR3B_RESERVED = (0x3B << 26), |
|
| 120 | 129 |
}; |
| 121 | 130 |
|
| 122 | 131 |
/* MIPS special opcodes */ |
| 132 |
#define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F) |
|
| 133 |
|
|
| 123 | 134 |
enum {
|
| 124 | 135 |
/* Shifts */ |
| 125 |
OPC_SLL = 0x00 | EXT_SPECIAL,
|
|
| 136 |
OPC_SLL = 0x00 | OPC_SPECIAL,
|
|
| 126 | 137 |
/* NOP is SLL r0, r0, 0 */ |
| 127 | 138 |
/* SSNOP is SLL r0, r0, 1 */ |
| 128 |
OPC_SRL = 0x02 | EXT_SPECIAL, |
|
| 129 |
OPC_SRA = 0x03 | EXT_SPECIAL, |
|
| 130 |
OPC_SLLV = 0x04 | EXT_SPECIAL, |
|
| 131 |
OPC_SRLV = 0x06 | EXT_SPECIAL, |
|
| 132 |
OPC_SRAV = 0x07 | EXT_SPECIAL, |
|
| 139 |
/* EHB is SLL r0, r0, 3 */ |
|
| 140 |
OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */ |
|
| 141 |
OPC_SRA = 0x03 | OPC_SPECIAL, |
|
| 142 |
OPC_SLLV = 0x04 | OPC_SPECIAL, |
|
| 143 |
OPC_SRLV = 0x06 | OPC_SPECIAL, |
|
| 144 |
OPC_SRAV = 0x07 | OPC_SPECIAL, |
|
| 145 |
OPC_DSLLV = 0x14 | OPC_SPECIAL, |
|
| 146 |
OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */ |
|
| 147 |
OPC_DSRAV = 0x17 | OPC_SPECIAL, |
|
| 148 |
OPC_DSLL = 0x38 | OPC_SPECIAL, |
|
| 149 |
OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */ |
|
| 150 |
OPC_DSRA = 0x3B | OPC_SPECIAL, |
|
| 151 |
OPC_DSLL32 = 0x3C | OPC_SPECIAL, |
|
| 152 |
OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */ |
|
| 153 |
OPC_DSRA32 = 0x3F | OPC_SPECIAL, |
|
| 133 | 154 |
/* Multiplication / division */ |
| 134 |
OPC_MULT = 0x18 | EXT_SPECIAL, |
|
| 135 |
OPC_MULTU = 0x19 | EXT_SPECIAL, |
|
| 136 |
OPC_DIV = 0x1A | EXT_SPECIAL, |
|
| 137 |
OPC_DIVU = 0x1B | EXT_SPECIAL, |
|
| 155 |
OPC_MULT = 0x18 | OPC_SPECIAL, |
|
| 156 |
OPC_MULTU = 0x19 | OPC_SPECIAL, |
|
| 157 |
OPC_DIV = 0x1A | OPC_SPECIAL, |
|
| 158 |
OPC_DIVU = 0x1B | OPC_SPECIAL, |
|
| 159 |
OPC_DMULT = 0x1C | OPC_SPECIAL, |
|
| 160 |
OPC_DMULTU = 0x1D | OPC_SPECIAL, |
|
| 161 |
OPC_DDIV = 0x1E | OPC_SPECIAL, |
|
| 162 |
OPC_DDIVU = 0x1F | OPC_SPECIAL, |
|
| 138 | 163 |
/* 2 registers arithmetic / logic */ |
| 139 |
OPC_ADD = 0x20 | EXT_SPECIAL, |
|
| 140 |
OPC_ADDU = 0x21 | EXT_SPECIAL, |
|
| 141 |
OPC_SUB = 0x22 | EXT_SPECIAL, |
|
| 142 |
OPC_SUBU = 0x23 | EXT_SPECIAL, |
|
| 143 |
OPC_AND = 0x24 | EXT_SPECIAL, |
|
| 144 |
OPC_OR = 0x25 | EXT_SPECIAL, |
|
| 145 |
OPC_XOR = 0x26 | EXT_SPECIAL, |
|
| 146 |
OPC_NOR = 0x27 | EXT_SPECIAL, |
|
| 147 |
OPC_SLT = 0x2A | EXT_SPECIAL, |
|
| 148 |
OPC_SLTU = 0x2B | EXT_SPECIAL, |
|
| 164 |
OPC_ADD = 0x20 | OPC_SPECIAL, |
|
| 165 |
OPC_ADDU = 0x21 | OPC_SPECIAL, |
|
| 166 |
OPC_SUB = 0x22 | OPC_SPECIAL, |
|
| 167 |
OPC_SUBU = 0x23 | OPC_SPECIAL, |
|
| 168 |
OPC_AND = 0x24 | OPC_SPECIAL, |
|
| 169 |
OPC_OR = 0x25 | OPC_SPECIAL, |
|
| 170 |
OPC_XOR = 0x26 | OPC_SPECIAL, |
|
| 171 |
OPC_NOR = 0x27 | OPC_SPECIAL, |
|
| 172 |
OPC_SLT = 0x2A | OPC_SPECIAL, |
|
| 173 |
OPC_SLTU = 0x2B | OPC_SPECIAL, |
|
| 174 |
OPC_DADD = 0x2C | OPC_SPECIAL, |
|
| 175 |
OPC_DADDU = 0x2D | OPC_SPECIAL, |
|
| 176 |
OPC_DSUB = 0x2E | OPC_SPECIAL, |
|
| 177 |
OPC_DSUBU = 0x2F | OPC_SPECIAL, |
|
| 149 | 178 |
/* Jumps */ |
| 150 |
OPC_JR = 0x08 | EXT_SPECIAL,
|
|
| 151 |
OPC_JALR = 0x09 | EXT_SPECIAL,
|
|
| 179 |
OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */
|
|
| 180 |
OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */
|
|
| 152 | 181 |
/* Traps */ |
| 153 |
OPC_TGE = 0x30 | EXT_SPECIAL,
|
|
| 154 |
OPC_TGEU = 0x31 | EXT_SPECIAL,
|
|
| 155 |
OPC_TLT = 0x32 | EXT_SPECIAL,
|
|
| 156 |
OPC_TLTU = 0x33 | EXT_SPECIAL,
|
|
| 157 |
OPC_TEQ = 0x34 | EXT_SPECIAL,
|
|
| 158 |
OPC_TNE = 0x36 | EXT_SPECIAL,
|
|
| 182 |
OPC_TGE = 0x30 | OPC_SPECIAL,
|
|
| 183 |
OPC_TGEU = 0x31 | OPC_SPECIAL,
|
|
| 184 |
OPC_TLT = 0x32 | OPC_SPECIAL,
|
|
| 185 |
OPC_TLTU = 0x33 | OPC_SPECIAL,
|
|
| 186 |
OPC_TEQ = 0x34 | OPC_SPECIAL,
|
|
| 187 |
OPC_TNE = 0x36 | OPC_SPECIAL,
|
|
| 159 | 188 |
/* HI / LO registers load & stores */ |
| 160 |
OPC_MFHI = 0x10 | EXT_SPECIAL,
|
|
| 161 |
OPC_MTHI = 0x11 | EXT_SPECIAL,
|
|
| 162 |
OPC_MFLO = 0x12 | EXT_SPECIAL,
|
|
| 163 |
OPC_MTLO = 0x13 | EXT_SPECIAL,
|
|
| 189 |
OPC_MFHI = 0x10 | OPC_SPECIAL,
|
|
| 190 |
OPC_MTHI = 0x11 | OPC_SPECIAL,
|
|
| 191 |
OPC_MFLO = 0x12 | OPC_SPECIAL,
|
|
| 192 |
OPC_MTLO = 0x13 | OPC_SPECIAL,
|
|
| 164 | 193 |
/* Conditional moves */ |
| 165 |
OPC_MOVZ = 0x0A | EXT_SPECIAL,
|
|
| 166 |
OPC_MOVN = 0x0B | EXT_SPECIAL,
|
|
| 194 |
OPC_MOVZ = 0x0A | OPC_SPECIAL,
|
|
| 195 |
OPC_MOVN = 0x0B | OPC_SPECIAL,
|
|
| 167 | 196 |
|
| 168 |
OPC_MOVCI = 0x01 | EXT_SPECIAL,
|
|
| 197 |
OPC_MOVCI = 0x01 | OPC_SPECIAL,
|
|
| 169 | 198 |
|
| 170 | 199 |
/* Special */ |
| 171 |
OPC_PMON = 0x05 | EXT_SPECIAL, |
|
| 172 |
OPC_SYSCALL = 0x0C | EXT_SPECIAL, |
|
| 173 |
OPC_BREAK = 0x0D | EXT_SPECIAL, |
|
| 174 |
OPC_SYNC = 0x0F | EXT_SPECIAL, |
|
| 200 |
OPC_PMON = 0x05 | OPC_SPECIAL, /* inofficial */ |
|
| 201 |
OPC_SYSCALL = 0x0C | OPC_SPECIAL, |
|
| 202 |
OPC_BREAK = 0x0D | OPC_SPECIAL, |
|
| 203 |
OPC_SPIM = 0x0E | OPC_SPECIAL, /* inofficial */ |
|
| 204 |
OPC_SYNC = 0x0F | OPC_SPECIAL, |
|
| 205 |
|
|
| 206 |
OPC_SPECIAL15_RESERVED = 0x15 | OPC_SPECIAL, |
|
| 207 |
OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL, |
|
| 208 |
OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL, |
|
| 209 |
OPC_SPECIAL35_RESERVED = 0x35 | OPC_SPECIAL, |
|
| 210 |
OPC_SPECIAL37_RESERVED = 0x37 | OPC_SPECIAL, |
|
| 211 |
OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL, |
|
| 212 |
OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL, |
|
| 213 |
}; |
|
| 214 |
|
|
| 215 |
/* REGIMM (rt field) opcodes */ |
|
| 216 |
#define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16)) |
|
| 217 |
|
|
| 218 |
enum {
|
|
| 219 |
OPC_BLTZ = (0x00 << 16) | OPC_REGIMM, |
|
| 220 |
OPC_BLTZL = (0x02 << 16) | OPC_REGIMM, |
|
| 221 |
OPC_BGEZ = (0x01 << 16) | OPC_REGIMM, |
|
| 222 |
OPC_BGEZL = (0x03 << 16) | OPC_REGIMM, |
|
| 223 |
OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM, |
|
| 224 |
OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM, |
|
| 225 |
OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM, |
|
| 226 |
OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM, |
|
| 227 |
OPC_TGEI = (0x08 << 16) | OPC_REGIMM, |
|
| 228 |
OPC_TGEIU = (0x09 << 16) | OPC_REGIMM, |
|
| 229 |
OPC_TLTI = (0x0A << 16) | OPC_REGIMM, |
|
| 230 |
OPC_TLTIU = (0x0B << 16) | OPC_REGIMM, |
|
| 231 |
OPC_TEQI = (0x0C << 16) | OPC_REGIMM, |
|
| 232 |
OPC_TNEI = (0x0E << 16) | OPC_REGIMM, |
|
| 233 |
OPC_SYNCI = (0x1F << 16) | OPC_REGIMM, |
|
| 175 | 234 |
}; |
| 176 | 235 |
|
| 236 |
/* Special2 opcodes */ |
|
| 237 |
#define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F) |
|
| 238 |
|
|
| 177 | 239 |
enum {
|
| 178 |
/* Mutiply & xxx operations */ |
|
| 179 |
OPC_MADD = 0x00 | EXT_SPECIAL2,
|
|
| 180 |
OPC_MADDU = 0x01 | EXT_SPECIAL2,
|
|
| 181 |
OPC_MUL = 0x02 | EXT_SPECIAL2,
|
|
| 182 |
OPC_MSUB = 0x04 | EXT_SPECIAL2,
|
|
| 183 |
OPC_MSUBU = 0x05 | EXT_SPECIAL2,
|
|
| 240 |
/* Multiply & xxx operations */
|
|
| 241 |
OPC_MADD = 0x00 | OPC_SPECIAL2,
|
|
| 242 |
OPC_MADDU = 0x01 | OPC_SPECIAL2,
|
|
| 243 |
OPC_MUL = 0x02 | OPC_SPECIAL2,
|
|
| 244 |
OPC_MSUB = 0x04 | OPC_SPECIAL2,
|
|
| 245 |
OPC_MSUBU = 0x05 | OPC_SPECIAL2,
|
|
| 184 | 246 |
/* Misc */ |
| 185 |
OPC_CLZ = 0x20 | EXT_SPECIAL2, |
|
| 186 |
OPC_CLO = 0x21 | EXT_SPECIAL2, |
|
| 247 |
OPC_CLZ = 0x20 | OPC_SPECIAL2, |
|
| 248 |
OPC_CLO = 0x21 | OPC_SPECIAL2, |
|
| 249 |
OPC_DCLZ = 0x24 | OPC_SPECIAL2, |
|
| 250 |
OPC_DCLO = 0x25 | OPC_SPECIAL2, |
|
| 187 | 251 |
/* Special */ |
| 188 |
OPC_SDBBP = 0x3F | EXT_SPECIAL2, |
|
| 252 |
OPC_SDBBP = 0x3F | OPC_SPECIAL2, |
|
| 253 |
}; |
|
| 254 |
|
|
| 255 |
/* Special3 opcodes */ |
|
| 256 |
#define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F) |
|
| 257 |
|
|
| 258 |
enum {
|
|
| 259 |
OPC_EXT = 0x00 | OPC_SPECIAL3, |
|
| 260 |
OPC_DEXTM = 0x01 | OPC_SPECIAL3, |
|
| 261 |
OPC_DEXTU = 0x02 | OPC_SPECIAL3, |
|
| 262 |
OPC_DEXT = 0x03 | OPC_SPECIAL3, |
|
| 263 |
OPC_INS = 0x04 | OPC_SPECIAL3, |
|
| 264 |
OPC_DINSM = 0x05 | OPC_SPECIAL3, |
|
| 265 |
OPC_DINSU = 0x06 | OPC_SPECIAL3, |
|
| 266 |
OPC_DINS = 0x07 | OPC_SPECIAL3, |
|
| 267 |
OPC_BSHFL = 0x20 | OPC_SPECIAL3, |
|
| 268 |
OPC_DBSHFL = 0x24 | OPC_SPECIAL3, |
|
| 269 |
OPC_RDHWR = 0x3B | OPC_SPECIAL3, |
|
| 189 | 270 |
}; |
| 190 | 271 |
|
| 191 |
/* Branch REGIMM */ |
|
| 272 |
/* BSHFL opcodes */ |
|
| 273 |
#define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6)) |
|
| 274 |
|
|
| 192 | 275 |
enum {
|
| 193 |
OPC_BLTZ = 0x00 | EXT_REGIMM, |
|
| 194 |
OPC_BLTZL = 0x02 | EXT_REGIMM, |
|
| 195 |
OPC_BGEZ = 0x01 | EXT_REGIMM, |
|
| 196 |
OPC_BGEZL = 0x03 | EXT_REGIMM, |
|
| 197 |
OPC_BLTZAL = 0x10 | EXT_REGIMM, |
|
| 198 |
OPC_BLTZALL = 0x12 | EXT_REGIMM, |
|
| 199 |
OPC_BGEZAL = 0x11 | EXT_REGIMM, |
|
| 200 |
OPC_BGEZALL = 0x13 | EXT_REGIMM, |
|
| 201 |
OPC_TGEI = 0x08 | EXT_REGIMM, |
|
| 202 |
OPC_TGEIU = 0x09 | EXT_REGIMM, |
|
| 203 |
OPC_TLTI = 0x0A | EXT_REGIMM, |
|
| 204 |
OPC_TLTIU = 0x0B | EXT_REGIMM, |
|
| 205 |
OPC_TEQI = 0x0C | EXT_REGIMM, |
|
| 206 |
OPC_TNEI = 0x0E | EXT_REGIMM, |
|
| 276 |
OPC_WSBH = (0x02 << 6) | OPC_BSHFL, |
|
| 277 |
OPC_SEB = (0x10 << 6) | OPC_BSHFL, |
|
| 278 |
OPC_SEH = (0x18 << 6) | OPC_BSHFL, |
|
| 207 | 279 |
}; |
| 208 | 280 |
|
| 281 |
/* DBSHFL opcodes */ |
|
| 282 |
#define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6)) |
|
| 283 |
|
|
| 209 | 284 |
enum {
|
| 210 |
/* Coprocessor 0 (MMU) */ |
|
| 211 |
OPC_MFC0 = 0x00 | EXT_CP0, |
|
| 212 |
OPC_MTC0 = 0x04 | EXT_CP0, |
|
| 213 |
OPC_TLBR = 0x01 | EXT_CP0, |
|
| 214 |
OPC_TLBWI = 0x02 | EXT_CP0, |
|
| 215 |
OPC_TLBWR = 0x06 | EXT_CP0, |
|
| 216 |
OPC_TLBP = 0x08 | EXT_CP0, |
|
| 217 |
OPC_ERET = 0x18 | EXT_CP0, |
|
| 218 |
OPC_DERET = 0x1F | EXT_CP0, |
|
| 219 |
OPC_WAIT = 0x20 | EXT_CP0, |
|
| 285 |
OPC_DSBH = (0x02 << 6) | OPC_DBSHFL, |
|
| 286 |
OPC_DSHD = (0x05 << 6) | OPC_DBSHFL, |
|
| 220 | 287 |
}; |
| 221 | 288 |
|
| 222 |
#ifdef MIPS_USES_FPU |
|
| 289 |
/* Coprocessor 0 (rs field) */ |
|
| 290 |
#define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) |
|
| 291 |
|
|
| 223 | 292 |
enum {
|
| 224 |
/* Coprocessor 1 (FPU) */ |
|
| 225 |
OPC_MFC1 = 0x00 | EXT_CP1, |
|
| 226 |
OPC_MTC1 = 0x04 | EXT_CP1, |
|
| 227 |
OPC_CFC1 = 0x02 | EXT_CP1, |
|
| 228 |
OPC_CTC1 = 0x06 | EXT_CP1, |
|
| 293 |
OPC_MFC0 = (0x00 << 21) | OPC_CP0, |
|
| 294 |
OPC_DMFC0 = (0x01 << 21) | OPC_CP0, |
|
| 295 |
OPC_MTC0 = (0x04 << 21) | OPC_CP0, |
|
| 296 |
OPC_DMTC0 = (0x05 << 21) | OPC_CP0, |
|
| 297 |
OPC_RDPGPR = (0x0A << 21) | OPC_CP0, |
|
| 298 |
OPC_MFMC0 = (0x0B << 21) | OPC_CP0, |
|
| 299 |
OPC_WRPGPR = (0x0E << 21) | OPC_CP0, |
|
| 300 |
OPC_C0 = (0x10 << 21) | OPC_CP0, |
|
| 301 |
OPC_C0_FIRST = (0x10 << 21) | OPC_CP0, |
|
| 302 |
OPC_C0_LAST = (0x1F << 21) | OPC_CP0, |
|
| 229 | 303 |
}; |
| 230 |
#endif |
|
| 304 |
|
|
| 305 |
/* MFMC0 opcodes */ |
|
| 306 |
#define MASK_MFMC0(op) MASK_CP0(op) | (op & ((0x0C << 11) | (1 << 5))) |
|
| 307 |
|
|
| 308 |
enum {
|
|
| 309 |
OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0, |
|
| 310 |
OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0, |
|
| 311 |
}; |
|
| 312 |
|
|
| 313 |
/* Coprocessor 0 (with rs == C0) */ |
|
| 314 |
#define MASK_C0(op) MASK_CP0(op) | (op & 0x3F) |
|
| 315 |
|
|
| 316 |
enum {
|
|
| 317 |
OPC_TLBR = 0x01 | OPC_C0, |
|
| 318 |
OPC_TLBWI = 0x02 | OPC_C0, |
|
| 319 |
OPC_TLBWR = 0x06 | OPC_C0, |
|
| 320 |
OPC_TLBP = 0x08 | OPC_C0, |
|
| 321 |
OPC_RFE = 0x10 | OPC_C0, |
|
| 322 |
OPC_ERET = 0x18 | OPC_C0, |
|
| 323 |
OPC_DERET = 0x1F | OPC_C0, |
|
| 324 |
OPC_WAIT = 0x20 | OPC_C0, |
|
| 325 |
}; |
|
| 326 |
|
|
| 327 |
/* Coprocessor 1 (rs field) */ |
|
| 328 |
#define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) |
|
| 329 |
|
|
| 330 |
enum {
|
|
| 331 |
OPC_MFC1 = (0x00 << 21) | OPC_CP1, |
|
| 332 |
OPC_DMFC1 = (0x01 << 21) | OPC_CP1, |
|
| 333 |
OPC_CFC1 = (0x02 << 21) | OPC_CP1, |
|
| 334 |
OPC_MFHCI = (0x03 << 21) | OPC_CP1, |
|
| 335 |
OPC_MTC1 = (0x04 << 21) | OPC_CP1, |
|
| 336 |
OPC_DMTC1 = (0x05 << 21) | OPC_CP1, |
|
| 337 |
OPC_CTC1 = (0x06 << 21) | OPC_CP1, |
|
| 338 |
OPC_MTHCI = (0x07 << 21) | OPC_CP1, |
|
| 339 |
OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */ |
|
| 340 |
OPC_S_FMT = (0x10 << 21) | OPC_CP1, /* 16: fmt=single fp */ |
|
| 341 |
OPC_D_FMT = (0x11 << 21) | OPC_CP1, /* 17: fmt=double fp */ |
|
| 342 |
OPC_E_FMT = (0x12 << 21) | OPC_CP1, /* 18: fmt=extended fp */ |
|
| 343 |
OPC_Q_FMT = (0x13 << 21) | OPC_CP1, /* 19: fmt=quad fp */ |
|
| 344 |
OPC_W_FMT = (0x14 << 21) | OPC_CP1, /* 20: fmt=32bit fixed */ |
|
| 345 |
OPC_L_FMT = (0x15 << 21) | OPC_CP1, /* 21: fmt=64bit fixed */ |
|
| 346 |
}; |
|
| 347 |
|
|
| 348 |
enum {
|
|
| 349 |
OPC_BC1F = (0x00 << 16) | OPC_BC1, |
|
| 350 |
OPC_BC1T = (0x01 << 16) | OPC_BC1, |
|
| 351 |
OPC_BC1FL = (0x02 << 16) | OPC_BC1, |
|
| 352 |
OPC_BC1TL = (0x03 << 16) | OPC_BC1, |
|
| 353 |
}; |
|
| 354 |
|
|
| 355 |
#define MASK_CP1_BCOND(op) MASK_CP1(op) | (op & ((0x1F << 21) | (0x3 << 16))) |
|
| 356 |
#define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & ((0x1F << 21) | 0x3F)) |
|
| 357 |
|
|
| 358 |
#define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) |
|
| 359 |
#define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) |
|
| 231 | 360 |
|
| 232 | 361 |
const unsigned char *regnames[] = |
| 233 | 362 |
{ "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
|
| ... | ... | |
| 260 | 389 |
GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr); |
| 261 | 390 |
GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr); |
| 262 | 391 |
|
| 263 |
#ifdef MIPS_USES_FPU |
|
| 264 |
const unsigned char *fregnames[] = |
|
| 392 |
static const char *fregnames[] = |
|
| 265 | 393 |
{ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
|
| 266 | 394 |
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 267 | 395 |
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| ... | ... | |
| 344 | 472 |
FOP_CONDS(d) |
| 345 | 473 |
FOP_CONDS(s) |
| 346 | 474 |
|
| 347 |
#endif |
|
| 348 |
|
|
| 349 | 475 |
typedef struct DisasContext {
|
| 350 | 476 |
struct TranslationBlock *tb; |
| 351 | 477 |
target_ulong pc, saved_pc; |
| ... | ... | |
| 410 | 536 |
} \ |
| 411 | 537 |
} while (0) |
| 412 | 538 |
|
| 413 |
#ifdef MIPS_USES_FPU |
|
| 414 |
|
|
| 415 |
# define GEN_LOAD_FREG_FTN(FTn, Fn) \ |
|
| 539 |
#define GEN_LOAD_FREG_FTN(FTn, Fn) \ |
|
| 416 | 540 |
do { \
|
| 417 | 541 |
glue(gen_op_load_fpr_, FTn)(Fn); \ |
| 418 | 542 |
} while (0) |
| ... | ... | |
| 422 | 546 |
glue(gen_op_store_fpr_, FTn)(Fn); \ |
| 423 | 547 |
} while (0) |
| 424 | 548 |
|
| 425 |
#endif |
|
| 426 |
|
|
| 427 | 549 |
static inline void save_cpu_state (DisasContext *ctx, int do_save_pc) |
| 428 | 550 |
{
|
| 429 | 551 |
#if defined MIPS_DEBUG_DISAS |
| ... | ... | |
| 487 | 609 |
} |
| 488 | 610 |
#endif |
| 489 | 611 |
|
| 490 |
#ifdef TARGET_MIPS64
|
|
| 612 |
#ifdef MIPS_HAS_MIPS64
|
|
| 491 | 613 |
OP_LD_TABLE(d); |
| 492 | 614 |
OP_LD_TABLE(dl); |
| 493 | 615 |
OP_LD_TABLE(dr); |
| ... | ... | |
| 510 | 632 |
OP_ST_TABLE(b); |
| 511 | 633 |
OP_LD_TABLE(l); |
| 512 | 634 |
OP_ST_TABLE(c); |
| 513 |
#ifdef MIPS_USES_FPU |
|
| 514 | 635 |
OP_LD_TABLE(wc1); |
| 515 | 636 |
OP_ST_TABLE(wc1); |
| 516 | 637 |
OP_LD_TABLE(dc1); |
| 517 | 638 |
OP_ST_TABLE(dc1); |
| 518 |
#endif |
|
| 519 | 639 |
|
| 520 | 640 |
/* Load and store */ |
| 521 |
static void gen_ldst (DisasContext *ctx, uint16_t opc, int rt,
|
|
| 641 |
static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
|
|
| 522 | 642 |
int base, int16_t offset) |
| 523 | 643 |
{
|
| 524 |
const unsigned char *opn = "unk";
|
|
| 644 |
const char *opn = "unk"; |
|
| 525 | 645 |
|
| 526 | 646 |
if (base == 0) {
|
| 527 | 647 |
GEN_LOAD_IMM_TN(T0, offset); |
| ... | ... | |
| 536 | 656 |
* memory access |
| 537 | 657 |
*/ |
| 538 | 658 |
switch (opc) {
|
| 539 |
#if defined(TARGET_MIPS64)
|
|
| 659 |
#ifdef MIPS_HAS_MIPS64
|
|
| 540 | 660 |
case OPC_LD: |
| 541 |
#if defined (MIPS_HAS_UNALIGNED_LS) |
|
| 542 |
case OPC_ULD: |
|
| 543 |
#endif |
|
| 544 | 661 |
op_ldst(ld); |
| 545 | 662 |
GEN_STORE_TN_REG(rt, T0); |
| 546 | 663 |
opn = "ld"; |
| 547 | 664 |
break; |
| 665 |
case OPC_LLD: |
|
| 666 |
op_ldst(lld); |
|
| 667 |
GEN_STORE_TN_REG(rt, T0); |
|
| 668 |
opn = "lld"; |
|
| 669 |
break; |
|
| 548 | 670 |
case OPC_SD: |
| 549 |
#if defined (MIPS_HAS_UNALIGNED_LS) |
|
| 550 |
case OPC_USD: |
|
| 551 |
#endif |
|
| 552 | 671 |
GEN_LOAD_REG_TN(T1, rt); |
| 553 | 672 |
op_ldst(sd); |
| 554 | 673 |
opn = "sd"; |
| 555 | 674 |
break; |
| 675 |
case OPC_SCD: |
|
| 676 |
GEN_LOAD_REG_TN(T1, rt); |
|
| 677 |
op_ldst(scd); |
|
| 678 |
opn = "scd"; |
|
| 679 |
break; |
|
| 556 | 680 |
case OPC_LDL: |
| 557 | 681 |
op_ldst(ldl); |
| 558 | 682 |
GEN_STORE_TN_REG(rt, T0); |
| ... | ... | |
| 575 | 699 |
break; |
| 576 | 700 |
#endif |
| 577 | 701 |
case OPC_LW: |
| 578 |
#if defined (MIPS_HAS_UNALIGNED_LS) |
|
| 579 |
case OPC_ULW: |
|
| 580 |
#endif |
|
| 581 | 702 |
op_ldst(lw); |
| 582 | 703 |
GEN_STORE_TN_REG(rt, T0); |
| 583 | 704 |
opn = "lw"; |
| ... | ... | |
| 588 | 709 |
opn = "lwu"; |
| 589 | 710 |
break; |
| 590 | 711 |
case OPC_SW: |
| 591 |
#if defined (MIPS_HAS_UNALIGNED_LS) |
|
| 592 |
case OPC_USW: |
|
| 593 |
#endif |
|
| 594 | 712 |
GEN_LOAD_REG_TN(T1, rt); |
| 595 | 713 |
op_ldst(sw); |
| 596 | 714 |
opn = "sw"; |
| 597 | 715 |
break; |
| 598 | 716 |
case OPC_LH: |
| 599 |
#if defined (MIPS_HAS_UNALIGNED_LS) |
|
| 600 |
case OPC_ULH: |
|
| 601 |
#endif |
|
| 602 | 717 |
op_ldst(lh); |
| 603 | 718 |
GEN_STORE_TN_REG(rt, T0); |
| 604 | 719 |
opn = "lh"; |
| 605 | 720 |
break; |
| 606 | 721 |
case OPC_SH: |
| 607 |
#if defined (MIPS_HAS_UNALIGNED_LS) |
|
| 608 |
case OPC_USH: |
|
| 609 |
#endif |
|
| 610 | 722 |
GEN_LOAD_REG_TN(T1, rt); |
| 611 | 723 |
op_ldst(sh); |
| 612 | 724 |
opn = "sh"; |
| 613 | 725 |
break; |
| 614 | 726 |
case OPC_LHU: |
| 615 |
#if defined (MIPS_HAS_UNALIGNED_LS) |
|
| 616 |
case OPC_ULHU: |
|
| 617 |
#endif |
|
| 618 | 727 |
op_ldst(lhu); |
| 619 | 728 |
GEN_STORE_TN_REG(rt, T0); |
| 620 | 729 |
opn = "lhu"; |
| ... | ... | |
| 675 | 784 |
MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
|
| 676 | 785 |
} |
| 677 | 786 |
|
| 678 |
#ifdef MIPS_USES_FPU |
|
| 679 |
|
|
| 680 | 787 |
/* Load and store */ |
| 681 |
static void gen_flt_ldst (DisasContext *ctx, uint16_t opc, int ft,
|
|
| 788 |
static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
|
|
| 682 | 789 |
int base, int16_t offset) |
| 683 | 790 |
{
|
| 684 |
const unsigned char *opn = "unk";
|
|
| 791 |
const char *opn = "unk"; |
|
| 685 | 792 |
|
| 686 | 793 |
if (base == 0) {
|
| 687 | 794 |
GEN_LOAD_IMM_TN(T0, offset); |
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