Revision 7a387fff target-mips/cpu.h

b/target-mips/cpu.h
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#endif
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    uint32_t CP0_index;
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    uint32_t CP0_random;
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    uint32_t CP0_EntryLo0;
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    uint32_t CP0_EntryLo1;
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    uint32_t CP0_Context;
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    uint64_t CP0_EntryLo0;
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    uint64_t CP0_EntryLo1;
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    uint64_t CP0_Context;
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    uint32_t CP0_PageMask;
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    uint32_t CP0_PageGrain;
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    uint32_t CP0_Wired;
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    uint32_t CP0_HWREna;
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    uint32_t CP0_BadVAddr;
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    uint32_t CP0_Count;
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    uint32_t CP0_EntryHi;
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    uint64_t CP0_EntryHi;
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    uint32_t CP0_Compare;
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    uint32_t CP0_Status;
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#define CP0St_CU3   31
......
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#define CP0St_RP    27
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#define CP0St_FR    26
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#define CP0St_RE    25
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#define CP0St_MX    24
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#define CP0St_PX    23
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#define CP0St_BEV   22
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#define CP0St_TS    21
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#define CP0St_SR    20
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#define CP0St_NMI   19
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#define CP0St_IM    8
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#define CP0St_KX    7
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#define CP0St_SX    6
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#define CP0St_UX    5
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#define CP0St_UM    4
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#define CP0St_R0    3
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#define CP0St_ERL   2
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#define CP0St_EXL   1
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#define CP0St_IE    0
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    uint32_t CP0_IntCtl;
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    uint32_t CP0_SRSCtl;
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    uint32_t CP0_Cause;
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#define CP0Ca_BD   31
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#define CP0Ca_TI   30
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#define CP0Ca_CE   28
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#define CP0Ca_DC   27
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#define CP0Ca_PCI  26
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#define CP0Ca_IV   23
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#define CP0Ca_WP   22
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#define CP0Ca_IP    8
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#define CP0Ca_EC    2
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    uint32_t CP0_EPC;
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    uint32_t CP0_PRid;
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    uint32_t CP0_EBase;
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    uint32_t CP0_Config0;
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#define CP0C0_M    31
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#define CP0C0_K23  28
......
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#define CP0C0_AT   13
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#define CP0C0_AR   10
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#define CP0C0_MT   7
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#define CP0C0_VI   3
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#define CP0C0_K0   0
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    uint32_t CP0_Config1;
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#define CP0C1_M    31
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#define CP0C1_MMU  25
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#define CP0C1_IS   22
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#define CP0C1_IL   19
......
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#define CP0C1_DS   13
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#define CP0C1_DL   10
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#define CP0C1_DA   7
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#define CP0C1_C2   6
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#define CP0C1_MD   5
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#define CP0C1_PC   4
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#define CP0C1_WR   3
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#define CP0C1_CA   2
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#define CP0C1_EP   1
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#define CP0C1_FP   0
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    uint32_t CP0_Config2;
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#define CP0C2_M    31
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#define CP0C2_TU   28
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#define CP0C2_TS   24
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#define CP0C2_TL   20
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#define CP0C2_TA   16
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#define CP0C2_SU   12
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#define CP0C2_SS   8
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#define CP0C2_SL   4
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#define CP0C2_SA   0
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    uint32_t CP0_Config3;
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#define CP0C3_M    31
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#define CP0C3_DSPP 10
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#define CP0C3_LPA  7
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#define CP0C3_VEIC 6
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#define CP0C3_VInt 5
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#define CP0C3_SP   4
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#define CP0C3_MT   2
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#define CP0C3_SM   1
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#define CP0C3_TL   0
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    uint32_t CP0_LLAddr;
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    uint32_t CP0_WatchLo;
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    uint32_t CP0_WatchHi;
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    uint32_t CP0_XContext;
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    uint32_t CP0_Framemask;
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    uint32_t CP0_Debug;
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#define CPDB_DBD   31
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#define CP0DB_DM   30
......
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#define CP0DB_DBp  1
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#define CP0DB_DSS  0
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    uint32_t CP0_DEPC;
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    uint32_t CP0_Performance0;
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    uint32_t CP0_TagLo;
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    uint32_t CP0_DataLo;
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    uint32_t CP0_TagHi;
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    uint32_t CP0_DataHi;
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    uint32_t CP0_ErrorEPC;
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    uint32_t CP0_DESAVE;
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    /* Qemu */
......
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    int halted; /* TRUE if the CPU is in suspend state */


  		





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    int SYNCI_Step; /* Address step size for SYNCI */


  		





  
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    int CCRes; /* Cycle count resolution/divisor */


  		





  
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    CPU_COMMON


  		





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    int ram_size;


  		












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