Revision 7a387fff target-mips/op.c
| b/target-mips/op.c | ||
|---|---|---|
| 437 | 437 |
RETURN(); |
| 438 | 438 |
} |
| 439 | 439 |
|
| 440 |
void op_rotr (void) |
|
| 441 |
{
|
|
| 442 |
target_ulong tmp; |
|
| 443 |
|
|
| 444 |
if (T1) {
|
|
| 445 |
tmp = T0 << (0x20 - T1); |
|
| 446 |
T0 = (T0 >> T1) | tmp; |
|
| 447 |
} else |
|
| 448 |
T0 = T1; |
|
| 449 |
RETURN(); |
|
| 450 |
} |
|
| 451 |
|
|
| 440 | 452 |
void op_sllv (void) |
| 441 | 453 |
{
|
| 442 | 454 |
T0 = T1 << (T0 & 0x1F); |
| ... | ... | |
| 455 | 467 |
RETURN(); |
| 456 | 468 |
} |
| 457 | 469 |
|
| 470 |
void op_rotrv (void) |
|
| 471 |
{
|
|
| 472 |
target_ulong tmp; |
|
| 473 |
|
|
| 474 |
T0 &= 0x1F; |
|
| 475 |
if (T0) {
|
|
| 476 |
tmp = T1 << (0x20 - T0); |
|
| 477 |
T0 = (T1 >> T0) | tmp; |
|
| 478 |
} else |
|
| 479 |
T0 = T1; |
|
| 480 |
RETURN(); |
|
| 481 |
} |
|
| 482 |
|
|
| 458 | 483 |
void op_clo (void) |
| 459 | 484 |
{
|
| 460 | 485 |
int n; |
| ... | ... | |
| 602 | 627 |
RETURN(); |
| 603 | 628 |
} |
| 604 | 629 |
|
| 630 |
void op_movf (void) |
|
| 631 |
{
|
|
| 632 |
if (!(env->fcr31 & PARAM1)) |
|
| 633 |
env->gpr[PARAM2] = env->gpr[PARAM3]; |
|
| 634 |
RETURN(); |
|
| 635 |
} |
|
| 636 |
|
|
| 637 |
void op_movt (void) |
|
| 638 |
{
|
|
| 639 |
if (env->fcr31 & PARAM1) |
|
| 640 |
env->gpr[PARAM2] = env->gpr[PARAM3]; |
|
| 641 |
RETURN(); |
|
| 642 |
} |
|
| 643 |
|
|
| 605 | 644 |
/* Tests */ |
| 606 | 645 |
#define OP_COND(name, cond) \ |
| 607 | 646 |
void glue(op_, name) (void) \ |
| ... | ... | |
| 625 | 664 |
OP_COND(lez, (int32_t)T0 <= 0); |
| 626 | 665 |
OP_COND(ltz, (int32_t)T0 < 0); |
| 627 | 666 |
|
| 628 |
/* Branchs */ |
|
| 667 |
/* Branches */
|
|
| 629 | 668 |
//#undef USE_DIRECT_JUMP |
| 630 | 669 |
|
| 631 | 670 |
void OPPROTO op_goto_tb0(void) |
| 632 | 671 |
{
|
| 633 | 672 |
GOTO_TB(op_goto_tb0, PARAM1, 0); |
| 673 |
RETURN(); |
|
| 634 | 674 |
} |
| 635 | 675 |
|
| 636 | 676 |
void OPPROTO op_goto_tb1(void) |
| 637 | 677 |
{
|
| 638 | 678 |
GOTO_TB(op_goto_tb1, PARAM1, 1); |
| 679 |
RETURN(); |
|
| 639 | 680 |
} |
| 640 | 681 |
|
| 641 | 682 |
/* Branch to register */ |
| 642 | 683 |
void op_save_breg_target (void) |
| 643 | 684 |
{
|
| 644 | 685 |
env->btarget = T2; |
| 686 |
RETURN(); |
|
| 645 | 687 |
} |
| 646 | 688 |
|
| 647 | 689 |
void op_restore_breg_target (void) |
| 648 | 690 |
{
|
| 649 | 691 |
T2 = env->btarget; |
| 692 |
RETURN(); |
|
| 650 | 693 |
} |
| 651 | 694 |
|
| 652 | 695 |
void op_breg (void) |
| ... | ... | |
| 724 | 767 |
RETURN(); |
| 725 | 768 |
} |
| 726 | 769 |
|
| 770 |
void op_mfc0_pagegrain (void) |
|
| 771 |
{
|
|
| 772 |
T0 = env->CP0_PageGrain; |
|
| 773 |
RETURN(); |
|
| 774 |
} |
|
| 775 |
|
|
| 727 | 776 |
void op_mfc0_wired (void) |
| 728 | 777 |
{
|
| 729 | 778 |
T0 = env->CP0_Wired; |
| 730 | 779 |
RETURN(); |
| 731 | 780 |
} |
| 732 | 781 |
|
| 782 |
void op_mfc0_hwrena (void) |
|
| 783 |
{
|
|
| 784 |
T0 = env->CP0_HWREna; |
|
| 785 |
RETURN(); |
|
| 786 |
} |
|
| 787 |
|
|
| 733 | 788 |
void op_mfc0_badvaddr (void) |
| 734 | 789 |
{
|
| 735 | 790 |
T0 = env->CP0_BadVAddr; |
| ... | ... | |
| 766 | 821 |
RETURN(); |
| 767 | 822 |
} |
| 768 | 823 |
|
| 824 |
void op_mfc0_intctl (void) |
|
| 825 |
{
|
|
| 826 |
T0 = env->CP0_IntCtl; |
|
| 827 |
RETURN(); |
|
| 828 |
} |
|
| 829 |
|
|
| 830 |
void op_mfc0_srsctl (void) |
|
| 831 |
{
|
|
| 832 |
T0 = env->CP0_SRSCtl; |
|
| 833 |
RETURN(); |
|
| 834 |
} |
|
| 835 |
|
|
| 769 | 836 |
void op_mfc0_cause (void) |
| 770 | 837 |
{
|
| 771 | 838 |
T0 = env->CP0_Cause; |
| ... | ... | |
| 784 | 851 |
RETURN(); |
| 785 | 852 |
} |
| 786 | 853 |
|
| 854 |
void op_mfc0_ebase (void) |
|
| 855 |
{
|
|
| 856 |
T0 = env->CP0_EBase; |
|
| 857 |
RETURN(); |
|
| 858 |
} |
|
| 859 |
|
|
| 787 | 860 |
void op_mfc0_config0 (void) |
| 788 | 861 |
{
|
| 789 | 862 |
T0 = env->CP0_Config0; |
| ... | ... | |
| 796 | 869 |
RETURN(); |
| 797 | 870 |
} |
| 798 | 871 |
|
| 872 |
void op_mfc0_config2 (void) |
|
| 873 |
{
|
|
| 874 |
T0 = env->CP0_Config2; |
|
| 875 |
RETURN(); |
|
| 876 |
} |
|
| 877 |
|
|
| 878 |
void op_mfc0_config3 (void) |
|
| 879 |
{
|
|
| 880 |
T0 = env->CP0_Config3; |
|
| 881 |
RETURN(); |
|
| 882 |
} |
|
| 883 |
|
|
| 799 | 884 |
void op_mfc0_lladdr (void) |
| 800 | 885 |
{
|
| 801 | 886 |
T0 = env->CP0_LLAddr >> 4; |
| 802 | 887 |
RETURN(); |
| 803 | 888 |
} |
| 804 | 889 |
|
| 805 |
void op_mfc0_watchlo (void) |
|
| 890 |
void op_mfc0_watchlo0 (void)
|
|
| 806 | 891 |
{
|
| 807 | 892 |
T0 = env->CP0_WatchLo; |
| 808 | 893 |
RETURN(); |
| 809 | 894 |
} |
| 810 | 895 |
|
| 811 |
void op_mfc0_watchhi (void) |
|
| 896 |
void op_mfc0_watchhi0 (void)
|
|
| 812 | 897 |
{
|
| 813 | 898 |
T0 = env->CP0_WatchHi; |
| 814 | 899 |
RETURN(); |
| 815 | 900 |
} |
| 816 | 901 |
|
| 902 |
void op_mfc0_xcontext (void) |
|
| 903 |
{
|
|
| 904 |
T0 = env->CP0_XContext; |
|
| 905 |
RETURN(); |
|
| 906 |
} |
|
| 907 |
|
|
| 908 |
void op_mfc0_framemask (void) |
|
| 909 |
{
|
|
| 910 |
T0 = env->CP0_Framemask; |
|
| 911 |
RETURN(); |
|
| 912 |
} |
|
| 913 |
|
|
| 817 | 914 |
void op_mfc0_debug (void) |
| 818 | 915 |
{
|
| 819 | 916 |
T0 = env->CP0_Debug; |
| ... | ... | |
| 828 | 925 |
RETURN(); |
| 829 | 926 |
} |
| 830 | 927 |
|
| 928 |
void op_mfc0_performance0 (void) |
|
| 929 |
{
|
|
| 930 |
T0 = env->CP0_Performance0; |
|
| 931 |
RETURN(); |
|
| 932 |
} |
|
| 933 |
|
|
| 831 | 934 |
void op_mfc0_taglo (void) |
| 832 | 935 |
{
|
| 833 | 936 |
T0 = env->CP0_TagLo; |
| ... | ... | |
| 840 | 943 |
RETURN(); |
| 841 | 944 |
} |
| 842 | 945 |
|
| 946 |
void op_mfc0_taghi (void) |
|
| 947 |
{
|
|
| 948 |
T0 = env->CP0_TagHi; |
|
| 949 |
RETURN(); |
|
| 950 |
} |
|
| 951 |
|
|
| 952 |
void op_mfc0_datahi (void) |
|
| 953 |
{
|
|
| 954 |
T0 = env->CP0_DataHi; |
|
| 955 |
RETURN(); |
|
| 956 |
} |
|
| 957 |
|
|
| 843 | 958 |
void op_mfc0_errorepc (void) |
| 844 | 959 |
{
|
| 845 | 960 |
T0 = env->CP0_ErrorEPC; |
| ... | ... | |
| 854 | 969 |
|
| 855 | 970 |
void op_mtc0_index (void) |
| 856 | 971 |
{
|
| 857 |
env->CP0_index = (env->CP0_index & 0x80000000) | (T0 & 0x0000000F);
|
|
| 972 |
env->CP0_index = (env->CP0_index & 0x80000000) | (T0 & (MIPS_TLB_NB - 1));
|
|
| 858 | 973 |
RETURN(); |
| 859 | 974 |
} |
| 860 | 975 |
|
| 861 | 976 |
void op_mtc0_entrylo0 (void) |
| 862 | 977 |
{
|
| 863 |
env->CP0_EntryLo0 = T0 & 0x3FFFFFFF; |
|
| 978 |
/* Large physaddr not implemented */ |
|
| 979 |
/* 1k pages not implemented */ |
|
| 980 |
env->CP0_EntryLo0 = T0 & 0x3FFFFFFFUL; |
|
| 864 | 981 |
RETURN(); |
| 865 | 982 |
} |
| 866 | 983 |
|
| 867 | 984 |
void op_mtc0_entrylo1 (void) |
| 868 | 985 |
{
|
| 869 |
env->CP0_EntryLo1 = T0 & 0x3FFFFFFF; |
|
| 986 |
/* Large physaddr not implemented */ |
|
| 987 |
/* 1k pages not implemented */ |
|
| 988 |
env->CP0_EntryLo1 = T0 & 0x3FFFFFFFUL; |
|
| 870 | 989 |
RETURN(); |
| 871 | 990 |
} |
| 872 | 991 |
|
| 873 | 992 |
void op_mtc0_context (void) |
| 874 | 993 |
{
|
| 875 |
env->CP0_Context = (env->CP0_Context & 0xFF800000) | (T0 & 0x007FFFF0);
|
|
| 994 |
env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
|
|
| 876 | 995 |
RETURN(); |
| 877 | 996 |
} |
| 878 | 997 |
|
| 879 | 998 |
void op_mtc0_pagemask (void) |
| 880 | 999 |
{
|
| 881 |
env->CP0_PageMask = T0 & 0x01FFE000; |
|
| 1000 |
/* 1k pages not implemented */ |
|
| 1001 |
env->CP0_PageMask = T0 & 0x1FFFE000; |
|
| 1002 |
RETURN(); |
|
| 1003 |
} |
|
| 1004 |
|
|
| 1005 |
void op_mtc0_pagegrain (void) |
|
| 1006 |
{
|
|
| 1007 |
/* SmartMIPS not implemented */ |
|
| 1008 |
/* Large physaddr not implemented */ |
|
| 1009 |
/* 1k pages not implemented */ |
|
| 1010 |
env->CP0_PageGrain = 0; |
|
| 882 | 1011 |
RETURN(); |
| 883 | 1012 |
} |
| 884 | 1013 |
|
| 885 | 1014 |
void op_mtc0_wired (void) |
| 886 | 1015 |
{
|
| 887 |
env->CP0_Wired = T0 & 0x0000000F; |
|
| 1016 |
env->CP0_Wired = T0 & (MIPS_TLB_NB - 1); |
|
| 1017 |
RETURN(); |
|
| 1018 |
} |
|
| 1019 |
|
|
| 1020 |
void op_mtc0_hwrena (void) |
|
| 1021 |
{
|
|
| 1022 |
env->CP0_HWREna = T0 & 0x0000000F; |
|
| 888 | 1023 |
RETURN(); |
| 889 | 1024 |
} |
| 890 | 1025 |
|
| ... | ... | |
| 898 | 1033 |
{
|
| 899 | 1034 |
uint32_t old, val; |
| 900 | 1035 |
|
| 1036 |
/* 1k pages not implemented */ |
|
| 1037 |
/* Ignore MIPS64 TLB for now */ |
|
| 901 | 1038 |
val = T0 & 0xFFFFE0FF; |
| 902 | 1039 |
old = env->CP0_EntryHi; |
| 903 | 1040 |
env->CP0_EntryHi = val; |
| ... | ... | |
| 950 | 1087 |
RETURN(); |
| 951 | 1088 |
} |
| 952 | 1089 |
|
| 1090 |
void op_mtc0_intctl (void) |
|
| 1091 |
{
|
|
| 1092 |
/* vectored interrupts not implemented */ |
|
| 1093 |
env->CP0_IntCtl = 0; |
|
| 1094 |
RETURN(); |
|
| 1095 |
} |
|
| 1096 |
|
|
| 1097 |
void op_mtc0_srsctl (void) |
|
| 1098 |
{
|
|
| 1099 |
/* shadow registers not implemented */ |
|
| 1100 |
env->CP0_SRSCtl = 0; |
|
| 1101 |
RETURN(); |
|
| 1102 |
} |
|
| 1103 |
|
|
| 953 | 1104 |
void op_mtc0_cause (void) |
| 954 | 1105 |
{
|
| 955 | 1106 |
uint32_t val, old; |
| ... | ... | |
| 960 | 1111 |
#if 0 |
| 961 | 1112 |
{
|
| 962 | 1113 |
int i, mask; |
| 963 |
|
|
| 964 | 1114 |
/* Check if we ever asserted a software IRQ */ |
| 965 | 1115 |
for (i = 0; i < 2; i++) {
|
| 966 | 1116 |
mask = 0x100 << i; |
| ... | ... | |
| 978 | 1128 |
RETURN(); |
| 979 | 1129 |
} |
| 980 | 1130 |
|
| 1131 |
void op_mtc0_ebase (void) |
|
| 1132 |
{
|
|
| 1133 |
/* vectored interrupts not implemented */ |
|
| 1134 |
/* Multi-CPU not implemented */ |
|
| 1135 |
env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000); |
|
| 1136 |
RETURN(); |
|
| 1137 |
} |
|
| 1138 |
|
|
| 981 | 1139 |
void op_mtc0_config0 (void) |
| 982 | 1140 |
{
|
| 983 | 1141 |
#if defined(MIPS_USES_R4K_TLB) |
| 984 |
env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF80) | (T0 & 0x7E000001); |
|
| 1142 |
/* Fixed mapping MMU not implemented */ |
|
| 1143 |
env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF88) | (T0 & 0x00000001); |
|
| 985 | 1144 |
#else |
| 986 |
env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF80) | (T0 & 0x00000001);
|
|
| 1145 |
env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF88) | (T0 & 0x00000001);
|
|
| 987 | 1146 |
#endif |
| 988 | 1147 |
RETURN(); |
| 989 | 1148 |
} |
| 990 | 1149 |
|
| 991 |
void op_mtc0_watchlo (void) |
|
| 1150 |
void op_mtc0_config2 (void) |
|
| 1151 |
{
|
|
| 1152 |
/* tertiary/secondary caches not implemented */ |
|
| 1153 |
env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); |
|
| 1154 |
RETURN(); |
|
| 1155 |
} |
|
| 1156 |
|
|
| 1157 |
void op_mtc0_watchlo0 (void) |
|
| 992 | 1158 |
{
|
| 993 | 1159 |
env->CP0_WatchLo = T0; |
| 994 | 1160 |
RETURN(); |
| 995 | 1161 |
} |
| 996 | 1162 |
|
| 997 |
void op_mtc0_watchhi (void) |
|
| 1163 |
void op_mtc0_watchhi0 (void)
|
|
| 998 | 1164 |
{
|
| 999 | 1165 |
env->CP0_WatchHi = T0 & 0x40FF0FF8; |
| 1000 | 1166 |
RETURN(); |
| 1001 | 1167 |
} |
| 1002 | 1168 |
|
| 1169 |
void op_mtc0_xcontext (void) |
|
| 1170 |
{
|
|
| 1171 |
env->CP0_XContext = T0; /* XXX */ |
|
| 1172 |
RETURN(); |
|
| 1173 |
} |
|
| 1174 |
|
|
| 1175 |
void op_mtc0_framemask (void) |
|
| 1176 |
{
|
|
| 1177 |
env->CP0_Framemask = T0; /* XXX */ |
|
| 1178 |
RETURN(); |
|
| 1179 |
} |
|
| 1180 |
|
|
| 1003 | 1181 |
void op_mtc0_debug (void) |
| 1004 | 1182 |
{
|
| 1005 | 1183 |
env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); |
| ... | ... | |
| 1016 | 1194 |
RETURN(); |
| 1017 | 1195 |
} |
| 1018 | 1196 |
|
| 1197 |
void op_mtc0_performance0 (void) |
|
| 1198 |
{
|
|
| 1199 |
env->CP0_Performance0 = T0; /* XXX */ |
|
| 1200 |
RETURN(); |
|
| 1201 |
} |
|
| 1202 |
|
|
| 1019 | 1203 |
void op_mtc0_taglo (void) |
| 1020 | 1204 |
{
|
| 1021 | 1205 |
env->CP0_TagLo = T0 & 0xFFFFFCF6; |
| 1022 | 1206 |
RETURN(); |
| 1023 | 1207 |
} |
| 1024 | 1208 |
|
| 1209 |
void op_mtc0_datalo (void) |
|
| 1210 |
{
|
|
| 1211 |
env->CP0_DataLo = T0; /* XXX */ |
|
| 1212 |
RETURN(); |
|
| 1213 |
} |
|
| 1214 |
|
|
| 1215 |
void op_mtc0_taghi (void) |
|
| 1216 |
{
|
|
| 1217 |
env->CP0_TagHi = T0; /* XXX */ |
|
| 1218 |
RETURN(); |
|
| 1219 |
} |
|
| 1220 |
|
|
| 1221 |
void op_mtc0_datahi (void) |
|
| 1222 |
{
|
|
| 1223 |
env->CP0_DataHi = T0; /* XXX */ |
|
| 1224 |
RETURN(); |
|
| 1225 |
} |
|
| 1226 |
|
|
| 1025 | 1227 |
void op_mtc0_errorepc (void) |
| 1026 | 1228 |
{
|
| 1027 | 1229 |
env->CP0_ErrorEPC = T0; |
| ... | ... | |
| 1422 | 1624 |
void op_pmon (void) |
| 1423 | 1625 |
{
|
| 1424 | 1626 |
CALL_FROM_TB1(do_pmon, PARAM1); |
| 1627 |
RETURN(); |
|
| 1628 |
} |
|
| 1629 |
|
|
| 1630 |
void op_di (void) |
|
| 1631 |
{
|
|
| 1632 |
uint32_t val; |
|
| 1633 |
|
|
| 1634 |
T0 = env->CP0_Status; |
|
| 1635 |
val = T0 & ~(1 << CP0St_IE); |
|
| 1636 |
if (val != T0) {
|
|
| 1637 |
env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
|
| 1638 |
env->CP0_Status = val; |
|
| 1639 |
} |
|
| 1640 |
RETURN(); |
|
| 1641 |
} |
|
| 1642 |
|
|
| 1643 |
void op_ei (void) |
|
| 1644 |
{
|
|
| 1645 |
uint32_t val; |
|
| 1646 |
|
|
| 1647 |
T0 = env->CP0_Status; |
|
| 1648 |
val = T0 | (1 << CP0St_IE); |
|
| 1649 |
if (val != T0) {
|
|
| 1650 |
const uint32_t mask = 0x0000FF00; |
|
| 1651 |
|
|
| 1652 |
env->CP0_Status = val; |
|
| 1653 |
if (!(env->hflags & MIPS_HFLAG_EXL) && |
|
| 1654 |
!(env->hflags & MIPS_HFLAG_ERL) && |
|
| 1655 |
!(env->hflags & MIPS_HFLAG_DM) && |
|
| 1656 |
(env->CP0_Status & env->CP0_Cause & mask)) {
|
|
| 1657 |
env->interrupt_request |= CPU_INTERRUPT_HARD; |
|
| 1658 |
if (logfile) |
|
| 1659 |
CALL_FROM_TB0(do_mtc0_status_irqraise_debug); |
|
| 1660 |
} |
|
| 1661 |
} |
|
| 1662 |
RETURN(); |
|
| 1425 | 1663 |
} |
| 1426 | 1664 |
|
| 1427 | 1665 |
void op_trap (void) |
| ... | ... | |
| 1434 | 1672 |
|
| 1435 | 1673 |
void op_debug (void) |
| 1436 | 1674 |
{
|
| 1437 |
CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG); |
|
| 1675 |
CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG); |
|
| 1676 |
RETURN(); |
|
| 1438 | 1677 |
} |
| 1439 | 1678 |
|
| 1440 | 1679 |
void op_set_lladdr (void) |
| 1441 | 1680 |
{
|
| 1442 | 1681 |
env->CP0_LLAddr = T2; |
| 1682 |
RETURN(); |
|
| 1443 | 1683 |
} |
| 1444 | 1684 |
|
| 1445 | 1685 |
void debug_eret (void); |
| ... | ... | |
| 1456 | 1696 |
env->CP0_Status &= ~(1 << CP0St_EXL); |
| 1457 | 1697 |
} |
| 1458 | 1698 |
env->CP0_LLAddr = 1; |
| 1699 |
RETURN(); |
|
| 1459 | 1700 |
} |
| 1460 | 1701 |
|
| 1461 | 1702 |
void op_deret (void) |
| 1462 | 1703 |
{
|
| 1463 | 1704 |
CALL_FROM_TB0(debug_eret); |
| 1464 | 1705 |
env->PC = env->CP0_DEPC; |
| 1706 |
RETURN(); |
|
| 1707 |
} |
|
| 1708 |
|
|
| 1709 |
void op_rdhwr_cpunum(void) |
|
| 1710 |
{
|
|
| 1711 |
if (env->CP0_HWREna & (1 << 0)) |
|
| 1712 |
T0 = env->CP0_EBase & 0x2ff; |
|
| 1713 |
else |
|
| 1714 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI); |
|
| 1715 |
RETURN(); |
|
| 1716 |
} |
|
| 1717 |
|
|
| 1718 |
void op_rdhwr_synci_step(void) |
|
| 1719 |
{
|
|
| 1720 |
if (env->CP0_HWREna & (1 << 1)) |
|
| 1721 |
T0 = env->SYNCI_Step; |
|
| 1722 |
else |
|
| 1723 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI); |
|
| 1724 |
RETURN(); |
|
| 1725 |
} |
|
| 1726 |
|
|
| 1727 |
void op_rdhwr_cc(void) |
|
| 1728 |
{
|
|
| 1729 |
if (env->CP0_HWREna & (1 << 2)) |
|
| 1730 |
T0 = env->CP0_Count; |
|
| 1731 |
else |
|
| 1732 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI); |
|
| 1733 |
RETURN(); |
|
| 1734 |
} |
|
| 1735 |
|
|
| 1736 |
void op_rdhwr_ccres(void) |
|
| 1737 |
{
|
|
| 1738 |
if (env->CP0_HWREna & (1 << 3)) |
|
| 1739 |
T0 = env->CCRes; |
|
| 1740 |
else |
|
| 1741 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI); |
|
| 1742 |
RETURN(); |
|
| 1465 | 1743 |
} |
| 1466 | 1744 |
|
| 1467 | 1745 |
void op_save_state (void) |
| ... | ... | |
| 1491 | 1769 |
void op_exit_tb (void) |
| 1492 | 1770 |
{
|
| 1493 | 1771 |
EXIT_TB(); |
| 1772 |
RETURN(); |
|
| 1494 | 1773 |
} |
| 1495 | 1774 |
|
| 1496 | 1775 |
void op_wait (void) |
| 1497 | 1776 |
{
|
| 1498 | 1777 |
env->halted = 1; |
| 1499 | 1778 |
CALL_FROM_TB1(do_raise_exception, EXCP_HLT); |
| 1779 |
RETURN(); |
|
| 1780 |
} |
|
| 1781 |
|
|
| 1782 |
/* Bitfield operations. */ |
|
| 1783 |
void op_ext(void) |
|
| 1784 |
{
|
|
| 1785 |
unsigned int pos = PARAM1; |
|
| 1786 |
unsigned int size = PARAM2; |
|
| 1787 |
|
|
| 1788 |
T0 = (T1 >> pos) & ((1 << size) - 1); |
|
| 1789 |
RETURN(); |
|
| 1790 |
} |
|
| 1791 |
|
|
| 1792 |
void op_ins(void) |
|
| 1793 |
{
|
|
| 1794 |
unsigned int pos = PARAM1; |
|
| 1795 |
unsigned int size = PARAM2; |
|
| 1796 |
target_ulong mask = ((1 << size) - 1) << pos; |
|
| 1797 |
|
|
| 1798 |
T0 = (T2 & ~mask) | ((T1 << pos) & mask); |
|
| 1799 |
RETURN(); |
|
| 1800 |
} |
|
| 1801 |
|
|
| 1802 |
void op_wsbh(void) |
|
| 1803 |
{
|
|
| 1804 |
T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF); |
|
| 1805 |
RETURN(); |
|
| 1806 |
} |
|
| 1807 |
|
|
| 1808 |
void op_dsbh(void) |
|
| 1809 |
{
|
|
| 1810 |
T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL); |
|
| 1811 |
RETURN(); |
|
| 1812 |
} |
|
| 1813 |
|
|
| 1814 |
void op_dshd(void) |
|
| 1815 |
{
|
|
| 1816 |
T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL); |
|
| 1817 |
RETURN(); |
|
| 1818 |
} |
|
| 1819 |
|
|
| 1820 |
void op_seb(void) |
|
| 1821 |
{
|
|
| 1822 |
T0 = ((T1 & 0xFF) ^ 0x80) - 0x80; |
|
| 1823 |
RETURN(); |
|
| 1824 |
} |
|
| 1825 |
|
|
| 1826 |
void op_seh(void) |
|
| 1827 |
{
|
|
| 1828 |
T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000; |
|
| 1829 |
RETURN(); |
|
| 1500 | 1830 |
} |
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