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# Date Author Comment
9a78eead 10/30/2010 11:01 am Stefan Weil

target-xxx: Use fprintf_function (format checking)

fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
  • target-i386/helper.c
  • target-mips/translate.c
  • target-ppc/translate.c

Cc: Blue Swirl <>
Signed-off-by: Stefan Weil <>...

ae0bfb79 10/13/2010 09:38 pm Blue Swirl

ppc: remove video.x

Only Mac-on-Linux stuff used video.x, OpenBIOS does not need it.

Remove video.x MoL hacks.

Signed-off-by: Alexander Graf <>
Signed-off-by: Blue Swirl <>

2c50e26e 09/30/2010 07:53 pm Edgar E. Iglesias

powerpc: Add a virtex5 ml507 refdesign board

Signed-off-by: Edgar E. Iglesias <>
Signed-off-by: Alexander Graf <>

a586e548 09/24/2010 11:01 pm Edgar E. Iglesias

powerpc: Improve emulation of the BookE MMU

Improve the emulation of the BookE MMU to be able to boot linux
on virtex5 boards.

Signed-off-by: Edgar E. Iglesias <>

a88790a1 07/03/2010 09:48 am Paolo Bonzini

remove exec-all.h inclusion from cpu.h

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Blue Swirl <>

10eb0cc0 07/03/2010 09:48 am Paolo Bonzini

move cpu_pc_from_tb to target-*/exec.h

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Blue Swirl <>

3c7b48b7 03/12/2010 08:44 pm Paul Brook

Target specific usermode cleanup

Disable various target specific code that is only relevant to system emulation.

Signed-off-by: Paul Brook <>

52705890 03/12/2010 06:28 pm Richard Henderson

Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.

Removes a set of ifdefs from exec.c.

Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other
than Alpha. This will be used for page_find_alloc, which is
supposed to be using virtual addresses in the first place....

e6bba2ef 02/27/2010 05:10 pm Nathan Froyd

target-ppc: fix SPE evcmp* instructions

The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bit
position. Because of this, the SPE evcmp* family of instructions would
store values in the result condition register that were also off by one
bit position....

73b01960 12/21/2009 05:03 pm Alexander Graf

PPC: Make DCR uint32_t

For what I know DCR is always 32 bits wide, so we should also use uint32_t to
pass it along the stacks.

This fixes a warning when compiling qemu-system-ppc64 with KVM enabled, making
it compile without --disable-werror

Signed-off-by: Alexander Graf <>...

b711de95 12/21/2009 02:52 pm Aurelien Jarno

PPC64: Fix alternate timebase

Fix the alternate time base the same way as the default timebase. SPR_ATBL
should return a 64-bit value on 64 bit implementations.

Signed-off-by: Aurelien Jarno <>

e3ea6529 12/21/2009 02:42 pm Alexander Graf

PPC64: Fix timebase

On PPC we have a 64-bit time base. Usually (PPC32) this is accessed using
two separate 32 bit SPR accesses to SPR_TBU and SPR_TBL.

On PPC64 the SPR_TBL register acts as 64 bit though, so we get the full
64 bits as return value. If we only take the lower ones, fine. But Linux...

d84bda46 11/07/2009 12:36 pm Blue Swirl

PPC: rename cpu_ppc_reset to cpu_reset for consistency

Signed-off-by: Blue Swirl <>

cb2dbfc3 10/23/2009 01:14 am Aurelien Jarno

target-ppc: move often used CPU fields at the top of the structure

Signed-off-by: Aurelien Jarno <>

c227f099 10/02/2009 12:12 am Anthony Liguori

Revert "Get rid of _t suffix"

In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem. Something
like this must be presented on the list first so people can provide input...

99a0949b 10/01/2009 09:45 pm malc

Get rid of _t suffix

Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <>

0b5c1ce8 08/24/2009 04:21 pm Nathan Froyd

cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal

handle_cpu_signal is very nearly copy-paste code for each target, with a
few minor variations. This patch sets up appropriate defaults for a
generic handle_cpu_signal and provides overrides for particular targets...

b11ebf64 08/16/2009 02:54 pm Blue Swirl

Replace REGX with PRIx64

Signed-off-by: Blue Swirl <>

90e189ec 08/16/2009 02:13 pm Blue Swirl

Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx

Signed-off-by: Blue Swirl <>

636aa200 08/16/2009 12:06 pm Blue Swirl

Replace always_inline with inline

We define inline as always_inline.

Signed-off-by: Blue Swirl <>

174c80d5 08/03/2009 07:33 pm Nathan Froyd

target-ppc: add cpu_set_tls

Signed-off-by: Nathan Froyd <>
Signed-off-by: malc <>

18b21a2f 08/03/2009 07:33 pm Nathan Froyd

target-ppc: retain l{w,d}arx loaded value

We do this so we can check on the corresponding stc{w,d}x. whether the
value has changed. It's a poor man's form of implementing atomic
operations and is valid only for NPTL usermode Linux emulation.

Signed-off-by: Nathan Froyd <>...

4425265b 08/03/2009 07:33 pm Nathan Froyd

target-ppc: add exceptions for conditional stores

Signed-off-by: Nathan Froyd <>
Signed-off-by: malc <>

d11f69b2 08/03/2009 07:33 pm Nathan Froyd

target-ppc: fix cpu_clone_regs

We only need to make sure that the clone syscall looks like it
succeeded, not clobber 60% of the register set.

Signed-off-by: Nathan Froyd <>
Signed-off-by: malc <>

8167ee88 07/16/2009 11:47 pm Blue Swirl

Update to a hopefully more future proof FSF address

Signed-off-by: Blue Swirl <>

1ad2134f 05/19/2009 06:17 pm Paul Brook

Hardware convenience library

The only target dependency for most hardware is sizeof(target_phys_addr_t).
Build these files into a convenience library, and use that instead of
building for every target.

Remove and poison various target specific macros to avoid bogus target...

c29b735c 05/16/2009 12:36 am Nathan Froyd

target-ppc: expose cpu capability flags

Do this so other pieces of code can make decisions based on the
capabilities of the CPU we're emulating.

Signed-off-by: Nathan Froyd <>
Signed-off-by: malc <>

fc1c67bc 04/28/2009 09:00 pm Blue Swirl

Fix PPC reset

7f70c937 03/13/2009 11:16 pm blueswir1

Make the ELF loader aware of backwards compatibility

Most 64 bit architectures I'm aware of support running 32 bit code
of the same architecture as well.

So x86_64 can run i386 code easily and ppc64 can run ppc code.

Unfortunately, the current checks are pretty strict. So you can only...

8eee0af9 03/07/2009 10:57 pm blueswir1

Keep SLB in-CPU

Real 970 CPUs have the SLB not memory backed, but inside the CPU.
This breaks bridge mode for 970 for now, but at least keeps us from
overwriting physical addresses 0x0 - 0x300, rendering our interrupt
handlers useless.

I put in a stub for bridge mode operation that could be enabled...

5b5aba4f 03/07/2009 10:51 pm blueswir1

Implement large pages

The current SLB/PTE code does not support large pages, which are
required by Linux, as it boots up with the kernel regions up as large.

This patch implements large page support, so we can run Linux.

Signed-off-by: Alexander Graf <>...

f6b868fc 03/07/2009 10:50 pm blueswir1

Implement slbmte

In order to modify SLB entries on recent PPC64 machines, the slbmte
instruction is used.

This patch implements the slbmte instruction and makes the "bridge"
mode code use the slb set functions, so we can move the SLB into
the CPU struct later....

c2764719 03/07/2009 05:24 pm pbrook

The _exit syscall is used for both thread termination in NPTL applications,
and process termination in legacy applications. Try to guess which we want
based on the presence of multiple threads.

Also implement locking when modifying the CPU list.

Signed-off-by: Paul Brook <>...

9fdc60bf 03/02/2009 06:42 pm aurel32

kvm/powerpc: Add irq support for E500 core

Signed-off-by: Liu Yu <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6662 c046a42c-6fe2-441c-8c8c-71466251a162

3a616592 02/08/2009 02:50 pm blueswir1

Load 32 bit ELF BIOS images also on PPC64

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6554 c046a42c-6fe2-441c-8c8c-71466251a162

fbd265b6 02/03/2009 09:55 pm aurel32

Rename spe_status to vec_status

Only one of Altivec and SPE will be available on a given chip.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6506 c046a42c-6fe2-441c-8c8c-71466251a162

0f6fbcbc 02/03/2009 09:55 pm aurel32

Add f field to ppc_avr_t

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6505 c046a42c-6fe2-441c-8c8c-71466251a162

fad6cb1a 01/05/2009 12:05 am aurel32

Update FSF address in GPL/LGPL boilerplate

The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <>
Signed-off-by: Aurelien Jarno <>...

6fa724a3 01/03/2009 04:04 pm aurel32

Add vscr access macros.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6158 c046a42c-6fe2-441c-8c8c-71466251a162

2231ef10 12/19/2008 12:43 am aurel32

target-ppc: fix type of spe_acc.

ACC is a 64-bit register and needs to be specified as such regardless of
the target.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6090 c046a42c-6fe2-441c-8c8c-71466251a162

ab5f265d 12/15/2008 09:03 am aurel32

target-ppc: add signed fields to ppc_avr_t.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6042 c046a42c-6fe2-441c-8c8c-71466251a162

93220573 12/12/2008 12:42 am aurel32

target-ppc: remove remaining warnings

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5991 c046a42c-6fe2-441c-8c8c-71466251a162

45d827d2 12/07/2008 03:40 pm aurel32

target-ppc: convert SPR accesses to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5910 c046a42c-6fe2-441c-8c8c-71466251a162

8983da70 12/07/2008 12:01 am aurel32

target-ppc: remove dead code

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5896 c046a42c-6fe2-441c-8c8c-71466251a162

74d37793 12/06/2008 11:46 pm aurel32

target-ppc: convert SLB/TLB instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5895 c046a42c-6fe2-441c-8c8c-71466251a162

2cbd949d 11/30/2008 06:23 pm aurel32

Common cpu_loop_exit prototype

All archs use the same cpu_loop_exit, so move the prototype in a common
header. i386 was carrying a __hidden attribute, but that was empty for
this arch anyway.

Signed-off-by: Jan Kiszka <>
Signed-off-by: Aurelien Jarno <>...

01a4afeb 11/27/2008 09:30 pm aurel32

target-ppc: convert POWER2 load/store instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5805 c046a42c-6fe2-441c-8c8c-71466251a162

6a6ae23f 11/27/2008 09:30 pm aurel32

target-ppc: convert SPE load/store to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5804 c046a42c-6fe2-441c-8c8c-71466251a162

fe1e5c53 11/24/2008 10:47 am aurel32

target-ppc: convert altivec load/store to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5787 c046a42c-6fe2-441c-8c8c-71466251a162

af12906f 11/19/2008 06:10 pm aurel32

target-ppc: convert fp ops to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5754 c046a42c-6fe2-441c-8c8c-71466251a162

6b917547 11/18/2008 09:46 pm aliguori

Refactor translation block CPU state handling (Jan Kiszka)

This patch refactors the way the CPU state is handled that is associated
with a TB. The basic motivation is to move more arch specific code out
of generic files. Specifically the long #ifdef clutter in tb_find_fast()...

622ed360 11/18/2008 09:36 pm aliguori

Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)

as macros should be avoided when possible.

Signed-off-by: Jan Kiszka <>
Signed-off-by: Anthony Liguori <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162

57951c27 11/10/2008 01:10 pm aurel32

target-ppc: convert most SPE integer instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5668 c046a42c-6fe2-441c-8c8c-71466251a162

4870167d 11/08/2008 10:57 am aurel32

target-ppc: fix tcg fatal error on i386 host

It looks like the i386 runs out of registers for allocation due
to too many global registers allocated by the ppc target.

Here is a quick and dirty fix that seems to solve the problem.
This should be considered as temporary....

8d71247e 11/01/2008 02:53 am aurel32

target-ppc: xer access prototypes no more used & implemented

Revision 5500 of the qemu repository removed all code using
ppc_load_xer & ppc_store_xer as well as their implementation.

Another patch fixes it's usage in kvm-userspace for powerpc, but I think...

e1571908 10/21/2008 02:31 pm aurel32

target-ppc: convert crf related instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5505 c046a42c-6fe2-441c-8c8c-71466251a162

3d7b417e 10/21/2008 02:28 pm aurel32

target-ppc: Convert XER accesses to TCG

Define XER bits as a single register and access them individually to
avoid defining 5 32-bit registers (TCG doesn't permit to map 8-bit
registers).

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162

b55266b5 09/20/2008 11:07 am blueswir1

Suppress gcc 4.x -Wpointer-sign (included in -Wall) warnings

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5275 c046a42c-6fe2-441c-8c8c-71466251a162

47e4661c 09/04/2008 08:06 pm aurel32

ppc: Convert CRF moves to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5158 c046a42c-6fe2-441c-8c8c-71466251a162

bd7d9a6d 09/04/2008 08:26 am aurel32

ppc: cleanup register types

- use target_ulong for gpr and dyngen registers
- remove ppc_gpr_t type
- define 64-bit dyngen registers for GPE register on 32-bit targets

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5154 c046a42c-6fe2-441c-8c8c-71466251a162

f78fb44e 09/04/2008 08:25 am aurel32

ppc: Convert GPR moves to TCG

Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with tcg_gen_mov_tl.
Introduce TCG variables cpu_gpr[0..31].

For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64.
Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and helpers...

9656f324 07/01/2008 11:01 pm pbrook

Move interrupt_request and user_mode_only to common cpu state.
Save and restore env->interrupt_request and env->halted.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162

b3c7724c 06/30/2008 07:31 pm pbrook

Move CPU save/load registration to common code.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162

2e70f6ef 06/29/2008 04:03 am pbrook

Add instruction counter.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162

f8ed7070 05/30/2008 08:54 pm pbrook

Fix typo.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162

6e68e076 05/30/2008 08:22 pm pbrook

Move clone() register setup to target specific code. Handle fork-like clone.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162

9133e39b 05/29/2008 01:08 pm bellard

Push common interrupt variables to cpu-defs.h (Glauber Costa)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162

ce5232c5 05/28/2008 08:14 pm bellard

moved halted field to CPU_COMMON

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4609 c046a42c-6fe2-441c-8c8c-71466251a162

f9320410 05/06/2008 05:58 pm aurel32

PPC: fix definition of msr_spe

(Tristan Gingold)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4361 c046a42c-6fe2-441c-8c8c-71466251a162

e9b34b37 12/10/2007 10:13 am j_mayer

Cleanup: remove useless TARGET_GPR_BITS definition.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3799 c046a42c-6fe2-441c-8c8c-71466251a162

4e777442 12/10/2007 09:40 am j_mayer

Fix PowerPC 74xx definitions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3798 c046a42c-6fe2-441c-8c8c-71466251a162

6b542af7 11/24/2007 04:03 am j_mayer

Fix incorrect debug prints (reported by Paul Brook).
Remove obsolete / duplicated debug prints and improve output consistency.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3725 c046a42c-6fe2-441c-8c8c-71466251a162

69facb78 11/24/2007 12:16 am j_mayer

Revert foolish patch.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3724 c046a42c-6fe2-441c-8c8c-71466251a162

9b605b9e 11/23/2007 07:33 pm pbrook

Fix ppc32 register dumps on 64-bit hosts.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3723 c046a42c-6fe2-441c-8c8c-71466251a162

bd928eba 11/21/2007 03:08 pm j_mayer

Fix PowerPC 7xx definitions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3713 c046a42c-6fe2-441c-8c8c-71466251a162

082c6681 11/19/2007 03:22 pm j_mayer

Remove shared macro used to define PowerPC implementations instructions sets:
tend more to propagate bugged definition than simplify the code.
Check and fix PowerPC 6xx implementations definitions.
Misc fixes in PowerPC CPU list.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3707 c046a42c-6fe2-441c-8c8c-71466251a162

add78955 11/19/2007 01:41 pm j_mayer

PowerPC 620 MMU do not have the same exact behavior as standard
64 bits PowerPC ones.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3706 c046a42c-6fe2-441c-8c8c-71466251a162

4018bae9 11/19/2007 03:48 am j_mayer

New PowerPC CPU flag to define the decrementer and time-base source clock.
Use it to properly initialize the clock for the PreP target.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3701 c046a42c-6fe2-441c-8c8c-71466251a162

4c1b1bfe 11/18/2007 01:14 am j_mayer

Improve PowerPC instructions set dump.
Remove meaningless define from cpu.h
Misc cleanups.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3682 c046a42c-6fe2-441c-8c8c-71466251a162

80d11f44 11/18/2007 01:02 am j_mayer

Add definitions for Freescale PowerPC implementations,
ie MPC5xx, MPC8xx, e200, e300, e500 and e600 cores.
Make those CPUs and PowerPC 440 available for user-mode emulation,
thus providing a way of testing their implementation specific instructions.

...

b4095fed 11/18/2007 12:42 am j_mayer

Define Freescale cores specific MMU model, exceptions and input bus.
(but do not provide any actual implementation).

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3680 c046a42c-6fe2-441c-8c8c-71466251a162

a4f30719 11/17/2007 11:14 pm j_mayer

PowerPC hypervisor mode is not fundamentally available only for PowerPC 64.
Remove TARGET_PPC64 dependency and add code provision to be able
to define a fake 32 bits CPU with hypervisor feature support.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3678 c046a42c-6fe2-441c-8c8c-71466251a162

7820dbf3 11/17/2007 04:16 am j_mayer

Make the PowerPC MMU model, exception model and input bus model
typedefed enums.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3660 c046a42c-6fe2-441c-8c8c-71466251a162

7b62a955 11/17/2007 04:04 am j_mayer

Add missing definition for number of input pins for the PowerPC 970 bus.
Use proper INPUT_NB definitions to allocate PowerPC input pins structure,
fixing a buffer overflow in the 6xx bus case.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3659 c046a42c-6fe2-441c-8c8c-71466251a162

b172c56a 11/17/2007 03:37 am j_mayer

Always make all PowerPC exception definitions visible.
Always make the hypervisor timers available.
Remove all TARGET_PPC64H checks, keeping a few if (0) tests for cases
that cannot be properly handled with the current PowerPC CPU definition.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3656 c046a42c-6fe2-441c-8c8c-71466251a162

7863667f 11/16/2007 04:11 pm j_mayer

Always make PowerPC hypervisor mode memory accesses and instructions
available for full system emulation, then removing all #if TARGET_PPC64H
from micro-ops and code translator.
Add new macros to dramatically simplify memory access tables definitions
in target-ppc/translate.c....

57c26279 11/14/2007 08:45 pm j_mayer

Fix PowerPC targets compilation on 32 bits hosts:
now that the SPE extension is available for all targets,
we always need to have some 64 bits temporary registers.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3647 c046a42c-6fe2-441c-8c8c-71466251a162

65d6c0f3 11/13/2007 01:29 am j_mayer

PowerPC SPE extension fix: must always preserve GPR high bits when
running in 32 bits mode.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3631 c046a42c-6fe2-441c-8c8c-71466251a162

3cd7d1dd 11/12/2007 03:56 am j_mayer

Allow use of SPE extension by all PowerPC targets,
adding gprh registers to store GPR MSBs when GPRs are 32 bits.
Remove not-needed-anymore ppcemb-linux-user target.
Keep ppcemb-softmmu target, which provides 1kB pages support
and 36 bits physical address space....

ee4e83ed 11/11/2007 01:51 am j_mayer

Allow selection of PowerPC CPU giving a PVR.
Remove unused pvr_mask field from CPU definition.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3571 c046a42c-6fe2-441c-8c8c-71466251a162

aaed909a 11/10/2007 05:15 pm bellard

added cpu_model parameter to cpu_init()

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162

056401ea 11/04/2007 04:55 am j_mayer

PowerPC 601 need specific callbacks for its BATs setup.
Implement PowerPC 601 HID0 register, needed for little-endian mode support.
As a consequence, we need to merge hflags coming from MSR with other ones.
Use little-endian mode from hflags instead of MSR during code translation....

faadf50e 11/03/2007 03:37 pm j_mayer PowerPC MMU and exception fixes:
  • PowerPC 601 (and probably POWER/POWER2) uses a different BAT format than
    later PowerPC implementation.
  • Bugfix in BATs check: must not stop after 4 BATs when more are provided.
  • Enable POWER 'rac' instruction.
  • Fix exception prefix for all supported PowerPC implementations....
7c58044c 10/27/2007 08:54 pm j_mayer

Fix PowerPC FPSCR update and floating-point exception generation
in most useful cases.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3458 c046a42c-6fe2-441c-8c8c-71466251a162

cd346349 10/26/2007 02:27 am j_mayer

Add PowerPC power-management state check callback.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3441 c046a42c-6fe2-441c-8c8c-71466251a162

0411a972 10/26/2007 12:35 am j_mayer

Gprof prooved the PowerPC emulation spent too much time in MSR load and store
routines. Coming back to a raw MSR storage model then speed-up the emulation.
Improve fast MSR updates (wrtee wrteei and mtriee cases).
Share rfi family instructions helpers code to avoid bug in duplicated code....

b227a8e9 10/14/2007 01:21 pm j_mayer

Properly implement non-execute bit on PowerPC segments and PTEs.
Fix page protection bits for PowerPC 64 MMU.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3395 c046a42c-6fe2-441c-8c8c-71466251a162

d68f1306 10/14/2007 12:27 pm j_mayer

Merge PowerPC 620 input bus definitions with standard PowerPC 6xx.
Avoid hardcoding PowerPC interrupts definitions to ease updates.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3393 c046a42c-6fe2-441c-8c8c-71466251a162

a13d7523 10/14/2007 12:14 pm j_mayer

There is no need of a specific MMU model for PowerPC 601.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3392 c046a42c-6fe2-441c-8c8c-71466251a162

6ebbf390 10/14/2007 10:07 am j_mayer

Replace is_user variable with mmu_idx in softmmu core,
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
and #ifdef TARGET_xxx in softmmu core functions....