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1
/*
2
 *  PowerPC CPU initialization for qemu.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
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 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
20

    
21
/* A lot of PowerPC definition have been included here.
22
 * Most of them are not usable for now but have been kept
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 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24
 */
25

    
26
#include "dis-asm.h"
27

    
28
//#define PPC_DUMP_CPU
29
//#define PPC_DEBUG_SPR
30
//#define PPC_DEBUG_IRQ
31

    
32
struct ppc_def_t {
33
    const unsigned char *name;
34
    uint32_t pvr;
35
    uint32_t pvr_mask;
36
    uint64_t insns_flags;
37
    uint64_t msr_mask;
38
    uint8_t mmu_model;
39
    uint8_t excp_model;
40
    uint8_t bus_model;
41
    uint8_t pad;
42
    uint32_t flags;
43
    int bfd_mach;
44
    void (*init_proc)(CPUPPCState *env);
45
};
46

    
47
/* For user-mode emulation, we don't emulate any IRQ controller */
48
#if defined(CONFIG_USER_ONLY)
49
#define PPC_IRQ_INIT_FN(name)                                                 \
50
static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \
51
{                                                                             \
52
}
53
#else
54
#define PPC_IRQ_INIT_FN(name)                                                 \
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void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
56
#endif
57

    
58
PPC_IRQ_INIT_FN(40x);
59
PPC_IRQ_INIT_FN(6xx);
60
PPC_IRQ_INIT_FN(970);
61

    
62
/* Generic callbacks:
63
 * do nothing but store/retrieve spr value
64
 */
65
#ifdef PPC_DUMP_SPR_ACCESSES
66
static void spr_read_generic (void *opaque, int sprn)
67
{
68
    gen_op_load_dump_spr(sprn);
69
}
70

    
71
static void spr_write_generic (void *opaque, int sprn)
72
{
73
    gen_op_store_dump_spr(sprn);
74
}
75
#else
76
static void spr_read_generic (void *opaque, int sprn)
77
{
78
    gen_op_load_spr(sprn);
79
}
80

    
81
static void spr_write_generic (void *opaque, int sprn)
82
{
83
    gen_op_store_spr(sprn);
84
}
85
#endif
86

    
87
#if !defined(CONFIG_USER_ONLY)
88
static void spr_write_clear (void *opaque, int sprn)
89
{
90
    gen_op_mask_spr(sprn);
91
}
92
#endif
93

    
94
/* SPR common to all PowerPC */
95
/* XER */
96
static void spr_read_xer (void *opaque, int sprn)
97
{
98
    gen_op_load_xer();
99
}
100

    
101
static void spr_write_xer (void *opaque, int sprn)
102
{
103
    gen_op_store_xer();
104
}
105

    
106
/* LR */
107
static void spr_read_lr (void *opaque, int sprn)
108
{
109
    gen_op_load_lr();
110
}
111

    
112
static void spr_write_lr (void *opaque, int sprn)
113
{
114
    gen_op_store_lr();
115
}
116

    
117
/* CTR */
118
static void spr_read_ctr (void *opaque, int sprn)
119
{
120
    gen_op_load_ctr();
121
}
122

    
123
static void spr_write_ctr (void *opaque, int sprn)
124
{
125
    gen_op_store_ctr();
126
}
127

    
128
/* User read access to SPR */
129
/* USPRx */
130
/* UMMCRx */
131
/* UPMCx */
132
/* USIA */
133
/* UDECR */
134
static void spr_read_ureg (void *opaque, int sprn)
135
{
136
    gen_op_load_spr(sprn + 0x10);
137
}
138

    
139
/* SPR common to all non-embedded PowerPC */
140
/* DECR */
141
#if !defined(CONFIG_USER_ONLY)
142
static void spr_read_decr (void *opaque, int sprn)
143
{
144
    gen_op_load_decr();
145
}
146

    
147
static void spr_write_decr (void *opaque, int sprn)
148
{
149
    gen_op_store_decr();
150
}
151
#endif
152

    
153
/* SPR common to all non-embedded PowerPC, except 601 */
154
/* Time base */
155
static void spr_read_tbl (void *opaque, int sprn)
156
{
157
    gen_op_load_tbl();
158
}
159

    
160
static void spr_read_tbu (void *opaque, int sprn)
161
{
162
    gen_op_load_tbu();
163
}
164

    
165
__attribute__ (( unused ))
166
static void spr_read_atbl (void *opaque, int sprn)
167
{
168
    gen_op_load_atbl();
169
}
170

    
171
__attribute__ (( unused ))
172
static void spr_read_atbu (void *opaque, int sprn)
173
{
174
    gen_op_load_atbu();
175
}
176

    
177
#if !defined(CONFIG_USER_ONLY)
178
static void spr_write_tbl (void *opaque, int sprn)
179
{
180
    gen_op_store_tbl();
181
}
182

    
183
static void spr_write_tbu (void *opaque, int sprn)
184
{
185
    gen_op_store_tbu();
186
}
187

    
188
__attribute__ (( unused ))
189
static void spr_write_atbl (void *opaque, int sprn)
190
{
191
    gen_op_store_atbl();
192
}
193

    
194
__attribute__ (( unused ))
195
static void spr_write_atbu (void *opaque, int sprn)
196
{
197
    gen_op_store_atbu();
198
}
199
#endif
200

    
201
#if !defined(CONFIG_USER_ONLY)
202
/* IBAT0U...IBAT0U */
203
/* IBAT0L...IBAT7L */
204
static void spr_read_ibat (void *opaque, int sprn)
205
{
206
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
207
}
208

    
209
static void spr_read_ibat_h (void *opaque, int sprn)
210
{
211
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
212
}
213

    
214
static void spr_write_ibatu (void *opaque, int sprn)
215
{
216
    gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
217
}
218

    
219
static void spr_write_ibatu_h (void *opaque, int sprn)
220
{
221
    gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
222
}
223

    
224
static void spr_write_ibatl (void *opaque, int sprn)
225
{
226
    gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
227
}
228

    
229
static void spr_write_ibatl_h (void *opaque, int sprn)
230
{
231
    gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
232
}
233

    
234
/* DBAT0U...DBAT7U */
235
/* DBAT0L...DBAT7L */
236
static void spr_read_dbat (void *opaque, int sprn)
237
{
238
    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
239
}
240

    
241
static void spr_read_dbat_h (void *opaque, int sprn)
242
{
243
    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
244
}
245

    
246
static void spr_write_dbatu (void *opaque, int sprn)
247
{
248
    gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
249
}
250

    
251
static void spr_write_dbatu_h (void *opaque, int sprn)
252
{
253
    gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
254
}
255

    
256
static void spr_write_dbatl (void *opaque, int sprn)
257
{
258
    gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
259
}
260

    
261
static void spr_write_dbatl_h (void *opaque, int sprn)
262
{
263
    gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
264
}
265

    
266
/* SDR1 */
267
static void spr_read_sdr1 (void *opaque, int sprn)
268
{
269
    gen_op_load_sdr1();
270
}
271

    
272
static void spr_write_sdr1 (void *opaque, int sprn)
273
{
274
    gen_op_store_sdr1();
275
}
276

    
277
/* 64 bits PowerPC specific SPRs */
278
/* ASR */
279
#if defined(TARGET_PPC64)
280
__attribute__ (( unused ))
281
static void spr_read_asr (void *opaque, int sprn)
282
{
283
    gen_op_load_asr();
284
}
285

    
286
__attribute__ (( unused ))
287
static void spr_write_asr (void *opaque, int sprn)
288
{
289
    gen_op_store_asr();
290
}
291
#endif
292
#endif
293

    
294
/* PowerPC 601 specific registers */
295
/* RTC */
296
static void spr_read_601_rtcl (void *opaque, int sprn)
297
{
298
    gen_op_load_601_rtcl();
299
}
300

    
301
static void spr_read_601_rtcu (void *opaque, int sprn)
302
{
303
    gen_op_load_601_rtcu();
304
}
305

    
306
#if !defined(CONFIG_USER_ONLY)
307
static void spr_write_601_rtcu (void *opaque, int sprn)
308
{
309
    gen_op_store_601_rtcu();
310
}
311

    
312
static void spr_write_601_rtcl (void *opaque, int sprn)
313
{
314
    gen_op_store_601_rtcl();
315
}
316
#endif
317

    
318
/* Unified bats */
319
#if !defined(CONFIG_USER_ONLY)
320
static void spr_read_601_ubat (void *opaque, int sprn)
321
{
322
    gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
323
}
324

    
325
static void spr_write_601_ubatu (void *opaque, int sprn)
326
{
327
    gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
328
}
329

    
330
static void spr_write_601_ubatl (void *opaque, int sprn)
331
{
332
    gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
333
}
334
#endif
335

    
336
/* PowerPC 40x specific registers */
337
#if !defined(CONFIG_USER_ONLY)
338
static void spr_read_40x_pit (void *opaque, int sprn)
339
{
340
    gen_op_load_40x_pit();
341
}
342

    
343
static void spr_write_40x_pit (void *opaque, int sprn)
344
{
345
    gen_op_store_40x_pit();
346
}
347

    
348
static void spr_write_40x_dbcr0 (void *opaque, int sprn)
349
{
350
    DisasContext *ctx = opaque;
351

    
352
    gen_op_store_40x_dbcr0();
353
    /* We must stop translation as we may have rebooted */
354
    GEN_STOP(ctx);
355
}
356

    
357
static void spr_write_40x_sler (void *opaque, int sprn)
358
{
359
    gen_op_store_40x_sler();
360
}
361

    
362
static void spr_write_booke_tcr (void *opaque, int sprn)
363
{
364
    gen_op_store_booke_tcr();
365
}
366

    
367
static void spr_write_booke_tsr (void *opaque, int sprn)
368
{
369
    gen_op_store_booke_tsr();
370
}
371
#endif
372

    
373
/* PowerPC 403 specific registers */
374
/* PBL1 / PBU1 / PBL2 / PBU2 */
375
#if !defined(CONFIG_USER_ONLY)
376
static void spr_read_403_pbr (void *opaque, int sprn)
377
{
378
    gen_op_load_403_pb(sprn - SPR_403_PBL1);
379
}
380

    
381
static void spr_write_403_pbr (void *opaque, int sprn)
382
{
383
    gen_op_store_403_pb(sprn - SPR_403_PBL1);
384
}
385

    
386
static void spr_write_pir (void *opaque, int sprn)
387
{
388
    gen_op_store_pir();
389
}
390
#endif
391

    
392
#if !defined(CONFIG_USER_ONLY)
393
/* Callback used to write the exception vector base */
394
static void spr_write_excp_prefix (void *opaque, int sprn)
395
{
396
    gen_op_store_excp_prefix();
397
    gen_op_store_spr(sprn);
398
}
399

    
400
static void spr_write_excp_vector (void *opaque, int sprn)
401
{
402
    DisasContext *ctx = opaque;
403

    
404
    if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
405
        gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
406
        gen_op_store_spr(sprn);
407
    } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
408
        gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
409
        gen_op_store_spr(sprn);
410
    } else {
411
        printf("Trying to write an unknown exception vector %d %03x\n",
412
               sprn, sprn);
413
        GEN_EXCP_PRIVREG(ctx);
414
    }
415
}
416
#endif
417

    
418
#if defined(CONFIG_USER_ONLY)
419
#define spr_register(env, num, name, uea_read, uea_write,                     \
420
                     oea_read, oea_write, initial_value)                      \
421
do {                                                                          \
422
     _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
423
} while (0)
424
static inline void _spr_register (CPUPPCState *env, int num,
425
                                  const unsigned char *name,
426
                                  void (*uea_read)(void *opaque, int sprn),
427
                                  void (*uea_write)(void *opaque, int sprn),
428
                                  target_ulong initial_value)
429
#else
430
static inline void spr_register (CPUPPCState *env, int num,
431
                                 const unsigned char *name,
432
                                 void (*uea_read)(void *opaque, int sprn),
433
                                 void (*uea_write)(void *opaque, int sprn),
434
                                 void (*oea_read)(void *opaque, int sprn),
435
                                 void (*oea_write)(void *opaque, int sprn),
436
                                 target_ulong initial_value)
437
#endif
438
{
439
    ppc_spr_t *spr;
440

    
441
    spr = &env->spr_cb[num];
442
    if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
443
#if !defined(CONFIG_USER_ONLY)
444
        spr->oea_read != NULL || spr->oea_write != NULL ||
445
#endif
446
        spr->uea_read != NULL || spr->uea_write != NULL) {
447
        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
448
        exit(1);
449
    }
450
#if defined(PPC_DEBUG_SPR)
451
    printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
452
           initial_value);
453
#endif
454
    spr->name = name;
455
    spr->uea_read = uea_read;
456
    spr->uea_write = uea_write;
457
#if !defined(CONFIG_USER_ONLY)
458
    spr->oea_read = oea_read;
459
    spr->oea_write = oea_write;
460
#endif
461
    env->spr[num] = initial_value;
462
}
463

    
464
/* Generic PowerPC SPRs */
465
static void gen_spr_generic (CPUPPCState *env)
466
{
467
    /* Integer processing */
468
    spr_register(env, SPR_XER, "XER",
469
                 &spr_read_xer, &spr_write_xer,
470
                 &spr_read_xer, &spr_write_xer,
471
                 0x00000000);
472
    /* Branch contol */
473
    spr_register(env, SPR_LR, "LR",
474
                 &spr_read_lr, &spr_write_lr,
475
                 &spr_read_lr, &spr_write_lr,
476
                 0x00000000);
477
    spr_register(env, SPR_CTR, "CTR",
478
                 &spr_read_ctr, &spr_write_ctr,
479
                 &spr_read_ctr, &spr_write_ctr,
480
                 0x00000000);
481
    /* Interrupt processing */
482
    spr_register(env, SPR_SRR0, "SRR0",
483
                 SPR_NOACCESS, SPR_NOACCESS,
484
                 &spr_read_generic, &spr_write_generic,
485
                 0x00000000);
486
    spr_register(env, SPR_SRR1, "SRR1",
487
                 SPR_NOACCESS, SPR_NOACCESS,
488
                 &spr_read_generic, &spr_write_generic,
489
                 0x00000000);
490
    /* Processor control */
491
    spr_register(env, SPR_SPRG0, "SPRG0",
492
                 SPR_NOACCESS, SPR_NOACCESS,
493
                 &spr_read_generic, &spr_write_generic,
494
                 0x00000000);
495
    spr_register(env, SPR_SPRG1, "SPRG1",
496
                 SPR_NOACCESS, SPR_NOACCESS,
497
                 &spr_read_generic, &spr_write_generic,
498
                 0x00000000);
499
    spr_register(env, SPR_SPRG2, "SPRG2",
500
                 SPR_NOACCESS, SPR_NOACCESS,
501
                 &spr_read_generic, &spr_write_generic,
502
                 0x00000000);
503
    spr_register(env, SPR_SPRG3, "SPRG3",
504
                 SPR_NOACCESS, SPR_NOACCESS,
505
                 &spr_read_generic, &spr_write_generic,
506
                 0x00000000);
507
}
508

    
509
/* SPR common to all non-embedded PowerPC, including 601 */
510
static void gen_spr_ne_601 (CPUPPCState *env)
511
{
512
    /* Exception processing */
513
    spr_register(env, SPR_DSISR, "DSISR",
514
                 SPR_NOACCESS, SPR_NOACCESS,
515
                 &spr_read_generic, &spr_write_generic,
516
                 0x00000000);
517
    spr_register(env, SPR_DAR, "DAR",
518
                 SPR_NOACCESS, SPR_NOACCESS,
519
                 &spr_read_generic, &spr_write_generic,
520
                 0x00000000);
521
    /* Timer */
522
    spr_register(env, SPR_DECR, "DECR",
523
                 SPR_NOACCESS, SPR_NOACCESS,
524
                 &spr_read_decr, &spr_write_decr,
525
                 0x00000000);
526
    /* Memory management */
527
    spr_register(env, SPR_SDR1, "SDR1",
528
                 SPR_NOACCESS, SPR_NOACCESS,
529
                 &spr_read_sdr1, &spr_write_sdr1,
530
                 0x00000000);
531
}
532

    
533
/* BATs 0-3 */
534
static void gen_low_BATs (CPUPPCState *env)
535
{
536
#if !defined(CONFIG_USER_ONLY)
537
    spr_register(env, SPR_IBAT0U, "IBAT0U",
538
                 SPR_NOACCESS, SPR_NOACCESS,
539
                 &spr_read_ibat, &spr_write_ibatu,
540
                 0x00000000);
541
    spr_register(env, SPR_IBAT0L, "IBAT0L",
542
                 SPR_NOACCESS, SPR_NOACCESS,
543
                 &spr_read_ibat, &spr_write_ibatl,
544
                 0x00000000);
545
    spr_register(env, SPR_IBAT1U, "IBAT1U",
546
                 SPR_NOACCESS, SPR_NOACCESS,
547
                 &spr_read_ibat, &spr_write_ibatu,
548
                 0x00000000);
549
    spr_register(env, SPR_IBAT1L, "IBAT1L",
550
                 SPR_NOACCESS, SPR_NOACCESS,
551
                 &spr_read_ibat, &spr_write_ibatl,
552
                 0x00000000);
553
    spr_register(env, SPR_IBAT2U, "IBAT2U",
554
                 SPR_NOACCESS, SPR_NOACCESS,
555
                 &spr_read_ibat, &spr_write_ibatu,
556
                 0x00000000);
557
    spr_register(env, SPR_IBAT2L, "IBAT2L",
558
                 SPR_NOACCESS, SPR_NOACCESS,
559
                 &spr_read_ibat, &spr_write_ibatl,
560
                 0x00000000);
561
    spr_register(env, SPR_IBAT3U, "IBAT3U",
562
                 SPR_NOACCESS, SPR_NOACCESS,
563
                 &spr_read_ibat, &spr_write_ibatu,
564
                 0x00000000);
565
    spr_register(env, SPR_IBAT3L, "IBAT3L",
566
                 SPR_NOACCESS, SPR_NOACCESS,
567
                 &spr_read_ibat, &spr_write_ibatl,
568
                 0x00000000);
569
    spr_register(env, SPR_DBAT0U, "DBAT0U",
570
                 SPR_NOACCESS, SPR_NOACCESS,
571
                 &spr_read_dbat, &spr_write_dbatu,
572
                 0x00000000);
573
    spr_register(env, SPR_DBAT0L, "DBAT0L",
574
                 SPR_NOACCESS, SPR_NOACCESS,
575
                 &spr_read_dbat, &spr_write_dbatl,
576
                 0x00000000);
577
    spr_register(env, SPR_DBAT1U, "DBAT1U",
578
                 SPR_NOACCESS, SPR_NOACCESS,
579
                 &spr_read_dbat, &spr_write_dbatu,
580
                 0x00000000);
581
    spr_register(env, SPR_DBAT1L, "DBAT1L",
582
                 SPR_NOACCESS, SPR_NOACCESS,
583
                 &spr_read_dbat, &spr_write_dbatl,
584
                 0x00000000);
585
    spr_register(env, SPR_DBAT2U, "DBAT2U",
586
                 SPR_NOACCESS, SPR_NOACCESS,
587
                 &spr_read_dbat, &spr_write_dbatu,
588
                 0x00000000);
589
    spr_register(env, SPR_DBAT2L, "DBAT2L",
590
                 SPR_NOACCESS, SPR_NOACCESS,
591
                 &spr_read_dbat, &spr_write_dbatl,
592
                 0x00000000);
593
    spr_register(env, SPR_DBAT3U, "DBAT3U",
594
                 SPR_NOACCESS, SPR_NOACCESS,
595
                 &spr_read_dbat, &spr_write_dbatu,
596
                 0x00000000);
597
    spr_register(env, SPR_DBAT3L, "DBAT3L",
598
                 SPR_NOACCESS, SPR_NOACCESS,
599
                 &spr_read_dbat, &spr_write_dbatl,
600
                 0x00000000);
601
    env->nb_BATs += 4;
602
#endif
603
}
604

    
605
/* BATs 4-7 */
606
static void gen_high_BATs (CPUPPCState *env)
607
{
608
#if !defined(CONFIG_USER_ONLY)
609
    spr_register(env, SPR_IBAT4U, "IBAT4U",
610
                 SPR_NOACCESS, SPR_NOACCESS,
611
                 &spr_read_ibat_h, &spr_write_ibatu_h,
612
                 0x00000000);
613
    spr_register(env, SPR_IBAT4L, "IBAT4L",
614
                 SPR_NOACCESS, SPR_NOACCESS,
615
                 &spr_read_ibat_h, &spr_write_ibatl_h,
616
                 0x00000000);
617
    spr_register(env, SPR_IBAT5U, "IBAT5U",
618
                 SPR_NOACCESS, SPR_NOACCESS,
619
                 &spr_read_ibat_h, &spr_write_ibatu_h,
620
                 0x00000000);
621
    spr_register(env, SPR_IBAT5L, "IBAT5L",
622
                 SPR_NOACCESS, SPR_NOACCESS,
623
                 &spr_read_ibat_h, &spr_write_ibatl_h,
624
                 0x00000000);
625
    spr_register(env, SPR_IBAT6U, "IBAT6U",
626
                 SPR_NOACCESS, SPR_NOACCESS,
627
                 &spr_read_ibat_h, &spr_write_ibatu_h,
628
                 0x00000000);
629
    spr_register(env, SPR_IBAT6L, "IBAT6L",
630
                 SPR_NOACCESS, SPR_NOACCESS,
631
                 &spr_read_ibat_h, &spr_write_ibatl_h,
632
                 0x00000000);
633
    spr_register(env, SPR_IBAT7U, "IBAT7U",
634
                 SPR_NOACCESS, SPR_NOACCESS,
635
                 &spr_read_ibat_h, &spr_write_ibatu_h,
636
                 0x00000000);
637
    spr_register(env, SPR_IBAT7L, "IBAT7L",
638
                 SPR_NOACCESS, SPR_NOACCESS,
639
                 &spr_read_ibat_h, &spr_write_ibatl_h,
640
                 0x00000000);
641
    spr_register(env, SPR_DBAT4U, "DBAT4U",
642
                 SPR_NOACCESS, SPR_NOACCESS,
643
                 &spr_read_dbat_h, &spr_write_dbatu_h,
644
                 0x00000000);
645
    spr_register(env, SPR_DBAT4L, "DBAT4L",
646
                 SPR_NOACCESS, SPR_NOACCESS,
647
                 &spr_read_dbat_h, &spr_write_dbatl_h,
648
                 0x00000000);
649
    spr_register(env, SPR_DBAT5U, "DBAT5U",
650
                 SPR_NOACCESS, SPR_NOACCESS,
651
                 &spr_read_dbat_h, &spr_write_dbatu_h,
652
                 0x00000000);
653
    spr_register(env, SPR_DBAT5L, "DBAT5L",
654
                 SPR_NOACCESS, SPR_NOACCESS,
655
                 &spr_read_dbat_h, &spr_write_dbatl_h,
656
                 0x00000000);
657
    spr_register(env, SPR_DBAT6U, "DBAT6U",
658
                 SPR_NOACCESS, SPR_NOACCESS,
659
                 &spr_read_dbat_h, &spr_write_dbatu_h,
660
                 0x00000000);
661
    spr_register(env, SPR_DBAT6L, "DBAT6L",
662
                 SPR_NOACCESS, SPR_NOACCESS,
663
                 &spr_read_dbat_h, &spr_write_dbatl_h,
664
                 0x00000000);
665
    spr_register(env, SPR_DBAT7U, "DBAT7U",
666
                 SPR_NOACCESS, SPR_NOACCESS,
667
                 &spr_read_dbat_h, &spr_write_dbatu_h,
668
                 0x00000000);
669
    spr_register(env, SPR_DBAT7L, "DBAT7L",
670
                 SPR_NOACCESS, SPR_NOACCESS,
671
                 &spr_read_dbat_h, &spr_write_dbatl_h,
672
                 0x00000000);
673
    env->nb_BATs += 4;
674
#endif
675
}
676

    
677
/* Generic PowerPC time base */
678
static void gen_tbl (CPUPPCState *env)
679
{
680
    spr_register(env, SPR_VTBL,  "TBL",
681
                 &spr_read_tbl, SPR_NOACCESS,
682
                 &spr_read_tbl, SPR_NOACCESS,
683
                 0x00000000);
684
    spr_register(env, SPR_TBL,   "TBL",
685
                 SPR_NOACCESS, SPR_NOACCESS,
686
                 SPR_NOACCESS, &spr_write_tbl,
687
                 0x00000000);
688
    spr_register(env, SPR_VTBU,  "TBU",
689
                 &spr_read_tbu, SPR_NOACCESS,
690
                 &spr_read_tbu, SPR_NOACCESS,
691
                 0x00000000);
692
    spr_register(env, SPR_TBU,   "TBU",
693
                 SPR_NOACCESS, SPR_NOACCESS,
694
                 SPR_NOACCESS, &spr_write_tbu,
695
                 0x00000000);
696
}
697

    
698
/* Softare table search registers */
699
static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
700
{
701
#if !defined(CONFIG_USER_ONLY)
702
    env->nb_tlb = nb_tlbs;
703
    env->nb_ways = nb_ways;
704
    env->id_tlbs = 1;
705
    spr_register(env, SPR_DMISS, "DMISS",
706
                 SPR_NOACCESS, SPR_NOACCESS,
707
                 &spr_read_generic, SPR_NOACCESS,
708
                 0x00000000);
709
    spr_register(env, SPR_DCMP, "DCMP",
710
                 SPR_NOACCESS, SPR_NOACCESS,
711
                 &spr_read_generic, SPR_NOACCESS,
712
                 0x00000000);
713
    spr_register(env, SPR_HASH1, "HASH1",
714
                 SPR_NOACCESS, SPR_NOACCESS,
715
                 &spr_read_generic, SPR_NOACCESS,
716
                 0x00000000);
717
    spr_register(env, SPR_HASH2, "HASH2",
718
                 SPR_NOACCESS, SPR_NOACCESS,
719
                 &spr_read_generic, SPR_NOACCESS,
720
                 0x00000000);
721
    spr_register(env, SPR_IMISS, "IMISS",
722
                 SPR_NOACCESS, SPR_NOACCESS,
723
                 &spr_read_generic, SPR_NOACCESS,
724
                 0x00000000);
725
    spr_register(env, SPR_ICMP, "ICMP",
726
                 SPR_NOACCESS, SPR_NOACCESS,
727
                 &spr_read_generic, SPR_NOACCESS,
728
                 0x00000000);
729
    spr_register(env, SPR_RPA, "RPA",
730
                 SPR_NOACCESS, SPR_NOACCESS,
731
                 &spr_read_generic, &spr_write_generic,
732
                 0x00000000);
733
#endif
734
}
735

    
736
/* SPR common to MPC755 and G2 */
737
static void gen_spr_G2_755 (CPUPPCState *env)
738
{
739
    /* SGPRs */
740
    spr_register(env, SPR_SPRG4, "SPRG4",
741
                 SPR_NOACCESS, SPR_NOACCESS,
742
                 &spr_read_generic, &spr_write_generic,
743
                 0x00000000);
744
    spr_register(env, SPR_SPRG5, "SPRG5",
745
                 SPR_NOACCESS, SPR_NOACCESS,
746
                 &spr_read_generic, &spr_write_generic,
747
                 0x00000000);
748
    spr_register(env, SPR_SPRG6, "SPRG6",
749
                 SPR_NOACCESS, SPR_NOACCESS,
750
                 &spr_read_generic, &spr_write_generic,
751
                 0x00000000);
752
    spr_register(env, SPR_SPRG7, "SPRG7",
753
                 SPR_NOACCESS, SPR_NOACCESS,
754
                 &spr_read_generic, &spr_write_generic,
755
                 0x00000000);
756
    /* External access control */
757
    /* XXX : not implemented */
758
    spr_register(env, SPR_EAR, "EAR",
759
                 SPR_NOACCESS, SPR_NOACCESS,
760
                 &spr_read_generic, &spr_write_generic,
761
                 0x00000000);
762
}
763

    
764
/* SPR common to all 7xx PowerPC implementations */
765
static void gen_spr_7xx (CPUPPCState *env)
766
{
767
    /* Breakpoints */
768
    /* XXX : not implemented */
769
    spr_register(env, SPR_DABR, "DABR",
770
                 SPR_NOACCESS, SPR_NOACCESS,
771
                 &spr_read_generic, &spr_write_generic,
772
                 0x00000000);
773
    /* XXX : not implemented */
774
    spr_register(env, SPR_IABR, "IABR",
775
                 SPR_NOACCESS, SPR_NOACCESS,
776
                 &spr_read_generic, &spr_write_generic,
777
                 0x00000000);
778
    /* Cache management */
779
    /* XXX : not implemented */
780
    spr_register(env, SPR_ICTC, "ICTC",
781
                 SPR_NOACCESS, SPR_NOACCESS,
782
                 &spr_read_generic, &spr_write_generic,
783
                 0x00000000);
784
    /* XXX : not implemented */
785
    spr_register(env, SPR_L2CR, "L2CR",
786
                 SPR_NOACCESS, SPR_NOACCESS,
787
                 &spr_read_generic, &spr_write_generic,
788
                 0x00000000);
789
    /* Performance monitors */
790
    /* XXX : not implemented */
791
    spr_register(env, SPR_MMCR0, "MMCR0",
792
                 SPR_NOACCESS, SPR_NOACCESS,
793
                 &spr_read_generic, &spr_write_generic,
794
                 0x00000000);
795
    /* XXX : not implemented */
796
    spr_register(env, SPR_MMCR1, "MMCR1",
797
                 SPR_NOACCESS, SPR_NOACCESS,
798
                 &spr_read_generic, &spr_write_generic,
799
                 0x00000000);
800
    /* XXX : not implemented */
801
    spr_register(env, SPR_PMC1, "PMC1",
802
                 SPR_NOACCESS, SPR_NOACCESS,
803
                 &spr_read_generic, &spr_write_generic,
804
                 0x00000000);
805
    /* XXX : not implemented */
806
    spr_register(env, SPR_PMC2, "PMC2",
807
                 SPR_NOACCESS, SPR_NOACCESS,
808
                 &spr_read_generic, &spr_write_generic,
809
                 0x00000000);
810
    /* XXX : not implemented */
811
    spr_register(env, SPR_PMC3, "PMC3",
812
                 SPR_NOACCESS, SPR_NOACCESS,
813
                 &spr_read_generic, &spr_write_generic,
814
                 0x00000000);
815
    /* XXX : not implemented */
816
    spr_register(env, SPR_PMC4, "PMC4",
817
                 SPR_NOACCESS, SPR_NOACCESS,
818
                 &spr_read_generic, &spr_write_generic,
819
                 0x00000000);
820
    /* XXX : not implemented */
821
    spr_register(env, SPR_SIAR, "SIAR",
822
                 SPR_NOACCESS, SPR_NOACCESS,
823
                 &spr_read_generic, SPR_NOACCESS,
824
                 0x00000000);
825
    /* XXX : not implemented */
826
    spr_register(env, SPR_UMMCR0, "UMMCR0",
827
                 &spr_read_ureg, SPR_NOACCESS,
828
                 &spr_read_ureg, SPR_NOACCESS,
829
                 0x00000000);
830
    /* XXX : not implemented */
831
    spr_register(env, SPR_UMMCR1, "UMMCR1",
832
                 &spr_read_ureg, SPR_NOACCESS,
833
                 &spr_read_ureg, SPR_NOACCESS,
834
                 0x00000000);
835
    /* XXX : not implemented */
836
    spr_register(env, SPR_UPMC1, "UPMC1",
837
                 &spr_read_ureg, SPR_NOACCESS,
838
                 &spr_read_ureg, SPR_NOACCESS,
839
                 0x00000000);
840
    /* XXX : not implemented */
841
    spr_register(env, SPR_UPMC2, "UPMC2",
842
                 &spr_read_ureg, SPR_NOACCESS,
843
                 &spr_read_ureg, SPR_NOACCESS,
844
                 0x00000000);
845
    /* XXX : not implemented */
846
    spr_register(env, SPR_UPMC3, "UPMC3",
847
                 &spr_read_ureg, SPR_NOACCESS,
848
                 &spr_read_ureg, SPR_NOACCESS,
849
                 0x00000000);
850
    /* XXX : not implemented */
851
    spr_register(env, SPR_UPMC4, "UPMC4",
852
                 &spr_read_ureg, SPR_NOACCESS,
853
                 &spr_read_ureg, SPR_NOACCESS,
854
                 0x00000000);
855
    /* XXX : not implemented */
856
    spr_register(env, SPR_USIAR, "USIAR",
857
                 &spr_read_ureg, SPR_NOACCESS,
858
                 &spr_read_ureg, SPR_NOACCESS,
859
                 0x00000000);
860
    /* External access control */
861
    /* XXX : not implemented */
862
    spr_register(env, SPR_EAR, "EAR",
863
                 SPR_NOACCESS, SPR_NOACCESS,
864
                 &spr_read_generic, &spr_write_generic,
865
                 0x00000000);
866
}
867

    
868
static void gen_spr_thrm (CPUPPCState *env)
869
{
870
    /* Thermal management */
871
    /* XXX : not implemented */
872
    spr_register(env, SPR_THRM1, "THRM1",
873
                 SPR_NOACCESS, SPR_NOACCESS,
874
                 &spr_read_generic, &spr_write_generic,
875
                 0x00000000);
876
    /* XXX : not implemented */
877
    spr_register(env, SPR_THRM2, "THRM2",
878
                 SPR_NOACCESS, SPR_NOACCESS,
879
                 &spr_read_generic, &spr_write_generic,
880
                 0x00000000);
881
    /* XXX : not implemented */
882
    spr_register(env, SPR_THRM3, "THRM3",
883
                 SPR_NOACCESS, SPR_NOACCESS,
884
                 &spr_read_generic, &spr_write_generic,
885
                 0x00000000);
886
}
887

    
888
/* SPR specific to PowerPC 604 implementation */
889
static void gen_spr_604 (CPUPPCState *env)
890
{
891
    /* Processor identification */
892
    spr_register(env, SPR_PIR, "PIR",
893
                 SPR_NOACCESS, SPR_NOACCESS,
894
                 &spr_read_generic, &spr_write_pir,
895
                 0x00000000);
896
    /* Breakpoints */
897
    /* XXX : not implemented */
898
    spr_register(env, SPR_IABR, "IABR",
899
                 SPR_NOACCESS, SPR_NOACCESS,
900
                 &spr_read_generic, &spr_write_generic,
901
                 0x00000000);
902
    /* XXX : not implemented */
903
    spr_register(env, SPR_DABR, "DABR",
904
                 SPR_NOACCESS, SPR_NOACCESS,
905
                 &spr_read_generic, &spr_write_generic,
906
                 0x00000000);
907
    /* Performance counters */
908
    /* XXX : not implemented */
909
    spr_register(env, SPR_MMCR0, "MMCR0",
910
                 SPR_NOACCESS, SPR_NOACCESS,
911
                 &spr_read_generic, &spr_write_generic,
912
                 0x00000000);
913
    /* XXX : not implemented */
914
    spr_register(env, SPR_MMCR1, "MMCR1",
915
                 SPR_NOACCESS, SPR_NOACCESS,
916
                 &spr_read_generic, &spr_write_generic,
917
                 0x00000000);
918
    /* XXX : not implemented */
919
    spr_register(env, SPR_PMC1, "PMC1",
920
                 SPR_NOACCESS, SPR_NOACCESS,
921
                 &spr_read_generic, &spr_write_generic,
922
                 0x00000000);
923
    /* XXX : not implemented */
924
    spr_register(env, SPR_PMC2, "PMC2",
925
                 SPR_NOACCESS, SPR_NOACCESS,
926
                 &spr_read_generic, &spr_write_generic,
927
                 0x00000000);
928
    /* XXX : not implemented */
929
    spr_register(env, SPR_PMC3, "PMC3",
930
                 SPR_NOACCESS, SPR_NOACCESS,
931
                 &spr_read_generic, &spr_write_generic,
932
                 0x00000000);
933
    /* XXX : not implemented */
934
    spr_register(env, SPR_PMC4, "PMC4",
935
                 SPR_NOACCESS, SPR_NOACCESS,
936
                 &spr_read_generic, &spr_write_generic,
937
                 0x00000000);
938
    /* XXX : not implemented */
939
    spr_register(env, SPR_SIAR, "SIAR",
940
                 SPR_NOACCESS, SPR_NOACCESS,
941
                 &spr_read_generic, SPR_NOACCESS,
942
                 0x00000000);
943
    /* XXX : not implemented */
944
    spr_register(env, SPR_SDA, "SDA",
945
                 SPR_NOACCESS, SPR_NOACCESS,
946
                 &spr_read_generic, SPR_NOACCESS,
947
                 0x00000000);
948
    /* External access control */
949
    /* XXX : not implemented */
950
    spr_register(env, SPR_EAR, "EAR",
951
                 SPR_NOACCESS, SPR_NOACCESS,
952
                 &spr_read_generic, &spr_write_generic,
953
                 0x00000000);
954
}
955

    
956
/* SPR specific to PowerPC 603 implementation */
957
static void gen_spr_603 (CPUPPCState *env)
958
{
959
    /* External access control */
960
    /* XXX : not implemented */
961
    spr_register(env, SPR_EAR, "EAR",
962
                 SPR_NOACCESS, SPR_NOACCESS,
963
                 &spr_read_generic, &spr_write_generic,
964
                 0x00000000);
965
}
966

    
967
/* SPR specific to PowerPC G2 implementation */
968
static void gen_spr_G2 (CPUPPCState *env)
969
{
970
    /* Memory base address */
971
    /* MBAR */
972
    /* XXX : not implemented */
973
    spr_register(env, SPR_MBAR, "MBAR",
974
                 SPR_NOACCESS, SPR_NOACCESS,
975
                 &spr_read_generic, &spr_write_generic,
976
                 0x00000000);
977
    /* System version register */
978
    /* SVR */
979
    /* XXX : TODO: initialize it to an appropriate value */
980
    spr_register(env, SPR_SVR, "SVR",
981
                 SPR_NOACCESS, SPR_NOACCESS,
982
                 &spr_read_generic, SPR_NOACCESS,
983
                 0x00000000);
984
    /* Exception processing */
985
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
986
                 SPR_NOACCESS, SPR_NOACCESS,
987
                 &spr_read_generic, &spr_write_generic,
988
                 0x00000000);
989
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
990
                 SPR_NOACCESS, SPR_NOACCESS,
991
                 &spr_read_generic, &spr_write_generic,
992
                 0x00000000);
993
    /* Breakpoints */
994
    /* XXX : not implemented */
995
    spr_register(env, SPR_DABR, "DABR",
996
                 SPR_NOACCESS, SPR_NOACCESS,
997
                 &spr_read_generic, &spr_write_generic,
998
                 0x00000000);
999
    /* XXX : not implemented */
1000
    spr_register(env, SPR_DABR2, "DABR2",
1001
                 SPR_NOACCESS, SPR_NOACCESS,
1002
                 &spr_read_generic, &spr_write_generic,
1003
                 0x00000000);
1004
    /* XXX : not implemented */
1005
    spr_register(env, SPR_IABR, "IABR",
1006
                 SPR_NOACCESS, SPR_NOACCESS,
1007
                 &spr_read_generic, &spr_write_generic,
1008
                 0x00000000);
1009
    /* XXX : not implemented */
1010
    spr_register(env, SPR_IABR2, "IABR2",
1011
                 SPR_NOACCESS, SPR_NOACCESS,
1012
                 &spr_read_generic, &spr_write_generic,
1013
                 0x00000000);
1014
    /* XXX : not implemented */
1015
    spr_register(env, SPR_IBCR, "IBCR",
1016
                 SPR_NOACCESS, SPR_NOACCESS,
1017
                 &spr_read_generic, &spr_write_generic,
1018
                 0x00000000);
1019
    /* XXX : not implemented */
1020
    spr_register(env, SPR_DBCR, "DBCR",
1021
                 SPR_NOACCESS, SPR_NOACCESS,
1022
                 &spr_read_generic, &spr_write_generic,
1023
                 0x00000000);
1024
}
1025

    
1026
/* SPR specific to PowerPC 602 implementation */
1027
static void gen_spr_602 (CPUPPCState *env)
1028
{
1029
    /* ESA registers */
1030
    /* XXX : not implemented */
1031
    spr_register(env, SPR_SER, "SER",
1032
                 SPR_NOACCESS, SPR_NOACCESS,
1033
                 &spr_read_generic, &spr_write_generic,
1034
                 0x00000000);
1035
    /* XXX : not implemented */
1036
    spr_register(env, SPR_SEBR, "SEBR",
1037
                 SPR_NOACCESS, SPR_NOACCESS,
1038
                 &spr_read_generic, &spr_write_generic,
1039
                 0x00000000);
1040
    /* XXX : not implemented */
1041
    spr_register(env, SPR_ESASRR, "ESASRR",
1042
                 SPR_NOACCESS, SPR_NOACCESS,
1043
                 &spr_read_generic, &spr_write_generic,
1044
                 0x00000000);
1045
    /* Floating point status */
1046
    /* XXX : not implemented */
1047
    spr_register(env, SPR_SP, "SP",
1048
                 SPR_NOACCESS, SPR_NOACCESS,
1049
                 &spr_read_generic, &spr_write_generic,
1050
                 0x00000000);
1051
    /* XXX : not implemented */
1052
    spr_register(env, SPR_LT, "LT",
1053
                 SPR_NOACCESS, SPR_NOACCESS,
1054
                 &spr_read_generic, &spr_write_generic,
1055
                 0x00000000);
1056
    /* Watchdog timer */
1057
    /* XXX : not implemented */
1058
    spr_register(env, SPR_TCR, "TCR",
1059
                 SPR_NOACCESS, SPR_NOACCESS,
1060
                 &spr_read_generic, &spr_write_generic,
1061
                 0x00000000);
1062
    /* Interrupt base */
1063
    spr_register(env, SPR_IBR, "IBR",
1064
                 SPR_NOACCESS, SPR_NOACCESS,
1065
                 &spr_read_generic, &spr_write_generic,
1066
                 0x00000000);
1067
    /* XXX : not implemented */
1068
    spr_register(env, SPR_IABR, "IABR",
1069
                 SPR_NOACCESS, SPR_NOACCESS,
1070
                 &spr_read_generic, &spr_write_generic,
1071
                 0x00000000);
1072
}
1073

    
1074
/* SPR specific to PowerPC 601 implementation */
1075
static void gen_spr_601 (CPUPPCState *env)
1076
{
1077
    /* Multiplication/division register */
1078
    /* MQ */
1079
    spr_register(env, SPR_MQ, "MQ",
1080
                 &spr_read_generic, &spr_write_generic,
1081
                 &spr_read_generic, &spr_write_generic,
1082
                 0x00000000);
1083
    /* RTC registers */
1084
    spr_register(env, SPR_601_RTCU, "RTCU",
1085
                 SPR_NOACCESS, SPR_NOACCESS,
1086
                 SPR_NOACCESS, &spr_write_601_rtcu,
1087
                 0x00000000);
1088
    spr_register(env, SPR_601_VRTCU, "RTCU",
1089
                 &spr_read_601_rtcu, SPR_NOACCESS,
1090
                 &spr_read_601_rtcu, SPR_NOACCESS,
1091
                 0x00000000);
1092
    spr_register(env, SPR_601_RTCL, "RTCL",
1093
                 SPR_NOACCESS, SPR_NOACCESS,
1094
                 SPR_NOACCESS, &spr_write_601_rtcl,
1095
                 0x00000000);
1096
    spr_register(env, SPR_601_VRTCL, "RTCL",
1097
                 &spr_read_601_rtcl, SPR_NOACCESS,
1098
                 &spr_read_601_rtcl, SPR_NOACCESS,
1099
                 0x00000000);
1100
    /* Timer */
1101
#if 0 /* ? */
1102
    spr_register(env, SPR_601_UDECR, "UDECR",
1103
                 &spr_read_decr, SPR_NOACCESS,
1104
                 &spr_read_decr, SPR_NOACCESS,
1105
                 0x00000000);
1106
#endif
1107
    /* External access control */
1108
    /* XXX : not implemented */
1109
    spr_register(env, SPR_EAR, "EAR",
1110
                 SPR_NOACCESS, SPR_NOACCESS,
1111
                 &spr_read_generic, &spr_write_generic,
1112
                 0x00000000);
1113
    /* Memory management */
1114
#if !defined(CONFIG_USER_ONLY)
1115
    spr_register(env, SPR_IBAT0U, "IBAT0U",
1116
                 SPR_NOACCESS, SPR_NOACCESS,
1117
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1118
                 0x00000000);
1119
    spr_register(env, SPR_IBAT0L, "IBAT0L",
1120
                 SPR_NOACCESS, SPR_NOACCESS,
1121
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1122
                 0x00000000);
1123
    spr_register(env, SPR_IBAT1U, "IBAT1U",
1124
                 SPR_NOACCESS, SPR_NOACCESS,
1125
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1126
                 0x00000000);
1127
    spr_register(env, SPR_IBAT1L, "IBAT1L",
1128
                 SPR_NOACCESS, SPR_NOACCESS,
1129
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1130
                 0x00000000);
1131
    spr_register(env, SPR_IBAT2U, "IBAT2U",
1132
                 SPR_NOACCESS, SPR_NOACCESS,
1133
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1134
                 0x00000000);
1135
    spr_register(env, SPR_IBAT2L, "IBAT2L",
1136
                 SPR_NOACCESS, SPR_NOACCESS,
1137
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1138
                 0x00000000);
1139
    spr_register(env, SPR_IBAT3U, "IBAT3U",
1140
                 SPR_NOACCESS, SPR_NOACCESS,
1141
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1142
                 0x00000000);
1143
    spr_register(env, SPR_IBAT3L, "IBAT3L",
1144
                 SPR_NOACCESS, SPR_NOACCESS,
1145
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1146
                 0x00000000);
1147
    env->nb_BATs = 4;
1148
#endif
1149
}
1150

    
1151
static void gen_spr_74xx (CPUPPCState *env)
1152
{
1153
    /* Processor identification */
1154
    spr_register(env, SPR_PIR, "PIR",
1155
                 SPR_NOACCESS, SPR_NOACCESS,
1156
                 &spr_read_generic, &spr_write_pir,
1157
                 0x00000000);
1158
    /* XXX : not implemented */
1159
    spr_register(env, SPR_MMCR2, "MMCR2",
1160
                 SPR_NOACCESS, SPR_NOACCESS,
1161
                 &spr_read_generic, &spr_write_generic,
1162
                 0x00000000);
1163
    /* XXX : not implemented */
1164
    spr_register(env, SPR_UMMCR2, "UMMCR2",
1165
                 &spr_read_ureg, SPR_NOACCESS,
1166
                 &spr_read_ureg, SPR_NOACCESS,
1167
                 0x00000000);
1168
    /* XXX: not implemented */
1169
    spr_register(env, SPR_BAMR, "BAMR",
1170
                 SPR_NOACCESS, SPR_NOACCESS,
1171
                 &spr_read_generic, &spr_write_generic,
1172
                 0x00000000);
1173
    /* XXX : not implemented */
1174
    spr_register(env, SPR_UBAMR, "UBAMR",
1175
                 &spr_read_ureg, SPR_NOACCESS,
1176
                 &spr_read_ureg, SPR_NOACCESS,
1177
                 0x00000000);
1178
    /* XXX : not implemented */
1179
    spr_register(env, SPR_MSSCR0, "MSSCR0",
1180
                 SPR_NOACCESS, SPR_NOACCESS,
1181
                 &spr_read_generic, &spr_write_generic,
1182
                 0x00000000);
1183
    /* Hardware implementation registers */
1184
    /* XXX : not implemented */
1185
    spr_register(env, SPR_HID0, "HID0",
1186
                 SPR_NOACCESS, SPR_NOACCESS,
1187
                 &spr_read_generic, &spr_write_generic,
1188
                 0x00000000);
1189
    /* XXX : not implemented */
1190
    spr_register(env, SPR_HID1, "HID1",
1191
                 SPR_NOACCESS, SPR_NOACCESS,
1192
                 &spr_read_generic, &spr_write_generic,
1193
                 0x00000000);
1194
    /* Altivec */
1195
    spr_register(env, SPR_VRSAVE, "VRSAVE",
1196
                 &spr_read_generic, &spr_write_generic,
1197
                 &spr_read_generic, &spr_write_generic,
1198
                 0x00000000);
1199
}
1200

    
1201
static void gen_l3_ctrl (CPUPPCState *env)
1202
{
1203
    /* L3CR */
1204
    /* XXX : not implemented */
1205
    spr_register(env, SPR_L3CR, "L3CR",
1206
                 SPR_NOACCESS, SPR_NOACCESS,
1207
                 &spr_read_generic, &spr_write_generic,
1208
                 0x00000000);
1209
    /* L3ITCR0 */
1210
    /* XXX : not implemented */
1211
    spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1212
                 SPR_NOACCESS, SPR_NOACCESS,
1213
                 &spr_read_generic, &spr_write_generic,
1214
                 0x00000000);
1215
    /* L3ITCR1 */
1216
    /* XXX : not implemented */
1217
    spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1218
                 SPR_NOACCESS, SPR_NOACCESS,
1219
                 &spr_read_generic, &spr_write_generic,
1220
                 0x00000000);
1221
    /* L3ITCR2 */
1222
    /* XXX : not implemented */
1223
    spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1224
                 SPR_NOACCESS, SPR_NOACCESS,
1225
                 &spr_read_generic, &spr_write_generic,
1226
                 0x00000000);
1227
    /* L3ITCR3 */
1228
    /* XXX : not implemented */
1229
    spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1230
                 SPR_NOACCESS, SPR_NOACCESS,
1231
                 &spr_read_generic, &spr_write_generic,
1232
                 0x00000000);
1233
    /* L3OHCR */
1234
    /* XXX : not implemented */
1235
    spr_register(env, SPR_L3OHCR, "L3OHCR",
1236
                 SPR_NOACCESS, SPR_NOACCESS,
1237
                 &spr_read_generic, &spr_write_generic,
1238
                 0x00000000);
1239
    /* L3PM */
1240
    /* XXX : not implemented */
1241
    spr_register(env, SPR_L3PM, "L3PM",
1242
                 SPR_NOACCESS, SPR_NOACCESS,
1243
                 &spr_read_generic, &spr_write_generic,
1244
                 0x00000000);
1245
}
1246

    
1247
static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1248
{
1249
#if !defined(CONFIG_USER_ONLY)
1250
    env->nb_tlb = nb_tlbs;
1251
    env->nb_ways = nb_ways;
1252
    env->id_tlbs = 1;
1253
    /* XXX : not implemented */
1254
    spr_register(env, SPR_PTEHI, "PTEHI",
1255
                 SPR_NOACCESS, SPR_NOACCESS,
1256
                 &spr_read_generic, &spr_write_generic,
1257
                 0x00000000);
1258
    /* XXX : not implemented */
1259
    spr_register(env, SPR_PTELO, "PTELO",
1260
                 SPR_NOACCESS, SPR_NOACCESS,
1261
                 &spr_read_generic, &spr_write_generic,
1262
                 0x00000000);
1263
    /* XXX : not implemented */
1264
    spr_register(env, SPR_TLBMISS, "TLBMISS",
1265
                 SPR_NOACCESS, SPR_NOACCESS,
1266
                 &spr_read_generic, &spr_write_generic,
1267
                 0x00000000);
1268
#endif
1269
}
1270

    
1271
/* PowerPC BookE SPR */
1272
static void gen_spr_BookE (CPUPPCState *env)
1273
{
1274
    /* Processor identification */
1275
    spr_register(env, SPR_BOOKE_PIR, "PIR",
1276
                 SPR_NOACCESS, SPR_NOACCESS,
1277
                 &spr_read_generic, &spr_write_pir,
1278
                 0x00000000);
1279
    /* Interrupt processing */
1280
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1281
                 SPR_NOACCESS, SPR_NOACCESS,
1282
                 &spr_read_generic, &spr_write_generic,
1283
                 0x00000000);
1284
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1285
                 SPR_NOACCESS, SPR_NOACCESS,
1286
                 &spr_read_generic, &spr_write_generic,
1287
                 0x00000000);
1288
#if 0
1289
    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1290
                 SPR_NOACCESS, SPR_NOACCESS,
1291
                 &spr_read_generic, &spr_write_generic,
1292
                 0x00000000);
1293
    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1294
                 SPR_NOACCESS, SPR_NOACCESS,
1295
                 &spr_read_generic, &spr_write_generic,
1296
                 0x00000000);
1297
#endif
1298
    /* Debug */
1299
    /* XXX : not implemented */
1300
    spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1301
                 SPR_NOACCESS, SPR_NOACCESS,
1302
                 &spr_read_generic, &spr_write_generic,
1303
                 0x00000000);
1304
    /* XXX : not implemented */
1305
    spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1306
                 SPR_NOACCESS, SPR_NOACCESS,
1307
                 &spr_read_generic, &spr_write_generic,
1308
                 0x00000000);
1309
    /* XXX : not implemented */
1310
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1311
                 SPR_NOACCESS, SPR_NOACCESS,
1312
                 &spr_read_generic, &spr_write_generic,
1313
                 0x00000000);
1314
    /* XXX : not implemented */
1315
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1316
                 SPR_NOACCESS, SPR_NOACCESS,
1317
                 &spr_read_generic, &spr_write_generic,
1318
                 0x00000000);
1319
    /* XXX : not implemented */
1320
    spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1321
                 SPR_NOACCESS, SPR_NOACCESS,
1322
                 &spr_read_generic, &spr_write_generic,
1323
                 0x00000000);
1324
    /* XXX : not implemented */
1325
    spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1326
                 SPR_NOACCESS, SPR_NOACCESS,
1327
                 &spr_read_generic, &spr_write_generic,
1328
                 0x00000000);
1329
    /* XXX : not implemented */
1330
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1331
                 SPR_NOACCESS, SPR_NOACCESS,
1332
                 &spr_read_generic, &spr_write_generic,
1333
                 0x00000000);
1334
    /* XXX : not implemented */
1335
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1336
                 SPR_NOACCESS, SPR_NOACCESS,
1337
                 &spr_read_generic, &spr_write_generic,
1338
                 0x00000000);
1339
    /* XXX : not implemented */
1340
    spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1341
                 SPR_NOACCESS, SPR_NOACCESS,
1342
                 &spr_read_generic, &spr_write_generic,
1343
                 0x00000000);
1344
    /* XXX : not implemented */
1345
    spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1346
                 SPR_NOACCESS, SPR_NOACCESS,
1347
                 &spr_read_generic, &spr_write_generic,
1348
                 0x00000000);
1349
    /* XXX : not implemented */
1350
    spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1351
                 SPR_NOACCESS, SPR_NOACCESS,
1352
                 &spr_read_generic, &spr_write_generic,
1353
                 0x00000000);
1354
    /* XXX : not implemented */
1355
    spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1356
                 SPR_NOACCESS, SPR_NOACCESS,
1357
                 &spr_read_generic, &spr_write_clear,
1358
                 0x00000000);
1359
    spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1360
                 SPR_NOACCESS, SPR_NOACCESS,
1361
                 &spr_read_generic, &spr_write_generic,
1362
                 0x00000000);
1363
    spr_register(env, SPR_BOOKE_ESR, "ESR",
1364
                 SPR_NOACCESS, SPR_NOACCESS,
1365
                 &spr_read_generic, &spr_write_generic,
1366
                 0x00000000);
1367
    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1368
                 SPR_NOACCESS, SPR_NOACCESS,
1369
                 &spr_read_generic, &spr_write_excp_prefix,
1370
                 0x00000000);
1371
    /* Exception vectors */
1372
    spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1373
                 SPR_NOACCESS, SPR_NOACCESS,
1374
                 &spr_read_generic, &spr_write_excp_vector,
1375
                 0x00000000);
1376
    spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1377
                 SPR_NOACCESS, SPR_NOACCESS,
1378
                 &spr_read_generic, &spr_write_excp_vector,
1379
                 0x00000000);
1380
    spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1381
                 SPR_NOACCESS, SPR_NOACCESS,
1382
                 &spr_read_generic, &spr_write_excp_vector,
1383
                 0x00000000);
1384
    spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1385
                 SPR_NOACCESS, SPR_NOACCESS,
1386
                 &spr_read_generic, &spr_write_excp_vector,
1387
                 0x00000000);
1388
    spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1389
                 SPR_NOACCESS, SPR_NOACCESS,
1390
                 &spr_read_generic, &spr_write_excp_vector,
1391
                 0x00000000);
1392
    spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1393
                 SPR_NOACCESS, SPR_NOACCESS,
1394
                 &spr_read_generic, &spr_write_excp_vector,
1395
                 0x00000000);
1396
    spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1397
                 SPR_NOACCESS, SPR_NOACCESS,
1398
                 &spr_read_generic, &spr_write_excp_vector,
1399
                 0x00000000);
1400
    spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1401
                 SPR_NOACCESS, SPR_NOACCESS,
1402
                 &spr_read_generic, &spr_write_excp_vector,
1403
                 0x00000000);
1404
    spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1405
                 SPR_NOACCESS, SPR_NOACCESS,
1406
                 &spr_read_generic, &spr_write_excp_vector,
1407
                 0x00000000);
1408
    spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1409
                 SPR_NOACCESS, SPR_NOACCESS,
1410
                 &spr_read_generic, &spr_write_excp_vector,
1411
                 0x00000000);
1412
    spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1413
                 SPR_NOACCESS, SPR_NOACCESS,
1414
                 &spr_read_generic, &spr_write_excp_vector,
1415
                 0x00000000);
1416
    spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1417
                 SPR_NOACCESS, SPR_NOACCESS,
1418
                 &spr_read_generic, &spr_write_excp_vector,
1419
                 0x00000000);
1420
    spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1421
                 SPR_NOACCESS, SPR_NOACCESS,
1422
                 &spr_read_generic, &spr_write_excp_vector,
1423
                 0x00000000);
1424
    spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1425
                 SPR_NOACCESS, SPR_NOACCESS,
1426
                 &spr_read_generic, &spr_write_excp_vector,
1427
                 0x00000000);
1428
    spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1429
                 SPR_NOACCESS, SPR_NOACCESS,
1430
                 &spr_read_generic, &spr_write_excp_vector,
1431
                 0x00000000);
1432
    spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1433
                 SPR_NOACCESS, SPR_NOACCESS,
1434
                 &spr_read_generic, &spr_write_excp_vector,
1435
                 0x00000000);
1436
#if 0
1437
    spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1438
                 SPR_NOACCESS, SPR_NOACCESS,
1439
                 &spr_read_generic, &spr_write_excp_vector,
1440
                 0x00000000);
1441
    spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1442
                 SPR_NOACCESS, SPR_NOACCESS,
1443
                 &spr_read_generic, &spr_write_excp_vector,
1444
                 0x00000000);
1445
    spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1446
                 SPR_NOACCESS, SPR_NOACCESS,
1447
                 &spr_read_generic, &spr_write_excp_vector,
1448
                 0x00000000);
1449
    spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1450
                 SPR_NOACCESS, SPR_NOACCESS,
1451
                 &spr_read_generic, &spr_write_excp_vector,
1452
                 0x00000000);
1453
    spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1454
                 SPR_NOACCESS, SPR_NOACCESS,
1455
                 &spr_read_generic, &spr_write_excp_vector,
1456
                 0x00000000);
1457
    spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1458
                 SPR_NOACCESS, SPR_NOACCESS,
1459
                 &spr_read_generic, &spr_write_excp_vector,
1460
                 0x00000000);
1461
#endif
1462
    spr_register(env, SPR_BOOKE_PID, "PID",
1463
                 SPR_NOACCESS, SPR_NOACCESS,
1464
                 &spr_read_generic, &spr_write_generic,
1465
                 0x00000000);
1466
    spr_register(env, SPR_BOOKE_TCR, "TCR",
1467
                 SPR_NOACCESS, SPR_NOACCESS,
1468
                 &spr_read_generic, &spr_write_booke_tcr,
1469
                 0x00000000);
1470
    spr_register(env, SPR_BOOKE_TSR, "TSR",
1471
                 SPR_NOACCESS, SPR_NOACCESS,
1472
                 &spr_read_generic, &spr_write_booke_tsr,
1473
                 0x00000000);
1474
    /* Timer */
1475
    spr_register(env, SPR_DECR, "DECR",
1476
                 SPR_NOACCESS, SPR_NOACCESS,
1477
                 &spr_read_decr, &spr_write_decr,
1478
                 0x00000000);
1479
    spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1480
                 SPR_NOACCESS, SPR_NOACCESS,
1481
                 SPR_NOACCESS, &spr_write_generic,
1482
                 0x00000000);
1483
    /* SPRGs */
1484
    spr_register(env, SPR_USPRG0, "USPRG0",
1485
                 &spr_read_generic, &spr_write_generic,
1486
                 &spr_read_generic, &spr_write_generic,
1487
                 0x00000000);
1488
    spr_register(env, SPR_SPRG4, "SPRG4",
1489
                 SPR_NOACCESS, SPR_NOACCESS,
1490
                 &spr_read_generic, &spr_write_generic,
1491
                 0x00000000);
1492
    spr_register(env, SPR_USPRG4, "USPRG4",
1493
                 &spr_read_ureg, SPR_NOACCESS,
1494
                 &spr_read_ureg, SPR_NOACCESS,
1495
                 0x00000000);
1496
    spr_register(env, SPR_SPRG5, "SPRG5",
1497
                 SPR_NOACCESS, SPR_NOACCESS,
1498
                 &spr_read_generic, &spr_write_generic,
1499
                 0x00000000);
1500
    spr_register(env, SPR_USPRG5, "USPRG5",
1501
                 &spr_read_ureg, SPR_NOACCESS,
1502
                 &spr_read_ureg, SPR_NOACCESS,
1503
                 0x00000000);
1504
    spr_register(env, SPR_SPRG6, "SPRG6",
1505
                 SPR_NOACCESS, SPR_NOACCESS,
1506
                 &spr_read_generic, &spr_write_generic,
1507
                 0x00000000);
1508
    spr_register(env, SPR_USPRG6, "USPRG6",
1509
                 &spr_read_ureg, SPR_NOACCESS,
1510
                 &spr_read_ureg, SPR_NOACCESS,
1511
                 0x00000000);
1512
    spr_register(env, SPR_SPRG7, "SPRG7",
1513
                 SPR_NOACCESS, SPR_NOACCESS,
1514
                 &spr_read_generic, &spr_write_generic,
1515
                 0x00000000);
1516
    spr_register(env, SPR_USPRG7, "USPRG7",
1517
                 &spr_read_ureg, SPR_NOACCESS,
1518
                 &spr_read_ureg, SPR_NOACCESS,
1519
                 0x00000000);
1520
}
1521

    
1522
/* FSL storage control registers */
1523
static void gen_spr_BookE_FSL (CPUPPCState *env)
1524
{
1525
#if !defined(CONFIG_USER_ONLY)
1526
    /* TLB assist registers */
1527
    /* XXX : not implemented */
1528
    spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1529
                 SPR_NOACCESS, SPR_NOACCESS,
1530
                 &spr_read_generic, &spr_write_generic,
1531
                 0x00000000);
1532
    /* XXX : not implemented */
1533
    spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1534
                 SPR_NOACCESS, SPR_NOACCESS,
1535
                 &spr_read_generic, &spr_write_generic,
1536
                 0x00000000);
1537
    /* XXX : not implemented */
1538
    spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1539
                 SPR_NOACCESS, SPR_NOACCESS,
1540
                 &spr_read_generic, &spr_write_generic,
1541
                 0x00000000);
1542
    /* XXX : not implemented */
1543
    spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1544
                 SPR_NOACCESS, SPR_NOACCESS,
1545
                 &spr_read_generic, &spr_write_generic,
1546
                 0x00000000);
1547
    /* XXX : not implemented */
1548
    spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1549
                 SPR_NOACCESS, SPR_NOACCESS,
1550
                 &spr_read_generic, &spr_write_generic,
1551
                 0x00000000);
1552
    /* XXX : not implemented */
1553
    spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1554
                 SPR_NOACCESS, SPR_NOACCESS,
1555
                 &spr_read_generic, &spr_write_generic,
1556
                 0x00000000);
1557
    /* XXX : not implemented */
1558
    spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1559
                 SPR_NOACCESS, SPR_NOACCESS,
1560
                 &spr_read_generic, &spr_write_generic,
1561
                 0x00000000);
1562
    if (env->nb_pids > 1) {
1563
        /* XXX : not implemented */
1564
        spr_register(env, SPR_BOOKE_PID1, "PID1",
1565
                     SPR_NOACCESS, SPR_NOACCESS,
1566
                     &spr_read_generic, &spr_write_generic,
1567
                     0x00000000);
1568
    }
1569
    if (env->nb_pids > 2) {
1570
        /* XXX : not implemented */
1571
        spr_register(env, SPR_BOOKE_PID2, "PID2",
1572
                     SPR_NOACCESS, SPR_NOACCESS,
1573
                     &spr_read_generic, &spr_write_generic,
1574
                     0x00000000);
1575
    }
1576
    /* XXX : not implemented */
1577
    spr_register(env, SPR_MMUCFG, "MMUCFG",
1578
                 SPR_NOACCESS, SPR_NOACCESS,
1579
                 &spr_read_generic, SPR_NOACCESS,
1580
                 0x00000000); /* TOFIX */
1581
    /* XXX : not implemented */
1582
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1583
                 SPR_NOACCESS, SPR_NOACCESS,
1584
                 &spr_read_generic, &spr_write_generic,
1585
                 0x00000000); /* TOFIX */
1586
    switch (env->nb_ways) {
1587
    case 4:
1588
        /* XXX : not implemented */
1589
        spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1590
                     SPR_NOACCESS, SPR_NOACCESS,
1591
                     &spr_read_generic, SPR_NOACCESS,
1592
                     0x00000000); /* TOFIX */
1593
        /* Fallthru */
1594
    case 3:
1595
        /* XXX : not implemented */
1596
        spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1597
                     SPR_NOACCESS, SPR_NOACCESS,
1598
                     &spr_read_generic, SPR_NOACCESS,
1599
                     0x00000000); /* TOFIX */
1600
        /* Fallthru */
1601
    case 2:
1602
        /* XXX : not implemented */
1603
        spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1604
                     SPR_NOACCESS, SPR_NOACCESS,
1605
                     &spr_read_generic, SPR_NOACCESS,
1606
                     0x00000000); /* TOFIX */
1607
        /* Fallthru */
1608
    case 1:
1609
        /* XXX : not implemented */
1610
        spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1611
                     SPR_NOACCESS, SPR_NOACCESS,
1612
                     &spr_read_generic, SPR_NOACCESS,
1613
                     0x00000000); /* TOFIX */
1614
        /* Fallthru */
1615
    case 0:
1616
    default:
1617
        break;
1618
    }
1619
#endif
1620
}
1621

    
1622
/* SPR specific to PowerPC 440 implementation */
1623
static void gen_spr_440 (CPUPPCState *env)
1624
{
1625
    /* Cache control */
1626
    /* XXX : not implemented */
1627
    spr_register(env, SPR_440_DNV0, "DNV0",
1628
                 SPR_NOACCESS, SPR_NOACCESS,
1629
                 &spr_read_generic, &spr_write_generic,
1630
                 0x00000000);
1631
    /* XXX : not implemented */
1632
    spr_register(env, SPR_440_DNV1, "DNV1",
1633
                 SPR_NOACCESS, SPR_NOACCESS,
1634
                 &spr_read_generic, &spr_write_generic,
1635
                 0x00000000);
1636
    /* XXX : not implemented */
1637
    spr_register(env, SPR_440_DNV2, "DNV2",
1638
                 SPR_NOACCESS, SPR_NOACCESS,
1639
                 &spr_read_generic, &spr_write_generic,
1640
                 0x00000000);
1641
    /* XXX : not implemented */
1642
    spr_register(env, SPR_440_DNV3, "DNV3",
1643
                 SPR_NOACCESS, SPR_NOACCESS,
1644
                 &spr_read_generic, &spr_write_generic,
1645
                 0x00000000);
1646
    /* XXX : not implemented */
1647
    spr_register(env, SPR_440_DTV0, "DTV0",
1648
                 SPR_NOACCESS, SPR_NOACCESS,
1649
                 &spr_read_generic, &spr_write_generic,
1650
                 0x00000000);
1651
    /* XXX : not implemented */
1652
    spr_register(env, SPR_440_DTV1, "DTV1",
1653
                 SPR_NOACCESS, SPR_NOACCESS,
1654
                 &spr_read_generic, &spr_write_generic,
1655
                 0x00000000);
1656
    /* XXX : not implemented */
1657
    spr_register(env, SPR_440_DTV2, "DTV2",
1658
                 SPR_NOACCESS, SPR_NOACCESS,
1659
                 &spr_read_generic, &spr_write_generic,
1660
                 0x00000000);
1661
    /* XXX : not implemented */
1662
    spr_register(env, SPR_440_DTV3, "DTV3",
1663
                 SPR_NOACCESS, SPR_NOACCESS,
1664
                 &spr_read_generic, &spr_write_generic,
1665
                 0x00000000);
1666
    /* XXX : not implemented */
1667
    spr_register(env, SPR_440_DVLIM, "DVLIM",
1668
                 SPR_NOACCESS, SPR_NOACCESS,
1669
                 &spr_read_generic, &spr_write_generic,
1670
                 0x00000000);
1671
    /* XXX : not implemented */
1672
    spr_register(env, SPR_440_INV0, "INV0",
1673
                 SPR_NOACCESS, SPR_NOACCESS,
1674
                 &spr_read_generic, &spr_write_generic,
1675
                 0x00000000);
1676
    /* XXX : not implemented */
1677
    spr_register(env, SPR_440_INV1, "INV1",
1678
                 SPR_NOACCESS, SPR_NOACCESS,
1679
                 &spr_read_generic, &spr_write_generic,
1680
                 0x00000000);
1681
    /* XXX : not implemented */
1682
    spr_register(env, SPR_440_INV2, "INV2",
1683
                 SPR_NOACCESS, SPR_NOACCESS,
1684
                 &spr_read_generic, &spr_write_generic,
1685
                 0x00000000);
1686
    /* XXX : not implemented */
1687
    spr_register(env, SPR_440_INV3, "INV3",
1688
                 SPR_NOACCESS, SPR_NOACCESS,
1689
                 &spr_read_generic, &spr_write_generic,
1690
                 0x00000000);
1691
    /* XXX : not implemented */
1692
    spr_register(env, SPR_440_ITV0, "ITV0",
1693
                 SPR_NOACCESS, SPR_NOACCESS,
1694
                 &spr_read_generic, &spr_write_generic,
1695
                 0x00000000);
1696
    /* XXX : not implemented */
1697
    spr_register(env, SPR_440_ITV1, "ITV1",
1698
                 SPR_NOACCESS, SPR_NOACCESS,
1699
                 &spr_read_generic, &spr_write_generic,
1700
                 0x00000000);
1701
    /* XXX : not implemented */
1702
    spr_register(env, SPR_440_ITV2, "ITV2",
1703
                 SPR_NOACCESS, SPR_NOACCESS,
1704
                 &spr_read_generic, &spr_write_generic,
1705
                 0x00000000);
1706
    /* XXX : not implemented */
1707
    spr_register(env, SPR_440_ITV3, "ITV3",
1708
                 SPR_NOACCESS, SPR_NOACCESS,
1709
                 &spr_read_generic, &spr_write_generic,
1710
                 0x00000000);
1711
    /* XXX : not implemented */
1712
    spr_register(env, SPR_440_IVLIM, "IVLIM",
1713
                 SPR_NOACCESS, SPR_NOACCESS,
1714
                 &spr_read_generic, &spr_write_generic,
1715
                 0x00000000);
1716
    /* Cache debug */
1717
    /* XXX : not implemented */
1718
    spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1719
                 SPR_NOACCESS, SPR_NOACCESS,
1720
                 &spr_read_generic, SPR_NOACCESS,
1721
                 0x00000000);
1722
    /* XXX : not implemented */
1723
    spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1724
                 SPR_NOACCESS, SPR_NOACCESS,
1725
                 &spr_read_generic, SPR_NOACCESS,
1726
                 0x00000000);
1727
    /* XXX : not implemented */
1728
    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1729
                 SPR_NOACCESS, SPR_NOACCESS,
1730
                 &spr_read_generic, SPR_NOACCESS,
1731
                 0x00000000);
1732
    /* XXX : not implemented */
1733
    spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1734
                 SPR_NOACCESS, SPR_NOACCESS,
1735
                 &spr_read_generic, SPR_NOACCESS,
1736
                 0x00000000);
1737
    /* XXX : not implemented */
1738
    spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1739
                 SPR_NOACCESS, SPR_NOACCESS,
1740
                 &spr_read_generic, SPR_NOACCESS,
1741
                 0x00000000);
1742
    /* XXX : not implemented */
1743
    spr_register(env, SPR_440_DBDR, "DBDR",
1744
                 SPR_NOACCESS, SPR_NOACCESS,
1745
                 &spr_read_generic, &spr_write_generic,
1746
                 0x00000000);
1747
    /* Processor control */
1748
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1749
                 SPR_NOACCESS, SPR_NOACCESS,
1750
                 &spr_read_generic, &spr_write_generic,
1751
                 0x00000000);
1752
    spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1753
                 SPR_NOACCESS, SPR_NOACCESS,
1754
                 &spr_read_generic, SPR_NOACCESS,
1755
                 0x00000000);
1756
    /* Storage control */
1757
    spr_register(env, SPR_440_MMUCR, "MMUCR",
1758
                 SPR_NOACCESS, SPR_NOACCESS,
1759
                 &spr_read_generic, &spr_write_generic,
1760
                 0x00000000);
1761
}
1762

    
1763
/* SPR shared between PowerPC 40x implementations */
1764
static void gen_spr_40x (CPUPPCState *env)
1765
{
1766
    /* Cache */
1767
    /* not emulated, as Qemu do not emulate caches */
1768
    spr_register(env, SPR_40x_DCCR, "DCCR",
1769
                 SPR_NOACCESS, SPR_NOACCESS,
1770
                 &spr_read_generic, &spr_write_generic,
1771
                 0x00000000);
1772
    /* not emulated, as Qemu do not emulate caches */
1773
    spr_register(env, SPR_40x_ICCR, "ICCR",
1774
                 SPR_NOACCESS, SPR_NOACCESS,
1775
                 &spr_read_generic, &spr_write_generic,
1776
                 0x00000000);
1777
    /* not emulated, as Qemu do not emulate caches */
1778
    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1779
                 SPR_NOACCESS, SPR_NOACCESS,
1780
                 &spr_read_generic, SPR_NOACCESS,
1781
                 0x00000000);
1782
    /* Exception */
1783
    spr_register(env, SPR_40x_DEAR, "DEAR",
1784
                 SPR_NOACCESS, SPR_NOACCESS,
1785
                 &spr_read_generic, &spr_write_generic,
1786
                 0x00000000);
1787
    spr_register(env, SPR_40x_ESR, "ESR",
1788
                 SPR_NOACCESS, SPR_NOACCESS,
1789
                 &spr_read_generic, &spr_write_generic,
1790
                 0x00000000);
1791
    spr_register(env, SPR_40x_EVPR, "EVPR",
1792
                 SPR_NOACCESS, SPR_NOACCESS,
1793
                 &spr_read_generic, &spr_write_excp_prefix,
1794
                 0x00000000);
1795
    spr_register(env, SPR_40x_SRR2, "SRR2",
1796
                 &spr_read_generic, &spr_write_generic,
1797
                 &spr_read_generic, &spr_write_generic,
1798
                 0x00000000);
1799
    spr_register(env, SPR_40x_SRR3, "SRR3",
1800
                 &spr_read_generic, &spr_write_generic,
1801
                 &spr_read_generic, &spr_write_generic,
1802
                 0x00000000);
1803
    /* Timers */
1804
    spr_register(env, SPR_40x_PIT, "PIT",
1805
                 SPR_NOACCESS, SPR_NOACCESS,
1806
                 &spr_read_40x_pit, &spr_write_40x_pit,
1807
                 0x00000000);
1808
    spr_register(env, SPR_40x_TCR, "TCR",
1809
                 SPR_NOACCESS, SPR_NOACCESS,
1810
                 &spr_read_generic, &spr_write_booke_tcr,
1811
                 0x00000000);
1812
    spr_register(env, SPR_40x_TSR, "TSR",
1813
                 SPR_NOACCESS, SPR_NOACCESS,
1814
                 &spr_read_generic, &spr_write_booke_tsr,
1815
                 0x00000000);
1816
}
1817

    
1818
/* SPR specific to PowerPC 405 implementation */
1819
static void gen_spr_405 (CPUPPCState *env)
1820
{
1821
    /* MMU */
1822
    spr_register(env, SPR_40x_PID, "PID",
1823
                 SPR_NOACCESS, SPR_NOACCESS,
1824
                 &spr_read_generic, &spr_write_generic,
1825
                 0x00000000);
1826
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1827
                 SPR_NOACCESS, SPR_NOACCESS,
1828
                 &spr_read_generic, &spr_write_generic,
1829
                 0x00700000);
1830
    /* Debug interface */
1831
    /* XXX : not implemented */
1832
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
1833
                 SPR_NOACCESS, SPR_NOACCESS,
1834
                 &spr_read_generic, &spr_write_40x_dbcr0,
1835
                 0x00000000);
1836
    /* XXX : not implemented */
1837
    spr_register(env, SPR_405_DBCR1, "DBCR1",
1838
                 SPR_NOACCESS, SPR_NOACCESS,
1839
                 &spr_read_generic, &spr_write_generic,
1840
                 0x00000000);
1841
    /* XXX : not implemented */
1842
    spr_register(env, SPR_40x_DBSR, "DBSR",
1843
                 SPR_NOACCESS, SPR_NOACCESS,
1844
                 &spr_read_generic, &spr_write_clear,
1845
                 /* Last reset was system reset */
1846
                 0x00000300);
1847
    /* XXX : not implemented */
1848
    spr_register(env, SPR_40x_DAC1, "DAC1",
1849
                 SPR_NOACCESS, SPR_NOACCESS,
1850
                 &spr_read_generic, &spr_write_generic,
1851
                 0x00000000);
1852
    spr_register(env, SPR_40x_DAC2, "DAC2",
1853
                 SPR_NOACCESS, SPR_NOACCESS,
1854
                 &spr_read_generic, &spr_write_generic,
1855
                 0x00000000);
1856
    /* XXX : not implemented */
1857
    spr_register(env, SPR_405_DVC1, "DVC1",
1858
                 SPR_NOACCESS, SPR_NOACCESS,
1859
                 &spr_read_generic, &spr_write_generic,
1860
                 0x00000000);
1861
    /* XXX : not implemented */
1862
    spr_register(env, SPR_405_DVC2, "DVC2",
1863
                 SPR_NOACCESS, SPR_NOACCESS,
1864
                 &spr_read_generic, &spr_write_generic,
1865
                 0x00000000);
1866
    /* XXX : not implemented */
1867
    spr_register(env, SPR_40x_IAC1, "IAC1",
1868
                 SPR_NOACCESS, SPR_NOACCESS,
1869
                 &spr_read_generic, &spr_write_generic,
1870
                 0x00000000);
1871
    spr_register(env, SPR_40x_IAC2, "IAC2",
1872
                 SPR_NOACCESS, SPR_NOACCESS,
1873
                 &spr_read_generic, &spr_write_generic,
1874
                 0x00000000);
1875
    /* XXX : not implemented */
1876
    spr_register(env, SPR_405_IAC3, "IAC3",
1877
                 SPR_NOACCESS, SPR_NOACCESS,
1878
                 &spr_read_generic, &spr_write_generic,
1879
                 0x00000000);
1880
    /* XXX : not implemented */
1881
    spr_register(env, SPR_405_IAC4, "IAC4",
1882
                 SPR_NOACCESS, SPR_NOACCESS,
1883
                 &spr_read_generic, &spr_write_generic,
1884
                 0x00000000);
1885
    /* Storage control */
1886
    /* XXX: TODO: not implemented */
1887
    spr_register(env, SPR_405_SLER, "SLER",
1888
                 SPR_NOACCESS, SPR_NOACCESS,
1889
                 &spr_read_generic, &spr_write_40x_sler,
1890
                 0x00000000);
1891
    spr_register(env, SPR_40x_ZPR, "ZPR",
1892
                 SPR_NOACCESS, SPR_NOACCESS,
1893
                 &spr_read_generic, &spr_write_generic,
1894
                 0x00000000);
1895
    /* XXX : not implemented */
1896
    spr_register(env, SPR_405_SU0R, "SU0R",
1897
                 SPR_NOACCESS, SPR_NOACCESS,
1898
                 &spr_read_generic, &spr_write_generic,
1899
                 0x00000000);
1900
    /* SPRG */
1901
    spr_register(env, SPR_USPRG0, "USPRG0",
1902
                 &spr_read_ureg, SPR_NOACCESS,
1903
                 &spr_read_ureg, SPR_NOACCESS,
1904
                 0x00000000);
1905
    spr_register(env, SPR_SPRG4, "SPRG4",
1906
                 SPR_NOACCESS, SPR_NOACCESS,
1907
                 &spr_read_generic, &spr_write_generic,
1908
                 0x00000000);
1909
    spr_register(env, SPR_USPRG4, "USPRG4",
1910
                 &spr_read_ureg, SPR_NOACCESS,
1911
                 &spr_read_ureg, SPR_NOACCESS,
1912
                 0x00000000);
1913
    spr_register(env, SPR_SPRG5, "SPRG5",
1914
                 SPR_NOACCESS, SPR_NOACCESS,
1915
                 spr_read_generic, &spr_write_generic,
1916
                 0x00000000);
1917
    spr_register(env, SPR_USPRG5, "USPRG5",
1918
                 &spr_read_ureg, SPR_NOACCESS,
1919
                 &spr_read_ureg, SPR_NOACCESS,
1920
                 0x00000000);
1921
    spr_register(env, SPR_SPRG6, "SPRG6",
1922
                 SPR_NOACCESS, SPR_NOACCESS,
1923
                 spr_read_generic, &spr_write_generic,
1924
                 0x00000000);
1925
    spr_register(env, SPR_USPRG6, "USPRG6",
1926
                 &spr_read_ureg, SPR_NOACCESS,
1927
                 &spr_read_ureg, SPR_NOACCESS,
1928
                 0x00000000);
1929
    spr_register(env, SPR_SPRG7, "SPRG7",
1930
                 SPR_NOACCESS, SPR_NOACCESS,
1931
                 spr_read_generic, &spr_write_generic,
1932
                 0x00000000);
1933
    spr_register(env, SPR_USPRG7, "USPRG7",
1934
                 &spr_read_ureg, SPR_NOACCESS,
1935
                 &spr_read_ureg, SPR_NOACCESS,
1936
                 0x00000000);
1937
}
1938

    
1939
/* SPR shared between PowerPC 401 & 403 implementations */
1940
static void gen_spr_401_403 (CPUPPCState *env)
1941
{
1942
    /* Time base */
1943
    spr_register(env, SPR_403_VTBL,  "TBL",
1944
                 &spr_read_tbl, SPR_NOACCESS,
1945
                 &spr_read_tbl, SPR_NOACCESS,
1946
                 0x00000000);
1947
    spr_register(env, SPR_403_TBL,   "TBL",
1948
                 SPR_NOACCESS, SPR_NOACCESS,
1949
                 SPR_NOACCESS, &spr_write_tbl,
1950
                 0x00000000);
1951
    spr_register(env, SPR_403_VTBU,  "TBU",
1952
                 &spr_read_tbu, SPR_NOACCESS,
1953
                 &spr_read_tbu, SPR_NOACCESS,
1954
                 0x00000000);
1955
    spr_register(env, SPR_403_TBU,   "TBU",
1956
                 SPR_NOACCESS, SPR_NOACCESS,
1957
                 SPR_NOACCESS, &spr_write_tbu,
1958
                 0x00000000);
1959
    /* Debug */
1960
    /* not emulated, as Qemu do not emulate caches */
1961
    spr_register(env, SPR_403_CDBCR, "CDBCR",
1962
                 SPR_NOACCESS, SPR_NOACCESS,
1963
                 &spr_read_generic, &spr_write_generic,
1964
                 0x00000000);
1965
}
1966

    
1967
/* SPR specific to PowerPC 401 implementation */
1968
static void gen_spr_401 (CPUPPCState *env)
1969
{
1970
    /* Debug interface */
1971
    /* XXX : not implemented */
1972
    spr_register(env, SPR_40x_DBCR0, "DBCR",
1973
                 SPR_NOACCESS, SPR_NOACCESS,
1974
                 &spr_read_generic, &spr_write_40x_dbcr0,
1975
                 0x00000000);
1976
    /* XXX : not implemented */
1977
    spr_register(env, SPR_40x_DBSR, "DBSR",
1978
                 SPR_NOACCESS, SPR_NOACCESS,
1979
                 &spr_read_generic, &spr_write_clear,
1980
                 /* Last reset was system reset */
1981
                 0x00000300);
1982
    /* XXX : not implemented */
1983
    spr_register(env, SPR_40x_DAC1, "DAC",
1984
                 SPR_NOACCESS, SPR_NOACCESS,
1985
                 &spr_read_generic, &spr_write_generic,
1986
                 0x00000000);
1987
    /* XXX : not implemented */
1988
    spr_register(env, SPR_40x_IAC1, "IAC",
1989
                 SPR_NOACCESS, SPR_NOACCESS,
1990
                 &spr_read_generic, &spr_write_generic,
1991
                 0x00000000);
1992
    /* Storage control */
1993
    /* XXX: TODO: not implemented */
1994
    spr_register(env, SPR_405_SLER, "SLER",
1995
                 SPR_NOACCESS, SPR_NOACCESS,
1996
                 &spr_read_generic, &spr_write_40x_sler,
1997
                 0x00000000);
1998
    /* not emulated, as Qemu never does speculative access */
1999
    spr_register(env, SPR_40x_SGR, "SGR",
2000
                 SPR_NOACCESS, SPR_NOACCESS,
2001
                 &spr_read_generic, &spr_write_generic,
2002
                 0xFFFFFFFF);
2003
    /* not emulated, as Qemu do not emulate caches */
2004
    spr_register(env, SPR_40x_DCWR, "DCWR",
2005
                 SPR_NOACCESS, SPR_NOACCESS,
2006
                 &spr_read_generic, &spr_write_generic,
2007
                 0x00000000);
2008
}
2009

    
2010
static void gen_spr_401x2 (CPUPPCState *env)
2011
{
2012
    gen_spr_401(env);
2013
    spr_register(env, SPR_40x_PID, "PID",
2014
                 SPR_NOACCESS, SPR_NOACCESS,
2015
                 &spr_read_generic, &spr_write_generic,
2016
                 0x00000000);
2017
    spr_register(env, SPR_40x_ZPR, "ZPR",
2018
                 SPR_NOACCESS, SPR_NOACCESS,
2019
                 &spr_read_generic, &spr_write_generic,
2020
                 0x00000000);
2021
}
2022

    
2023
/* SPR specific to PowerPC 403 implementation */
2024
static void gen_spr_403 (CPUPPCState *env)
2025
{
2026
    /* Debug interface */
2027
    /* XXX : not implemented */
2028
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
2029
                 SPR_NOACCESS, SPR_NOACCESS,
2030
                 &spr_read_generic, &spr_write_40x_dbcr0,
2031
                 0x00000000);
2032
    /* XXX : not implemented */
2033
    spr_register(env, SPR_40x_DBSR, "DBSR",
2034
                 SPR_NOACCESS, SPR_NOACCESS,
2035
                 &spr_read_generic, &spr_write_clear,
2036
                 /* Last reset was system reset */
2037
                 0x00000300);
2038
    /* XXX : not implemented */
2039
    spr_register(env, SPR_40x_DAC1, "DAC1",
2040
                 SPR_NOACCESS, SPR_NOACCESS,
2041
                 &spr_read_generic, &spr_write_generic,
2042
                 0x00000000);
2043
    /* XXX : not implemented */
2044
    spr_register(env, SPR_40x_DAC2, "DAC2",
2045
                 SPR_NOACCESS, SPR_NOACCESS,
2046
                 &spr_read_generic, &spr_write_generic,
2047
                 0x00000000);
2048
    /* XXX : not implemented */
2049
    spr_register(env, SPR_40x_IAC1, "IAC1",
2050
                 SPR_NOACCESS, SPR_NOACCESS,
2051
                 &spr_read_generic, &spr_write_generic,
2052
                 0x00000000);
2053
    /* XXX : not implemented */
2054
    spr_register(env, SPR_40x_IAC2, "IAC2",
2055
                 SPR_NOACCESS, SPR_NOACCESS,
2056
                 &spr_read_generic, &spr_write_generic,
2057
                 0x00000000);
2058
}
2059

    
2060
static void gen_spr_403_real (CPUPPCState *env)
2061
{
2062
    spr_register(env, SPR_403_PBL1,  "PBL1",
2063
                 SPR_NOACCESS, SPR_NOACCESS,
2064
                 &spr_read_403_pbr, &spr_write_403_pbr,
2065
                 0x00000000);
2066
    spr_register(env, SPR_403_PBU1,  "PBU1",
2067
                 SPR_NOACCESS, SPR_NOACCESS,
2068
                 &spr_read_403_pbr, &spr_write_403_pbr,
2069
                 0x00000000);
2070
    spr_register(env, SPR_403_PBL2,  "PBL2",
2071
                 SPR_NOACCESS, SPR_NOACCESS,
2072
                 &spr_read_403_pbr, &spr_write_403_pbr,
2073
                 0x00000000);
2074
    spr_register(env, SPR_403_PBU2,  "PBU2",
2075
                 SPR_NOACCESS, SPR_NOACCESS,
2076
                 &spr_read_403_pbr, &spr_write_403_pbr,
2077
                 0x00000000);
2078
}
2079

    
2080
static void gen_spr_403_mmu (CPUPPCState *env)
2081
{
2082
    /* MMU */
2083
    spr_register(env, SPR_40x_PID, "PID",
2084
                 SPR_NOACCESS, SPR_NOACCESS,
2085
                 &spr_read_generic, &spr_write_generic,
2086
                 0x00000000);
2087
    spr_register(env, SPR_40x_ZPR, "ZPR",
2088
                 SPR_NOACCESS, SPR_NOACCESS,
2089
                 &spr_read_generic, &spr_write_generic,
2090
                 0x00000000);
2091
}
2092

    
2093
/* SPR specific to PowerPC compression coprocessor extension */
2094
static void gen_spr_compress (CPUPPCState *env)
2095
{
2096
    /* XXX : not implemented */
2097
    spr_register(env, SPR_401_SKR, "SKR",
2098
                 SPR_NOACCESS, SPR_NOACCESS,
2099
                 &spr_read_generic, &spr_write_generic,
2100
                 0x00000000);
2101
}
2102

    
2103
#if defined (TARGET_PPC64)
2104
/* SPR specific to PowerPC 620 */
2105
static void gen_spr_620 (CPUPPCState *env)
2106
{
2107
    /* XXX : not implemented */
2108
    spr_register(env, SPR_620_PMR0, "PMR0",
2109
                 SPR_NOACCESS, SPR_NOACCESS,
2110
                 &spr_read_generic, &spr_write_generic,
2111
                 0x00000000);
2112
    /* XXX : not implemented */
2113
    spr_register(env, SPR_620_PMR1, "PMR1",
2114
                 SPR_NOACCESS, SPR_NOACCESS,
2115
                 &spr_read_generic, &spr_write_generic,
2116
                 0x00000000);
2117
    /* XXX : not implemented */
2118
    spr_register(env, SPR_620_PMR2, "PMR2",
2119
                 SPR_NOACCESS, SPR_NOACCESS,
2120
                 &spr_read_generic, &spr_write_generic,
2121
                 0x00000000);
2122
    /* XXX : not implemented */
2123
    spr_register(env, SPR_620_PMR3, "PMR3",
2124
                 SPR_NOACCESS, SPR_NOACCESS,
2125
                 &spr_read_generic, &spr_write_generic,
2126
                 0x00000000);
2127
    /* XXX : not implemented */
2128
    spr_register(env, SPR_620_PMR4, "PMR4",
2129
                 SPR_NOACCESS, SPR_NOACCESS,
2130
                 &spr_read_generic, &spr_write_generic,
2131
                 0x00000000);
2132
    /* XXX : not implemented */
2133
    spr_register(env, SPR_620_PMR5, "PMR5",
2134
                 SPR_NOACCESS, SPR_NOACCESS,
2135
                 &spr_read_generic, &spr_write_generic,
2136
                 0x00000000);
2137
    /* XXX : not implemented */
2138
    spr_register(env, SPR_620_PMR6, "PMR6",
2139
                 SPR_NOACCESS, SPR_NOACCESS,
2140
                 &spr_read_generic, &spr_write_generic,
2141
                 0x00000000);
2142
    /* XXX : not implemented */
2143
    spr_register(env, SPR_620_PMR7, "PMR7",
2144
                 SPR_NOACCESS, SPR_NOACCESS,
2145
                 &spr_read_generic, &spr_write_generic,
2146
                 0x00000000);
2147
    /* XXX : not implemented */
2148
    spr_register(env, SPR_620_PMR8, "PMR8",
2149
                 SPR_NOACCESS, SPR_NOACCESS,
2150
                 &spr_read_generic, &spr_write_generic,
2151
                 0x00000000);
2152
    /* XXX : not implemented */
2153
    spr_register(env, SPR_620_PMR9, "PMR9",
2154
                 SPR_NOACCESS, SPR_NOACCESS,
2155
                 &spr_read_generic, &spr_write_generic,
2156
                 0x00000000);
2157
    /* XXX : not implemented */
2158
    spr_register(env, SPR_620_PMRA, "PMR10",
2159
                 SPR_NOACCESS, SPR_NOACCESS,
2160
                 &spr_read_generic, &spr_write_generic,
2161
                 0x00000000);
2162
    /* XXX : not implemented */
2163
    spr_register(env, SPR_620_PMRB, "PMR11",
2164
                 SPR_NOACCESS, SPR_NOACCESS,
2165
                 &spr_read_generic, &spr_write_generic,
2166
                 0x00000000);
2167
    /* XXX : not implemented */
2168
    spr_register(env, SPR_620_PMRC, "PMR12",
2169
                 SPR_NOACCESS, SPR_NOACCESS,
2170
                 &spr_read_generic, &spr_write_generic,
2171
                 0x00000000);
2172
    /* XXX : not implemented */
2173
    spr_register(env, SPR_620_PMRD, "PMR13",
2174
                 SPR_NOACCESS, SPR_NOACCESS,
2175
                 &spr_read_generic, &spr_write_generic,
2176
                 0x00000000);
2177
    /* XXX : not implemented */
2178
    spr_register(env, SPR_620_PMRE, "PMR14",
2179
                 SPR_NOACCESS, SPR_NOACCESS,
2180
                 &spr_read_generic, &spr_write_generic,
2181
                 0x00000000);
2182
    /* XXX : not implemented */
2183
    spr_register(env, SPR_620_PMRF, "PMR15",
2184
                 SPR_NOACCESS, SPR_NOACCESS,
2185
                 &spr_read_generic, &spr_write_generic,
2186
                 0x00000000);
2187
    /* XXX : not implemented */
2188
    spr_register(env, SPR_620_HID8, "HID8",
2189
                 SPR_NOACCESS, SPR_NOACCESS,
2190
                 &spr_read_generic, &spr_write_generic,
2191
                 0x00000000);
2192
    /* XXX : not implemented */
2193
    spr_register(env, SPR_620_HID9, "HID9",
2194
                 SPR_NOACCESS, SPR_NOACCESS,
2195
                 &spr_read_generic, &spr_write_generic,
2196
                 0x00000000);
2197
}
2198
#endif /* defined (TARGET_PPC64) */
2199

    
2200
// XXX: TODO
2201
/*
2202
 * AMR     => SPR 29 (Power 2.04)
2203
 * CTRL    => SPR 136 (Power 2.04)
2204
 * CTRL    => SPR 152 (Power 2.04)
2205
 * SCOMC   => SPR 276 (64 bits ?)
2206
 * SCOMD   => SPR 277 (64 bits ?)
2207
 * TBU40   => SPR 286 (Power 2.04 hypv)
2208
 * HSPRG0  => SPR 304 (Power 2.04 hypv)
2209
 * HSPRG1  => SPR 305 (Power 2.04 hypv)
2210
 * HDSISR  => SPR 306 (Power 2.04 hypv)
2211
 * HDAR    => SPR 307 (Power 2.04 hypv)
2212
 * PURR    => SPR 309 (Power 2.04 hypv)
2213
 * HDEC    => SPR 310 (Power 2.04 hypv)
2214
 * HIOR    => SPR 311 (hypv)
2215
 * RMOR    => SPR 312 (970)
2216
 * HRMOR   => SPR 313 (Power 2.04 hypv)
2217
 * HSRR0   => SPR 314 (Power 2.04 hypv)
2218
 * HSRR1   => SPR 315 (Power 2.04 hypv)
2219
 * LPCR    => SPR 316 (970)
2220
 * LPIDR   => SPR 317 (970)
2221
 * SPEFSCR => SPR 512 (Power 2.04 emb)
2222
 * EPR     => SPR 702 (Power 2.04 emb)
2223
 * perf    => 768-783 (Power 2.04)
2224
 * perf    => 784-799 (Power 2.04)
2225
 * PPR     => SPR 896 (Power 2.04)
2226
 * EPLC    => SPR 947 (Power 2.04 emb)
2227
 * EPSC    => SPR 948 (Power 2.04 emb)
2228
 * DABRX   => 1015    (Power 2.04 hypv)
2229
 * FPECR   => SPR 1022 (?)
2230
 * ... and more (thermal management, performance counters, ...)
2231
 */
2232

    
2233
/*****************************************************************************/
2234
/* Exception vectors models                                                  */
2235
static void init_excp_4xx_real (CPUPPCState *env)
2236
{
2237
#if !defined(CONFIG_USER_ONLY)
2238
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2239
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2240
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2241
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2242
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2243
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2244
    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2245
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2246
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2247
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2248
    env->excp_prefix = 0x00000000;
2249
    env->ivor_mask = 0x0000FFF0;
2250
    env->ivpr_mask = 0xFFFF0000;
2251
    /* Hardware reset vector */
2252
    env->hreset_vector = 0xFFFFFFFCUL;
2253
#endif
2254
}
2255

    
2256
static void init_excp_4xx_softmmu (CPUPPCState *env)
2257
{
2258
#if !defined(CONFIG_USER_ONLY)
2259
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2260
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2261
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2262
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2263
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2264
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2265
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2266
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2267
    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2268
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2269
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2270
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2271
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2272
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2273
    env->excp_prefix = 0x00000000;
2274
    env->ivor_mask = 0x0000FFF0;
2275
    env->ivpr_mask = 0xFFFF0000;
2276
    /* Hardware reset vector */
2277
    env->hreset_vector = 0xFFFFFFFCUL;
2278
#endif
2279
}
2280

    
2281
static void init_excp_BookE (CPUPPCState *env)
2282
{
2283
#if !defined(CONFIG_USER_ONLY)
2284
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2285
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2286
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2287
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2288
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2289
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2290
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2291
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2292
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2293
    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2294
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2295
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2296
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2297
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2298
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2299
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2300
    env->excp_prefix = 0x00000000;
2301
    env->ivor_mask = 0x0000FFE0;
2302
    env->ivpr_mask = 0xFFFF0000;
2303
    /* Hardware reset vector */
2304
    env->hreset_vector = 0xFFFFFFFCUL;
2305
#endif
2306
}
2307

    
2308
static void init_excp_601 (CPUPPCState *env)
2309
{
2310
#if !defined(CONFIG_USER_ONLY)
2311
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2312
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2313
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2314
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2315
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2316
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2317
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2318
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2319
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2320
    env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2321
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2322
    env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2323
    env->excp_prefix = 0xFFF00000;
2324
    /* Hardware reset vector */
2325
    env->hreset_vector = 0xFFFFFFFCUL;
2326
#endif
2327
}
2328

    
2329
static void init_excp_602 (CPUPPCState *env)
2330
{
2331
#if !defined(CONFIG_USER_ONLY)
2332
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2333
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2334
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2335
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2336
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2337
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2338
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2339
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2340
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2341
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2342
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2343
    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2344
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2345
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2346
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2347
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2348
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2349
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2350
    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2351
    env->excp_prefix = 0xFFF00000;
2352
    /* Hardware reset vector */
2353
    env->hreset_vector = 0xFFFFFFFCUL;
2354
#endif
2355
}
2356

    
2357
static void init_excp_603 (CPUPPCState *env)
2358
{
2359
#if !defined(CONFIG_USER_ONLY)
2360
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2361
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2362
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2363
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2364
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2365
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2366
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2367
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2368
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2369
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2370
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2371
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2372
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2373
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2374
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2375
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2376
    /* Hardware reset vector */
2377
    env->hreset_vector = 0xFFFFFFFCUL;
2378
#endif
2379
}
2380

    
2381
static void init_excp_G2 (CPUPPCState *env)
2382
{
2383
#if !defined(CONFIG_USER_ONLY)
2384
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2385
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2386
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2387
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2388
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2389
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2390
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2391
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2392
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2393
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2394
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2395
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2396
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2397
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2398
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2399
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2400
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2401
    /* Hardware reset vector */
2402
    env->hreset_vector = 0xFFFFFFFCUL;
2403
#endif
2404
}
2405

    
2406
static void init_excp_604 (CPUPPCState *env)
2407
{
2408
#if !defined(CONFIG_USER_ONLY)
2409
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2410
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2411
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2412
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2413
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2414
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2415
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2416
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2417
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2418
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2419
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2420
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2421
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2422
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2423
    /* Hardware reset vector */
2424
    env->hreset_vector = 0xFFFFFFFCUL;
2425
#endif
2426
}
2427

    
2428
#if defined(TARGET_PPC64)
2429
static void init_excp_620 (CPUPPCState *env)
2430
{
2431
#if !defined(CONFIG_USER_ONLY)
2432
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2433
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2434
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2435
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2436
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2437
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2438
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2439
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2440
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2441
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2442
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2443
    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2444
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2445
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2446
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2447
    /* Hardware reset vector */
2448
    env->hreset_vector = 0x0000000000000100ULL; /* ? */
2449
#endif
2450
}
2451
#endif /* defined(TARGET_PPC64) */
2452

    
2453
static void init_excp_7x0 (CPUPPCState *env)
2454
{
2455
#if !defined(CONFIG_USER_ONLY)
2456
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2457
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2458
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2459
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2460
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2461
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2462
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2463
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2464
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2465
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2466
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2467
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2468
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2469
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2470
    /* Hardware reset vector */
2471
    env->hreset_vector = 0xFFFFFFFCUL;
2472
#endif
2473
}
2474

    
2475
static void init_excp_750FX (CPUPPCState *env)
2476
{
2477
#if !defined(CONFIG_USER_ONLY)
2478
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2479
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2480
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2481
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2482
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2483
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2484
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2485
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2486
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2487
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2488
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2489
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2490
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2491
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2492
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2493
    /* Hardware reset vector */
2494
    env->hreset_vector = 0xFFFFFFFCUL;
2495
#endif
2496
}
2497

    
2498
/* XXX: Check if this is correct */
2499
static void init_excp_7x5 (CPUPPCState *env)
2500
{
2501
#if !defined(CONFIG_USER_ONLY)
2502
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2503
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2504
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2505
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2506
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2507
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2508
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2509
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2510
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2511
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2512
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2513
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2514
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2515
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2516
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2517
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2518
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2519
    /* Hardware reset vector */
2520
    env->hreset_vector = 0xFFFFFFFCUL;
2521
#endif
2522
}
2523

    
2524
static void init_excp_7400 (CPUPPCState *env)
2525
{
2526
#if !defined(CONFIG_USER_ONLY)
2527
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2528
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2529
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2530
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2531
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2532
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2533
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2534
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2535
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2536
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2537
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2538
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2539
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2540
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2541
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2542
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2543
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2544
    /* Hardware reset vector */
2545
    env->hreset_vector = 0xFFFFFFFCUL;
2546
#endif
2547
}
2548

    
2549
static void init_excp_7450 (CPUPPCState *env)
2550
{
2551
#if !defined(CONFIG_USER_ONLY)
2552
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2553
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2554
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2555
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2556
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2557
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2558
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2559
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2560
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2561
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2562
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2563
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2564
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2565
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2566
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2567
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2568
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2569
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2570
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2571
    /* Hardware reset vector */
2572
    env->hreset_vector = 0xFFFFFFFCUL;
2573
#endif
2574
}
2575

    
2576
#if defined (TARGET_PPC64)
2577
static void init_excp_970 (CPUPPCState *env)
2578
{
2579
#if !defined(CONFIG_USER_ONLY)
2580
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2581
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2582
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2583
    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
2584
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2585
    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
2586
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2587
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2588
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2589
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2590
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2591
#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2592
    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
2593
#endif
2594
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2595
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2596
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2597
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2598
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2599
    env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
2600
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
2601
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
2602
    /* Hardware reset vector */
2603
    env->hreset_vector = 0x0000000000000100ULL;
2604
#endif
2605
}
2606
#endif
2607

    
2608
/*****************************************************************************/
2609
/* PowerPC implementations definitions                                       */
2610

    
2611
/* PowerPC 40x instruction set                                               */
2612
#define POWERPC_INSNS_EMB    (PPC_INSNS_BASE | PPC_CACHE_DCBZ | PPC_EMB_COMMON)
2613

    
2614
/* PowerPC 401                                                               */
2615
#define POWERPC_INSNS_401    (POWERPC_INSNS_EMB |                             \
2616
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2617
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2618
#define POWERPC_MSRM_401     (0x00000000000FD201ULL)
2619
#define POWERPC_MMU_401      (POWERPC_MMU_REAL_4xx)
2620
#define POWERPC_EXCP_401     (POWERPC_EXCP_40x)
2621
#define POWERPC_INPUT_401    (PPC_FLAGS_INPUT_401)
2622
#define POWERPC_BFDM_401     (bfd_mach_ppc_403)
2623
#define POWERPC_FLAG_401     (POWERPC_FLAG_NONE)
2624

    
2625
static void init_proc_401 (CPUPPCState *env)
2626
{
2627
    gen_spr_40x(env);
2628
    gen_spr_401_403(env);
2629
    gen_spr_401(env);
2630
    init_excp_4xx_real(env);
2631
    env->dcache_line_size = 32;
2632
    env->icache_line_size = 32;
2633
    /* Allocate hardware IRQ controller */
2634
    ppc40x_irq_init(env);
2635
}
2636

    
2637
/* PowerPC 401x2                                                             */
2638
#define POWERPC_INSNS_401x2  (POWERPC_INSNS_EMB |                             \
2639
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2640
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2641
                              PPC_CACHE_DCBA | PPC_MFTB |                     \
2642
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2643
#define POWERPC_MSRM_401x2   (0x00000000001FD231ULL)
2644
#define POWERPC_MMU_401x2    (POWERPC_MMU_SOFT_4xx_Z)
2645
#define POWERPC_EXCP_401x2   (POWERPC_EXCP_40x)
2646
#define POWERPC_INPUT_401x2  (PPC_FLAGS_INPUT_401)
2647
#define POWERPC_BFDM_401x2   (bfd_mach_ppc_403)
2648
#define POWERPC_FLAG_401x2   (POWERPC_FLAG_NONE)
2649

    
2650
static void init_proc_401x2 (CPUPPCState *env)
2651
{
2652
    gen_spr_40x(env);
2653
    gen_spr_401_403(env);
2654
    gen_spr_401x2(env);
2655
    gen_spr_compress(env);
2656
    /* Memory management */
2657
#if !defined(CONFIG_USER_ONLY)
2658
    env->nb_tlb = 64;
2659
    env->nb_ways = 1;
2660
    env->id_tlbs = 0;
2661
#endif
2662
    init_excp_4xx_softmmu(env);
2663
    env->dcache_line_size = 32;
2664
    env->icache_line_size = 32;
2665
    /* Allocate hardware IRQ controller */
2666
    ppc40x_irq_init(env);
2667
}
2668

    
2669
/* PowerPC 401x3                                                             */
2670
#define POWERPC_INSNS_401x3  (POWERPC_INSNS_EMB |                             \
2671
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2672
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2673
                              PPC_CACHE_DCBA | PPC_MFTB |                     \
2674
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2675
#define POWERPC_MSRM_401x3   (0x00000000001FD631ULL)
2676
#define POWERPC_MMU_401x3    (POWERPC_MMU_SOFT_4xx_Z)
2677
#define POWERPC_EXCP_401x3   (POWERPC_EXCP_40x)
2678
#define POWERPC_INPUT_401x3  (PPC_FLAGS_INPUT_401)
2679
#define POWERPC_BFDM_401x3   (bfd_mach_ppc_403)
2680
#define POWERPC_FLAG_401x3   (POWERPC_FLAG_NONE)
2681

    
2682
__attribute__ (( unused ))
2683
static void init_proc_401x3 (CPUPPCState *env)
2684
{
2685
    gen_spr_40x(env);
2686
    gen_spr_401_403(env);
2687
    gen_spr_401(env);
2688
    gen_spr_401x2(env);
2689
    gen_spr_compress(env);
2690
    init_excp_4xx_softmmu(env);
2691
    env->dcache_line_size = 32;
2692
    env->icache_line_size = 32;
2693
    /* Allocate hardware IRQ controller */
2694
    ppc40x_irq_init(env);
2695
}
2696

    
2697
/* IOP480                                                                    */
2698
#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB |                             \
2699
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2700
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2701
                              PPC_CACHE_DCBA |                                \
2702
                              PPC_4xx_COMMON | PPC_40x_EXCP |  PPC_40x_ICBT)
2703
#define POWERPC_MSRM_IOP480  (0x00000000001FD231ULL)
2704
#define POWERPC_MMU_IOP480   (POWERPC_MMU_SOFT_4xx_Z)
2705
#define POWERPC_EXCP_IOP480  (POWERPC_EXCP_40x)
2706
#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2707
#define POWERPC_BFDM_IOP480  (bfd_mach_ppc_403)
2708
#define POWERPC_FLAG_IOP480  (POWERPC_FLAG_NONE)
2709

    
2710
static void init_proc_IOP480 (CPUPPCState *env)
2711
{
2712
    gen_spr_40x(env);
2713
    gen_spr_401_403(env);
2714
    gen_spr_401x2(env);
2715
    gen_spr_compress(env);
2716
    /* Memory management */
2717
#if !defined(CONFIG_USER_ONLY)
2718
    env->nb_tlb = 64;
2719
    env->nb_ways = 1;
2720
    env->id_tlbs = 0;
2721
#endif
2722
    init_excp_4xx_softmmu(env);
2723
    env->dcache_line_size = 32;
2724
    env->icache_line_size = 32;
2725
    /* Allocate hardware IRQ controller */
2726
    ppc40x_irq_init(env);
2727
}
2728

    
2729
/* PowerPC 403                                                               */
2730
#define POWERPC_INSNS_403    (POWERPC_INSNS_EMB |                             \
2731
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2732
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2733
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2734
#define POWERPC_MSRM_403     (0x000000000007D00DULL)
2735
#define POWERPC_MMU_403      (POWERPC_MMU_REAL_4xx)
2736
#define POWERPC_EXCP_403     (POWERPC_EXCP_40x)
2737
#define POWERPC_INPUT_403    (PPC_FLAGS_INPUT_401)
2738
#define POWERPC_BFDM_403     (bfd_mach_ppc_403)
2739
#define POWERPC_FLAG_403     (POWERPC_FLAG_NONE)
2740

    
2741
static void init_proc_403 (CPUPPCState *env)
2742
{
2743
    gen_spr_40x(env);
2744
    gen_spr_401_403(env);
2745
    gen_spr_403(env);
2746
    gen_spr_403_real(env);
2747
    init_excp_4xx_real(env);
2748
    env->dcache_line_size = 32;
2749
    env->icache_line_size = 32;
2750
    /* Allocate hardware IRQ controller */
2751
    ppc40x_irq_init(env);
2752
#if !defined(CONFIG_USER_ONLY)
2753
    /* Hardware reset vector */
2754
    env->hreset_vector = 0xFFFFFFFCUL;
2755
#endif
2756
}
2757

    
2758
/* PowerPC 403 GCX                                                           */
2759
#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB |                             \
2760
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2761
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2762
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2763
#define POWERPC_MSRM_403GCX  (0x000000000007D00DULL)
2764
#define POWERPC_MMU_403GCX   (POWERPC_MMU_SOFT_4xx_Z)
2765
#define POWERPC_EXCP_403GCX  (POWERPC_EXCP_40x)
2766
#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2767
#define POWERPC_BFDM_403GCX  (bfd_mach_ppc_403)
2768
#define POWERPC_FLAG_403GCX  (POWERPC_FLAG_NONE)
2769

    
2770
static void init_proc_403GCX (CPUPPCState *env)
2771
{
2772
    gen_spr_40x(env);
2773
    gen_spr_401_403(env);
2774
    gen_spr_403(env);
2775
    gen_spr_403_real(env);
2776
    gen_spr_403_mmu(env);
2777
    /* Bus access control */
2778
    /* not emulated, as Qemu never does speculative access */
2779
    spr_register(env, SPR_40x_SGR, "SGR",
2780
                 SPR_NOACCESS, SPR_NOACCESS,
2781
                 &spr_read_generic, &spr_write_generic,
2782
                 0xFFFFFFFF);
2783
    /* not emulated, as Qemu do not emulate caches */
2784
    spr_register(env, SPR_40x_DCWR, "DCWR",
2785
                 SPR_NOACCESS, SPR_NOACCESS,
2786
                 &spr_read_generic, &spr_write_generic,
2787
                 0x00000000);
2788
    /* Memory management */
2789
#if !defined(CONFIG_USER_ONLY)
2790
    env->nb_tlb = 64;
2791
    env->nb_ways = 1;
2792
    env->id_tlbs = 0;
2793
#endif
2794
    init_excp_4xx_softmmu(env);
2795
    env->dcache_line_size = 32;
2796
    env->icache_line_size = 32;
2797
    /* Allocate hardware IRQ controller */
2798
    ppc40x_irq_init(env);
2799
}
2800

    
2801
/* PowerPC 405                                                               */
2802
#define POWERPC_INSNS_405    (POWERPC_INSNS_EMB | PPC_MFTB |                  \
2803
                              PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2804
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2805
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT |  \
2806
                              PPC_405_MAC)
2807
#define POWERPC_MSRM_405     (0x000000000006E630ULL)
2808
#define POWERPC_MMU_405      (POWERPC_MMU_SOFT_4xx)
2809
#define POWERPC_EXCP_405     (POWERPC_EXCP_40x)
2810
#define POWERPC_INPUT_405    (PPC_FLAGS_INPUT_405)
2811
#define POWERPC_BFDM_405     (bfd_mach_ppc_403)
2812
#define POWERPC_FLAG_405     (POWERPC_FLAG_NONE)
2813

    
2814
static void init_proc_405 (CPUPPCState *env)
2815
{
2816
    /* Time base */
2817
    gen_tbl(env);
2818
    gen_spr_40x(env);
2819
    gen_spr_405(env);
2820
    /* Bus access control */
2821
    /* not emulated, as Qemu never does speculative access */
2822
    spr_register(env, SPR_40x_SGR, "SGR",
2823
                 SPR_NOACCESS, SPR_NOACCESS,
2824
                 &spr_read_generic, &spr_write_generic,
2825
                 0xFFFFFFFF);
2826
    /* not emulated, as Qemu do not emulate caches */
2827
    spr_register(env, SPR_40x_DCWR, "DCWR",
2828
                 SPR_NOACCESS, SPR_NOACCESS,
2829
                 &spr_read_generic, &spr_write_generic,
2830
                 0x00000000);
2831
    /* Memory management */
2832
#if !defined(CONFIG_USER_ONLY)
2833
    env->nb_tlb = 64;
2834
    env->nb_ways = 1;
2835
    env->id_tlbs = 0;
2836
#endif
2837
    init_excp_4xx_softmmu(env);
2838
    env->dcache_line_size = 32;
2839
    env->icache_line_size = 32;
2840
    /* Allocate hardware IRQ controller */
2841
    ppc40x_irq_init(env);
2842
}
2843

    
2844
/* PowerPC 440 EP                                                            */
2845
#define POWERPC_INSNS_440EP  (POWERPC_INSNS_EMB |                             \
2846
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2847
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
2848
                              PPC_440_SPEC | PPC_RFMCI)
2849
#define POWERPC_MSRM_440EP   (0x000000000006D630ULL)
2850
#define POWERPC_MMU_440EP    (POWERPC_MMU_BOOKE)
2851
#define POWERPC_EXCP_440EP   (POWERPC_EXCP_BOOKE)
2852
#define POWERPC_INPUT_440EP  (PPC_FLAGS_INPUT_BookE)
2853
#define POWERPC_BFDM_440EP   (bfd_mach_ppc_403)
2854
#define POWERPC_FLAG_440EP   (POWERPC_FLAG_NONE)
2855

    
2856
static void init_proc_440EP (CPUPPCState *env)
2857
{
2858
    /* Time base */
2859
    gen_tbl(env);
2860
    gen_spr_BookE(env);
2861
    gen_spr_440(env);
2862
    /* XXX : not implemented */
2863
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2864
                 SPR_NOACCESS, SPR_NOACCESS,
2865
                 &spr_read_generic, &spr_write_generic,
2866
                 0x00000000);
2867
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2868
                 SPR_NOACCESS, SPR_NOACCESS,
2869
                 &spr_read_generic, &spr_write_generic,
2870
                 0x00000000);
2871
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2872
                 SPR_NOACCESS, SPR_NOACCESS,
2873
                 &spr_read_generic, &spr_write_generic,
2874
                 0x00000000);
2875
    /* XXX : not implemented */
2876
    spr_register(env, SPR_440_CCR1, "CCR1",
2877
                 SPR_NOACCESS, SPR_NOACCESS,
2878
                 &spr_read_generic, &spr_write_generic,
2879
                 0x00000000);
2880
    /* Memory management */
2881
#if !defined(CONFIG_USER_ONLY)
2882
    env->nb_tlb = 64;
2883
    env->nb_ways = 1;
2884
    env->id_tlbs = 0;
2885
#endif
2886
    init_excp_BookE(env);
2887
    env->dcache_line_size = 32;
2888
    env->icache_line_size = 32;
2889
    /* XXX: TODO: allocate internal IRQ controller */
2890
}
2891

    
2892
/* PowerPC 440 GP                                                            */
2893
#define POWERPC_INSNS_440GP  (POWERPC_INSNS_EMB |                             \
2894
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2895
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
2896
                              PPC_405_MAC | PPC_440_SPEC)
2897
#define POWERPC_MSRM_440GP   (0x000000000006FF30ULL)
2898
#define POWERPC_MMU_440GP    (POWERPC_MMU_BOOKE)
2899
#define POWERPC_EXCP_440GP   (POWERPC_EXCP_BOOKE)
2900
#define POWERPC_INPUT_440GP  (PPC_FLAGS_INPUT_BookE)
2901
#define POWERPC_BFDM_440GP   (bfd_mach_ppc_403)
2902
#define POWERPC_FLAG_440GP   (POWERPC_FLAG_NONE)
2903

    
2904
static void init_proc_440GP (CPUPPCState *env)
2905
{
2906
    /* Time base */
2907
    gen_tbl(env);
2908
    gen_spr_BookE(env);
2909
    gen_spr_440(env);
2910
    /* Memory management */
2911
#if !defined(CONFIG_USER_ONLY)
2912
    env->nb_tlb = 64;
2913
    env->nb_ways = 1;
2914
    env->id_tlbs = 0;
2915
#endif
2916
    init_excp_BookE(env);
2917
    env->dcache_line_size = 32;
2918
    env->icache_line_size = 32;
2919
    /* XXX: TODO: allocate internal IRQ controller */
2920
}
2921

    
2922
/* PowerPC 440x4                                                             */
2923
#define POWERPC_INSNS_440x4  (POWERPC_INSNS_EMB |                             \
2924
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2925
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
2926
                              PPC_440_SPEC)
2927
#define POWERPC_MSRM_440x4   (0x000000000006FF30ULL)
2928
#define POWERPC_MMU_440x4    (POWERPC_MMU_BOOKE)
2929
#define POWERPC_EXCP_440x4   (POWERPC_EXCP_BOOKE)
2930
#define POWERPC_INPUT_440x4  (PPC_FLAGS_INPUT_BookE)
2931
#define POWERPC_BFDM_440x4   (bfd_mach_ppc_403)
2932
#define POWERPC_FLAG_440x4   (POWERPC_FLAG_NONE)
2933

    
2934
__attribute__ (( unused ))
2935
static void init_proc_440x4 (CPUPPCState *env)
2936
{
2937
    /* Time base */
2938
    gen_tbl(env);
2939
    gen_spr_BookE(env);
2940
    gen_spr_440(env);
2941
    /* Memory management */
2942
#if !defined(CONFIG_USER_ONLY)
2943
    env->nb_tlb = 64;
2944
    env->nb_ways = 1;
2945
    env->id_tlbs = 0;
2946
#endif
2947
    init_excp_BookE(env);
2948
    env->dcache_line_size = 32;
2949
    env->icache_line_size = 32;
2950
    /* XXX: TODO: allocate internal IRQ controller */
2951
}
2952

    
2953
/* PowerPC 440x5                                                             */
2954
#define POWERPC_INSNS_440x5  (POWERPC_INSNS_EMB |                             \
2955
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2956
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
2957
                              PPC_440_SPEC | PPC_RFMCI)
2958
#define POWERPC_MSRM_440x5   (0x000000000006FF30ULL)
2959
#define POWERPC_MMU_440x5    (POWERPC_MMU_BOOKE)
2960
#define POWERPC_EXCP_440x5   (POWERPC_EXCP_BOOKE)
2961
#define POWERPC_INPUT_440x5  (PPC_FLAGS_INPUT_BookE)
2962
#define POWERPC_BFDM_440x5   (bfd_mach_ppc_403)
2963
#define POWERPC_FLAG_440x5   (POWERPC_FLAG_NONE)
2964

    
2965
static void init_proc_440x5 (CPUPPCState *env)
2966
{
2967
    /* Time base */
2968
    gen_tbl(env);
2969
    gen_spr_BookE(env);
2970
    gen_spr_440(env);
2971
    /* XXX : not implemented */
2972
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2973
                 SPR_NOACCESS, SPR_NOACCESS,
2974
                 &spr_read_generic, &spr_write_generic,
2975
                 0x00000000);
2976
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2977
                 SPR_NOACCESS, SPR_NOACCESS,
2978
                 &spr_read_generic, &spr_write_generic,
2979
                 0x00000000);
2980
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2981
                 SPR_NOACCESS, SPR_NOACCESS,
2982
                 &spr_read_generic, &spr_write_generic,
2983
                 0x00000000);
2984
    /* XXX : not implemented */
2985
    spr_register(env, SPR_440_CCR1, "CCR1",
2986
                 SPR_NOACCESS, SPR_NOACCESS,
2987
                 &spr_read_generic, &spr_write_generic,
2988
                 0x00000000);
2989
    /* Memory management */
2990
#if !defined(CONFIG_USER_ONLY)
2991
    env->nb_tlb = 64;
2992
    env->nb_ways = 1;
2993
    env->id_tlbs = 0;
2994
#endif
2995
    init_excp_BookE(env);
2996
    env->dcache_line_size = 32;
2997
    env->icache_line_size = 32;
2998
    /* XXX: TODO: allocate internal IRQ controller */
2999
}
3000

    
3001
/* PowerPC 460 (guessed)                                                     */
3002
#define POWERPC_INSNS_460    (POWERPC_INSNS_EMB |                             \
3003
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
3004
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
3005
                              PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3006
#define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3007
#define POWERPC_MMU_460      (POWERPC_MMU_BOOKE)
3008
#define POWERPC_EXCP_460     (POWERPC_EXCP_BOOKE)
3009
#define POWERPC_INPUT_460    (PPC_FLAGS_INPUT_BookE)
3010
#define POWERPC_BFDM_460     (bfd_mach_ppc_403)
3011
#define POWERPC_FLAG_460     (POWERPC_FLAG_NONE)
3012

    
3013
__attribute__ (( unused ))
3014
static void init_proc_460 (CPUPPCState *env)
3015
{
3016
    /* Time base */
3017
    gen_tbl(env);
3018
    gen_spr_BookE(env);
3019
    gen_spr_440(env);
3020
    /* XXX : not implemented */
3021
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3022
                 SPR_NOACCESS, SPR_NOACCESS,
3023
                 &spr_read_generic, &spr_write_generic,
3024
                 0x00000000);
3025
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3026
                 SPR_NOACCESS, SPR_NOACCESS,
3027
                 &spr_read_generic, &spr_write_generic,
3028
                 0x00000000);
3029
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3030
                 SPR_NOACCESS, SPR_NOACCESS,
3031
                 &spr_read_generic, &spr_write_generic,
3032
                 0x00000000);
3033
    /* XXX : not implemented */
3034
    spr_register(env, SPR_440_CCR1, "CCR1",
3035
                 SPR_NOACCESS, SPR_NOACCESS,
3036
                 &spr_read_generic, &spr_write_generic,
3037
                 0x00000000);
3038
    /* XXX : not implemented */
3039
    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3040
                 &spr_read_generic, &spr_write_generic,
3041
                 &spr_read_generic, &spr_write_generic,
3042
                 0x00000000);
3043
    /* Memory management */
3044
#if !defined(CONFIG_USER_ONLY)
3045
    env->nb_tlb = 64;
3046
    env->nb_ways = 1;
3047
    env->id_tlbs = 0;
3048
#endif
3049
    init_excp_BookE(env);
3050
    env->dcache_line_size = 32;
3051
    env->icache_line_size = 32;
3052
    /* XXX: TODO: allocate internal IRQ controller */
3053
}
3054

    
3055
/* PowerPC 460F (guessed)                                                    */
3056
#define POWERPC_INSNS_460F   (POWERPC_INSNS_EMB |                             \
3057
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
3058
                              PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES |  \
3059
                              PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |            \
3060
                              PPC_FLOAT_STFIWX |                              \
3061
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
3062
                              PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3063
#define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3064
#define POWERPC_MMU_460F     (POWERPC_MMU_BOOKE)
3065
#define POWERPC_EXCP_460F    (POWERPC_EXCP_BOOKE)
3066
#define POWERPC_INPUT_460F   (PPC_FLAGS_INPUT_BookE)
3067
#define POWERPC_BFDM_460F    (bfd_mach_ppc_403)
3068
#define POWERPC_FLAG_460F    (POWERPC_FLAG_NONE)
3069

    
3070
__attribute__ (( unused ))
3071
static void init_proc_460F (CPUPPCState *env)
3072
{
3073
    /* Time base */
3074
    gen_tbl(env);
3075
    gen_spr_BookE(env);
3076
    gen_spr_440(env);
3077
    /* XXX : not implemented */
3078
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3079
                 SPR_NOACCESS, SPR_NOACCESS,
3080
                 &spr_read_generic, &spr_write_generic,
3081
                 0x00000000);
3082
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3083
                 SPR_NOACCESS, SPR_NOACCESS,
3084
                 &spr_read_generic, &spr_write_generic,
3085
                 0x00000000);
3086
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3087
                 SPR_NOACCESS, SPR_NOACCESS,
3088
                 &spr_read_generic, &spr_write_generic,
3089
                 0x00000000);
3090
    /* XXX : not implemented */
3091
    spr_register(env, SPR_440_CCR1, "CCR1",
3092
                 SPR_NOACCESS, SPR_NOACCESS,
3093
                 &spr_read_generic, &spr_write_generic,
3094
                 0x00000000);
3095
    /* XXX : not implemented */
3096
    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3097
                 &spr_read_generic, &spr_write_generic,
3098
                 &spr_read_generic, &spr_write_generic,
3099
                 0x00000000);
3100
    /* Memory management */
3101
#if !defined(CONFIG_USER_ONLY)
3102
    env->nb_tlb = 64;
3103
    env->nb_ways = 1;
3104
    env->id_tlbs = 0;
3105
#endif
3106
    init_excp_BookE(env);
3107
    env->dcache_line_size = 32;
3108
    env->icache_line_size = 32;
3109
    /* XXX: TODO: allocate internal IRQ controller */
3110
}
3111

    
3112
/* Generic BookE PowerPC                                                     */
3113
#define POWERPC_INSNS_BookE  (POWERPC_INSNS_EMB |                             \
3114
                              PPC_MEM_EIEIO | PPC_MEM_TLBSYNC |               \
3115
                              PPC_CACHE_DCBA |                                \
3116
                              PPC_FLOAT | PPC_FLOAT_FSQRT |                   \
3117
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
3118
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIW |              \
3119
                              PPC_BOOKE)
3120
#define POWERPC_MSRM_BookE   (0x000000000006D630ULL)
3121
#define POWERPC_MMU_BookE    (POWERPC_MMU_BOOKE)
3122
#define POWERPC_EXCP_BookE   (POWERPC_EXCP_BOOKE)
3123
#define POWERPC_INPUT_BookE  (PPC_FLAGS_INPUT_BookE)
3124
#define POWERPC_BFDM_BookE   (bfd_mach_ppc_403)
3125
#define POWERPC_FLAG_BookE   (POWERPC_FLAG_NONE)
3126

    
3127
__attribute__ (( unused ))
3128
static void init_proc_BookE (CPUPPCState *env)
3129
{
3130
    init_excp_BookE(env);
3131
    env->dcache_line_size = 32;
3132
    env->icache_line_size = 32;
3133
}
3134

    
3135
/* e200 core                                                                 */
3136

    
3137
/* e300 core                                                                 */
3138

    
3139
/* e500 core                                                                 */
3140
#define POWERPC_INSNS_e500   (POWERPC_INSNS_EMB |                             \
3141
                              PPC_MEM_EIEIO | PPC_MEM_TLBSYNC |               \
3142
                              PPC_CACHE_DCBA |                                \
3143
                              PPC_BOOKE | PPC_E500_VECTOR)
3144
#define POWERPC_MMU_e500     (POWERPC_MMU_SOFT_4xx)
3145
#define POWERPC_EXCP_e500    (POWERPC_EXCP_40x)
3146
#define POWERPC_INPUT_e500   (PPC_FLAGS_INPUT_BookE)
3147
#define POWERPC_BFDM_e500    (bfd_mach_ppc_403)
3148
#define POWERPC_FLAG_e500    (POWERPC_FLAG_SPE)
3149

    
3150
__attribute__ (( unused ))
3151
static void init_proc_e500 (CPUPPCState *env)
3152
{
3153
    /* Time base */
3154
    gen_tbl(env);
3155
    gen_spr_BookE(env);
3156
    /* Memory management */
3157
    gen_spr_BookE_FSL(env);
3158
#if !defined(CONFIG_USER_ONLY)
3159
    env->nb_tlb = 64;
3160
    env->nb_ways = 1;
3161
    env->id_tlbs = 0;
3162
#endif
3163
    init_excp_BookE(env);
3164
    env->dcache_line_size = 32;
3165
    env->icache_line_size = 32;
3166
    /* XXX: TODO: allocate internal IRQ controller */
3167
}
3168

    
3169
/* e600 core                                                                 */
3170

    
3171
/* Non-embedded PowerPC                                                      */
3172
/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC                    */
3173
#define POWERPC_INSNS_6xx    (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC |     \
3174
                              PPC_MEM_EIEIO | PPC_MEM_TLBIE)
3175
/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602      */
3176
#define POWERPC_INSNS_WORKS  (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT |           \
3177
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
3178
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX |             \
3179
                              PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB |   \
3180
                              PPC_SEGMENT)
3181

    
3182
/* POWER : same as 601, without mfmsr, mfsr                                  */
3183
#if defined(TODO)
3184
#define POWERPC_INSNS_POWER  (XXX_TODO)
3185
/* POWER RSC (from RAD6000) */
3186
#define POWERPC_MSRM_POWER   (0x00000000FEF0ULL)
3187
#endif /* TODO */
3188

    
3189
/* PowerPC 601                                                               */
3190
#define POWERPC_INSNS_601    (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ |            \
3191
                              PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
3192
#define POWERPC_MSRM_601     (0x000000000000FE70ULL)
3193
//#define POWERPC_MMU_601      (POWERPC_MMU_601)
3194
//#define POWERPC_EXCP_601     (POWERPC_EXCP_601)
3195
#define POWERPC_INPUT_601    (PPC_FLAGS_INPUT_6xx)
3196
#define POWERPC_BFDM_601     (bfd_mach_ppc_601)
3197
#define POWERPC_FLAG_601     (POWERPC_FLAG_NONE)
3198

    
3199
static void init_proc_601 (CPUPPCState *env)
3200
{
3201
    gen_spr_ne_601(env);
3202
    gen_spr_601(env);
3203
    /* Hardware implementation registers */
3204
    /* XXX : not implemented */
3205
    spr_register(env, SPR_HID0, "HID0",
3206
                 SPR_NOACCESS, SPR_NOACCESS,
3207
                 &spr_read_generic, &spr_write_generic,
3208
                 0x00000000);
3209
    /* XXX : not implemented */
3210
    spr_register(env, SPR_HID1, "HID1",
3211
                 SPR_NOACCESS, SPR_NOACCESS,
3212
                 &spr_read_generic, &spr_write_generic,
3213
                 0x00000000);
3214
    /* XXX : not implemented */
3215
    spr_register(env, SPR_601_HID2, "HID2",
3216
                 SPR_NOACCESS, SPR_NOACCESS,
3217
                 &spr_read_generic, &spr_write_generic,
3218
                 0x00000000);
3219
    /* XXX : not implemented */
3220
    spr_register(env, SPR_601_HID5, "HID5",
3221
                 SPR_NOACCESS, SPR_NOACCESS,
3222
                 &spr_read_generic, &spr_write_generic,
3223
                 0x00000000);
3224
    /* XXX : not implemented */
3225
    spr_register(env, SPR_601_HID15, "HID15",
3226
                 SPR_NOACCESS, SPR_NOACCESS,
3227
                 &spr_read_generic, &spr_write_generic,
3228
                 0x00000000);
3229
    /* Memory management */
3230
#if !defined(CONFIG_USER_ONLY)
3231
    env->nb_tlb = 64;
3232
    env->nb_ways = 2;
3233
    env->id_tlbs = 0;
3234
#endif
3235
    init_excp_601(env);
3236
    env->dcache_line_size = 64;
3237
    env->icache_line_size = 64;
3238
    /* XXX: TODO: allocate internal IRQ controller */
3239
}
3240

    
3241
/* PowerPC 602                                                               */
3242
#define POWERPC_INSNS_602    (POWERPC_INSNS_6xx | PPC_MFTB |                  \
3243
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
3244
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX |             \
3245
                              PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
3246
                              PPC_SEGMENT | PPC_602_SPEC)
3247
#define POWERPC_MSRM_602     (0x000000000033FF73ULL)
3248
#define POWERPC_MMU_602      (POWERPC_MMU_SOFT_6xx)
3249
//#define POWERPC_EXCP_602     (POWERPC_EXCP_602)
3250
#define POWERPC_INPUT_602    (PPC_FLAGS_INPUT_6xx)
3251
#define POWERPC_BFDM_602     (bfd_mach_ppc_602)
3252
#define POWERPC_FLAG_602     (POWERPC_FLAG_TGPR)
3253

    
3254
static void init_proc_602 (CPUPPCState *env)
3255
{
3256
    gen_spr_ne_601(env);
3257
    gen_spr_602(env);
3258
    /* Time base */
3259
    gen_tbl(env);
3260
    /* hardware implementation registers */
3261
    /* XXX : not implemented */
3262
    spr_register(env, SPR_HID0, "HID0",
3263
                 SPR_NOACCESS, SPR_NOACCESS,
3264
                 &spr_read_generic, &spr_write_generic,
3265
                 0x00000000);
3266
    /* XXX : not implemented */
3267
    spr_register(env, SPR_HID1, "HID1",
3268
                 SPR_NOACCESS, SPR_NOACCESS,
3269
                 &spr_read_generic, &spr_write_generic,
3270
                 0x00000000);
3271
    /* Memory management */
3272
    gen_low_BATs(env);
3273
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3274
    init_excp_602(env);
3275
    env->dcache_line_size = 32;
3276
    env->icache_line_size = 32;
3277
    /* Allocate hardware IRQ controller */
3278
    ppc6xx_irq_init(env);
3279
}
3280

    
3281
/* PowerPC 603                                                               */
3282
#define POWERPC_INSNS_603    (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3283
#define POWERPC_MSRM_603     (0x000000000001FF73ULL)
3284
#define POWERPC_MMU_603      (POWERPC_MMU_SOFT_6xx)
3285
//#define POWERPC_EXCP_603     (POWERPC_EXCP_603)
3286
#define POWERPC_INPUT_603    (PPC_FLAGS_INPUT_6xx)
3287
#define POWERPC_BFDM_603     (bfd_mach_ppc_603)
3288
#define POWERPC_FLAG_603     (POWERPC_FLAG_TGPR)
3289

    
3290
static void init_proc_603 (CPUPPCState *env)
3291
{
3292
    gen_spr_ne_601(env);
3293
    gen_spr_603(env);
3294
    /* Time base */
3295
    gen_tbl(env);
3296
    /* hardware implementation registers */
3297
    /* XXX : not implemented */
3298
    spr_register(env, SPR_HID0, "HID0",
3299
                 SPR_NOACCESS, SPR_NOACCESS,
3300
                 &spr_read_generic, &spr_write_generic,
3301
                 0x00000000);
3302
    /* XXX : not implemented */
3303
    spr_register(env, SPR_HID1, "HID1",
3304
                 SPR_NOACCESS, SPR_NOACCESS,
3305
                 &spr_read_generic, &spr_write_generic,
3306
                 0x00000000);
3307
    /* Memory management */
3308
    gen_low_BATs(env);
3309
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3310
    init_excp_603(env);
3311
    env->dcache_line_size = 32;
3312
    env->icache_line_size = 32;
3313
    /* Allocate hardware IRQ controller */
3314
    ppc6xx_irq_init(env);
3315
}
3316

    
3317
/* PowerPC 603e                                                              */
3318
#define POWERPC_INSNS_603E   (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3319
#define POWERPC_MSRM_603E    (0x000000000007FF73ULL)
3320
#define POWERPC_MMU_603E     (POWERPC_MMU_SOFT_6xx)
3321
//#define POWERPC_EXCP_603E    (POWERPC_EXCP_603E)
3322
#define POWERPC_INPUT_603E   (PPC_FLAGS_INPUT_6xx)
3323
#define POWERPC_BFDM_603E    (bfd_mach_ppc_ec603e)
3324
#define POWERPC_FLAG_603E    (POWERPC_FLAG_TGPR)
3325

    
3326
static void init_proc_603E (CPUPPCState *env)
3327
{
3328
    gen_spr_ne_601(env);
3329
    gen_spr_603(env);
3330
    /* Time base */
3331
    gen_tbl(env);
3332
    /* hardware implementation registers */
3333
    /* XXX : not implemented */
3334
    spr_register(env, SPR_HID0, "HID0",
3335
                 SPR_NOACCESS, SPR_NOACCESS,
3336
                 &spr_read_generic, &spr_write_generic,
3337
                 0x00000000);
3338
    /* XXX : not implemented */
3339
    spr_register(env, SPR_HID1, "HID1",
3340
                 SPR_NOACCESS, SPR_NOACCESS,
3341
                 &spr_read_generic, &spr_write_generic,
3342
                 0x00000000);
3343
    /* XXX : not implemented */
3344
    spr_register(env, SPR_IABR, "IABR",
3345
                 SPR_NOACCESS, SPR_NOACCESS,
3346
                 &spr_read_generic, &spr_write_generic,
3347
                 0x00000000);
3348
    /* Memory management */
3349
    gen_low_BATs(env);
3350
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3351
    init_excp_603(env);
3352
    env->dcache_line_size = 32;
3353
    env->icache_line_size = 32;
3354
    /* Allocate hardware IRQ controller */
3355
    ppc6xx_irq_init(env);
3356
}
3357

    
3358
/* PowerPC G2                                                                */
3359
#define POWERPC_INSNS_G2     (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3360
#define POWERPC_MSRM_G2      (0x000000000006FFF2ULL)
3361
#define POWERPC_MMU_G2       (POWERPC_MMU_SOFT_6xx)
3362
//#define POWERPC_EXCP_G2      (POWERPC_EXCP_G2)
3363
#define POWERPC_INPUT_G2     (PPC_FLAGS_INPUT_6xx)
3364
#define POWERPC_BFDM_G2      (bfd_mach_ppc_ec603e)
3365
#define POWERPC_FLAG_G2      (POWERPC_FLAG_TGPR)
3366

    
3367
static void init_proc_G2 (CPUPPCState *env)
3368
{
3369
    gen_spr_ne_601(env);
3370
    gen_spr_G2_755(env);
3371
    gen_spr_G2(env);
3372
    /* Time base */
3373
    gen_tbl(env);
3374
    /* Hardware implementation register */
3375
    /* XXX : not implemented */
3376
    spr_register(env, SPR_HID0, "HID0",
3377
                 SPR_NOACCESS, SPR_NOACCESS,
3378
                 &spr_read_generic, &spr_write_generic,
3379
                 0x00000000);
3380
    /* XXX : not implemented */
3381
    spr_register(env, SPR_HID1, "HID1",
3382
                 SPR_NOACCESS, SPR_NOACCESS,
3383
                 &spr_read_generic, &spr_write_generic,
3384
                 0x00000000);
3385
    /* XXX : not implemented */
3386
    spr_register(env, SPR_HID2, "HID2",
3387
                 SPR_NOACCESS, SPR_NOACCESS,
3388
                 &spr_read_generic, &spr_write_generic,
3389
                 0x00000000);
3390
    /* Memory management */
3391
    gen_low_BATs(env);
3392
    gen_high_BATs(env);
3393
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3394
    init_excp_G2(env);
3395
    env->dcache_line_size = 32;
3396
    env->icache_line_size = 32;
3397
    /* Allocate hardware IRQ controller */
3398
    ppc6xx_irq_init(env);
3399
}
3400

    
3401
/* PowerPC G2LE                                                              */
3402
#define POWERPC_INSNS_G2LE   (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3403
#define POWERPC_MSRM_G2LE    (0x000000000007FFF3ULL)
3404
#define POWERPC_MMU_G2LE     (POWERPC_MMU_SOFT_6xx)
3405
#define POWERPC_EXCP_G2LE    (POWERPC_EXCP_G2)
3406
#define POWERPC_INPUT_G2LE   (PPC_FLAGS_INPUT_6xx)
3407
#define POWERPC_BFDM_G2LE    (bfd_mach_ppc_ec603e)
3408
#define POWERPC_FLAG_G2LE    (POWERPC_FLAG_TGPR)
3409

    
3410
static void init_proc_G2LE (CPUPPCState *env)
3411
{
3412
    gen_spr_ne_601(env);
3413
    gen_spr_G2_755(env);
3414
    gen_spr_G2(env);
3415
    /* Time base */
3416
    gen_tbl(env);
3417
    /* Hardware implementation register */
3418
    /* XXX : not implemented */
3419
    spr_register(env, SPR_HID0, "HID0",
3420
                 SPR_NOACCESS, SPR_NOACCESS,
3421
                 &spr_read_generic, &spr_write_generic,
3422
                 0x00000000);
3423
    /* XXX : not implemented */
3424
    spr_register(env, SPR_HID1, "HID1",
3425
                 SPR_NOACCESS, SPR_NOACCESS,
3426
                 &spr_read_generic, &spr_write_generic,
3427
                 0x00000000);
3428
    /* XXX : not implemented */
3429
    spr_register(env, SPR_HID2, "HID2",
3430
                 SPR_NOACCESS, SPR_NOACCESS,
3431
                 &spr_read_generic, &spr_write_generic,
3432
                 0x00000000);
3433
    /* Memory management */
3434
    gen_low_BATs(env);
3435
    gen_high_BATs(env);
3436
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3437
    init_excp_G2(env);
3438
    env->dcache_line_size = 32;
3439
    env->icache_line_size = 32;
3440
    /* Allocate hardware IRQ controller */
3441
    ppc6xx_irq_init(env);
3442
}
3443

    
3444
/* PowerPC 604                                                               */
3445
#define POWERPC_INSNS_604    (POWERPC_INSNS_WORKS | PPC_EXTERN)
3446
#define POWERPC_MSRM_604     (0x000000000005FF77ULL)
3447
#define POWERPC_MMU_604      (POWERPC_MMU_32B)
3448
//#define POWERPC_EXCP_604     (POWERPC_EXCP_604)
3449
#define POWERPC_INPUT_604    (PPC_FLAGS_INPUT_6xx)
3450
#define POWERPC_BFDM_604     (bfd_mach_ppc_604)
3451
#define POWERPC_FLAG_604     (POWERPC_FLAG_NONE)
3452

    
3453
static void init_proc_604 (CPUPPCState *env)
3454
{
3455
    gen_spr_ne_601(env);
3456
    gen_spr_604(env);
3457
    /* Time base */
3458
    gen_tbl(env);
3459
    /* Hardware implementation registers */
3460
    /* XXX : not implemented */
3461
    spr_register(env, SPR_HID0, "HID0",
3462
                 SPR_NOACCESS, SPR_NOACCESS,
3463
                 &spr_read_generic, &spr_write_generic,
3464
                 0x00000000);
3465
    /* XXX : not implemented */
3466
    spr_register(env, SPR_HID1, "HID1",
3467
                 SPR_NOACCESS, SPR_NOACCESS,
3468
                 &spr_read_generic, &spr_write_generic,
3469
                 0x00000000);
3470
    /* Memory management */
3471
    gen_low_BATs(env);
3472
    init_excp_604(env);
3473
    env->dcache_line_size = 32;
3474
    env->icache_line_size = 32;
3475
    /* Allocate hardware IRQ controller */
3476
    ppc6xx_irq_init(env);
3477
}
3478

    
3479
/* PowerPC 740/750 (aka G3)                                                  */
3480
#define POWERPC_INSNS_7x0    (POWERPC_INSNS_WORKS | PPC_EXTERN)
3481
#define POWERPC_MSRM_7x0     (0x000000000007FF77ULL)
3482
#define POWERPC_MMU_7x0      (POWERPC_MMU_32B)
3483
//#define POWERPC_EXCP_7x0     (POWERPC_EXCP_7x0)
3484
#define POWERPC_INPUT_7x0    (PPC_FLAGS_INPUT_6xx)
3485
#define POWERPC_BFDM_7x0     (bfd_mach_ppc_750)
3486
#define POWERPC_FLAG_7x0     (POWERPC_FLAG_NONE)
3487

    
3488
static void init_proc_7x0 (CPUPPCState *env)
3489
{
3490
    gen_spr_ne_601(env);
3491
    gen_spr_7xx(env);
3492
    /* Time base */
3493
    gen_tbl(env);
3494
    /* Thermal management */
3495
    gen_spr_thrm(env);
3496
    /* Hardware implementation registers */
3497
    /* XXX : not implemented */
3498
    spr_register(env, SPR_HID0, "HID0",
3499
                 SPR_NOACCESS, SPR_NOACCESS,
3500
                 &spr_read_generic, &spr_write_generic,
3501
                 0x00000000);
3502
    /* XXX : not implemented */
3503
    spr_register(env, SPR_HID1, "HID1",
3504
                 SPR_NOACCESS, SPR_NOACCESS,
3505
                 &spr_read_generic, &spr_write_generic,
3506
                 0x00000000);
3507
    /* Memory management */
3508
    gen_low_BATs(env);
3509
    init_excp_7x0(env);
3510
    env->dcache_line_size = 32;
3511
    env->icache_line_size = 32;
3512
    /* Allocate hardware IRQ controller */
3513
    ppc6xx_irq_init(env);
3514
}
3515

    
3516
/* PowerPC 750FX/GX                                                          */
3517
#define POWERPC_INSNS_750fx  (POWERPC_INSNS_WORKS | PPC_EXTERN)
3518
#define POWERPC_MSRM_750fx   (0x000000000007FF77ULL)
3519
#define POWERPC_MMU_750fx    (POWERPC_MMU_32B)
3520
#define POWERPC_EXCP_750fx   (POWERPC_EXCP_7x0)
3521
#define POWERPC_INPUT_750fx  (PPC_FLAGS_INPUT_6xx)
3522
#define POWERPC_BFDM_750fx   (bfd_mach_ppc_750)
3523
#define POWERPC_FLAG_750fx   (POWERPC_FLAG_NONE)
3524

    
3525
static void init_proc_750fx (CPUPPCState *env)
3526
{
3527
    gen_spr_ne_601(env);
3528
    gen_spr_7xx(env);
3529
    /* Time base */
3530
    gen_tbl(env);
3531
    /* Thermal management */
3532
    gen_spr_thrm(env);
3533
    /* Hardware implementation registers */
3534
    /* XXX : not implemented */
3535
    spr_register(env, SPR_HID0, "HID0",
3536
                 SPR_NOACCESS, SPR_NOACCESS,
3537
                 &spr_read_generic, &spr_write_generic,
3538
                 0x00000000);
3539
    /* XXX : not implemented */
3540
    spr_register(env, SPR_HID1, "HID1",
3541
                 SPR_NOACCESS, SPR_NOACCESS,
3542
                 &spr_read_generic, &spr_write_generic,
3543
                 0x00000000);
3544
    /* XXX : not implemented */
3545
    spr_register(env, SPR_750_HID2, "HID2",
3546
                 SPR_NOACCESS, SPR_NOACCESS,
3547
                 &spr_read_generic, &spr_write_generic,
3548
                 0x00000000);
3549
    /* Memory management */
3550
    gen_low_BATs(env);
3551
    /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3552
    gen_high_BATs(env);
3553
    init_excp_750FX(env);
3554
    env->dcache_line_size = 32;
3555
    env->icache_line_size = 32;
3556
    /* Allocate hardware IRQ controller */
3557
    ppc6xx_irq_init(env);
3558
}
3559

    
3560
/* PowerPC 745/755                                                           */
3561
#define POWERPC_INSNS_7x5    (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3562
#define POWERPC_MSRM_7x5     (0x000000000007FF77ULL)
3563
#define POWERPC_MMU_7x5      (POWERPC_MMU_SOFT_6xx)
3564
//#define POWERPC_EXCP_7x5     (POWERPC_EXCP_7x5)
3565
#define POWERPC_INPUT_7x5    (PPC_FLAGS_INPUT_6xx)
3566
#define POWERPC_BFDM_7x5     (bfd_mach_ppc_750)
3567
#define POWERPC_FLAG_7x5     (POWERPC_FLAG_NONE)
3568

    
3569
static void init_proc_7x5 (CPUPPCState *env)
3570
{
3571
    gen_spr_ne_601(env);
3572
    gen_spr_G2_755(env);
3573
    /* Time base */
3574
    gen_tbl(env);
3575
    /* L2 cache control */
3576
    /* XXX : not implemented */
3577
    spr_register(env, SPR_ICTC, "ICTC",
3578
                 SPR_NOACCESS, SPR_NOACCESS,
3579
                 &spr_read_generic, &spr_write_generic,
3580
                 0x00000000);
3581
    /* XXX : not implemented */
3582
    spr_register(env, SPR_L2PMCR, "L2PMCR",
3583
                 SPR_NOACCESS, SPR_NOACCESS,
3584
                 &spr_read_generic, &spr_write_generic,
3585
                 0x00000000);
3586
    /* Hardware implementation registers */
3587
    /* XXX : not implemented */
3588
    spr_register(env, SPR_HID0, "HID0",
3589
                 SPR_NOACCESS, SPR_NOACCESS,
3590
                 &spr_read_generic, &spr_write_generic,
3591
                 0x00000000);
3592
    /* XXX : not implemented */
3593
    spr_register(env, SPR_HID1, "HID1",
3594
                 SPR_NOACCESS, SPR_NOACCESS,
3595
                 &spr_read_generic, &spr_write_generic,
3596
                 0x00000000);
3597
    /* XXX : not implemented */
3598
    spr_register(env, SPR_HID2, "HID2",
3599
                 SPR_NOACCESS, SPR_NOACCESS,
3600
                 &spr_read_generic, &spr_write_generic,
3601
                 0x00000000);
3602
    /* Memory management */
3603
    gen_low_BATs(env);
3604
    gen_high_BATs(env);
3605
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3606
    init_excp_7x5(env);
3607
    env->dcache_line_size = 32;
3608
    env->icache_line_size = 32;
3609
    /* Allocate hardware IRQ controller */
3610
    ppc6xx_irq_init(env);
3611
#if !defined(CONFIG_USER_ONLY)
3612
    /* Hardware reset vector */
3613
    env->hreset_vector = 0xFFFFFFFCUL;
3614
#endif
3615
}
3616

    
3617
/* PowerPC 7400 (aka G4)                                                     */
3618
#define POWERPC_INSNS_7400   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3619
                              PPC_EXTERN | PPC_MEM_TLBIA |                    \
3620
                              PPC_ALTIVEC)
3621
#define POWERPC_MSRM_7400    (0x000000000205FF77ULL)
3622
#define POWERPC_MMU_7400     (POWERPC_MMU_32B)
3623
#define POWERPC_EXCP_7400    (POWERPC_EXCP_74xx)
3624
#define POWERPC_INPUT_7400   (PPC_FLAGS_INPUT_6xx)
3625
#define POWERPC_BFDM_7400    (bfd_mach_ppc_7400)
3626
#define POWERPC_FLAG_7400    (POWERPC_FLAG_VRE)
3627

    
3628
static void init_proc_7400 (CPUPPCState *env)
3629
{
3630
    gen_spr_ne_601(env);
3631
    gen_spr_7xx(env);
3632
    /* Time base */
3633
    gen_tbl(env);
3634
    /* 74xx specific SPR */
3635
    gen_spr_74xx(env);
3636
    /* Thermal management */
3637
    gen_spr_thrm(env);
3638
    /* Memory management */
3639
    gen_low_BATs(env);
3640
    init_excp_7400(env);
3641
    env->dcache_line_size = 32;
3642
    env->icache_line_size = 32;
3643
    /* Allocate hardware IRQ controller */
3644
    ppc6xx_irq_init(env);
3645
}
3646

    
3647
/* PowerPC 7410 (aka G4)                                                     */
3648
#define POWERPC_INSNS_7410   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3649
                              PPC_EXTERN | PPC_MEM_TLBIA |                    \
3650
                              PPC_ALTIVEC)
3651
#define POWERPC_MSRM_7410    (0x000000000205FF77ULL)
3652
#define POWERPC_MMU_7410     (POWERPC_MMU_32B)
3653
#define POWERPC_EXCP_7410    (POWERPC_EXCP_74xx)
3654
#define POWERPC_INPUT_7410   (PPC_FLAGS_INPUT_6xx)
3655
#define POWERPC_BFDM_7410    (bfd_mach_ppc_7400)
3656
#define POWERPC_FLAG_7410    (POWERPC_FLAG_VRE)
3657

    
3658
static void init_proc_7410 (CPUPPCState *env)
3659
{
3660
    gen_spr_ne_601(env);
3661
    gen_spr_7xx(env);
3662
    /* Time base */
3663
    gen_tbl(env);
3664
    /* 74xx specific SPR */
3665
    gen_spr_74xx(env);
3666
    /* Thermal management */
3667
    gen_spr_thrm(env);
3668
    /* L2PMCR */
3669
    /* XXX : not implemented */
3670
    spr_register(env, SPR_L2PMCR, "L2PMCR",
3671
                 SPR_NOACCESS, SPR_NOACCESS,
3672
                 &spr_read_generic, &spr_write_generic,
3673
                 0x00000000);
3674
    /* LDSTDB */
3675
    /* XXX : not implemented */
3676
    spr_register(env, SPR_LDSTDB, "LDSTDB",
3677
                 SPR_NOACCESS, SPR_NOACCESS,
3678
                 &spr_read_generic, &spr_write_generic,
3679
                 0x00000000);
3680
    /* Memory management */
3681
    gen_low_BATs(env);
3682
    init_excp_7400(env);
3683
    env->dcache_line_size = 32;
3684
    env->icache_line_size = 32;
3685
    /* Allocate hardware IRQ controller */
3686
    ppc6xx_irq_init(env);
3687
}
3688

    
3689
/* PowerPC 7440 (aka G4)                                                     */
3690
#define POWERPC_INSNS_7440   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3691
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3692
                              PPC_ALTIVEC)
3693
#define POWERPC_MSRM_7440    (0x000000000205FF77ULL)
3694
#define POWERPC_MMU_7440     (POWERPC_MMU_SOFT_74xx)
3695
#define POWERPC_EXCP_7440    (POWERPC_EXCP_74xx)
3696
#define POWERPC_INPUT_7440   (PPC_FLAGS_INPUT_6xx)
3697
#define POWERPC_BFDM_7440    (bfd_mach_ppc_7400)
3698
#define POWERPC_FLAG_7440    (POWERPC_FLAG_VRE)
3699

    
3700
__attribute__ (( unused ))
3701
static void init_proc_7440 (CPUPPCState *env)
3702
{
3703
    gen_spr_ne_601(env);
3704
    gen_spr_7xx(env);
3705
    /* Time base */
3706
    gen_tbl(env);
3707
    /* 74xx specific SPR */
3708
    gen_spr_74xx(env);
3709
    /* LDSTCR */
3710
    /* XXX : not implemented */
3711
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3712
                 SPR_NOACCESS, SPR_NOACCESS,
3713
                 &spr_read_generic, &spr_write_generic,
3714
                 0x00000000);
3715
    /* ICTRL */
3716
    /* XXX : not implemented */
3717
    spr_register(env, SPR_ICTRL, "ICTRL",
3718
                 SPR_NOACCESS, SPR_NOACCESS,
3719
                 &spr_read_generic, &spr_write_generic,
3720
                 0x00000000);
3721
    /* MSSSR0 */
3722
    /* XXX : not implemented */
3723
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3724
                 SPR_NOACCESS, SPR_NOACCESS,
3725
                 &spr_read_generic, &spr_write_generic,
3726
                 0x00000000);
3727
    /* PMC */
3728
    /* XXX : not implemented */
3729
    spr_register(env, SPR_PMC5, "PMC5",
3730
                 SPR_NOACCESS, SPR_NOACCESS,
3731
                 &spr_read_generic, &spr_write_generic,
3732
                 0x00000000);
3733
    /* XXX : not implemented */
3734
    spr_register(env, SPR_UPMC5, "UPMC5",
3735
                 &spr_read_ureg, SPR_NOACCESS,
3736
                 &spr_read_ureg, SPR_NOACCESS,
3737
                 0x00000000);
3738
    /* XXX : not implemented */
3739
    spr_register(env, SPR_PMC6, "PMC6",
3740
                 SPR_NOACCESS, SPR_NOACCESS,
3741
                 &spr_read_generic, &spr_write_generic,
3742
                 0x00000000);
3743
    /* XXX : not implemented */
3744
    spr_register(env, SPR_UPMC6, "UPMC6",
3745
                 &spr_read_ureg, SPR_NOACCESS,
3746
                 &spr_read_ureg, SPR_NOACCESS,
3747
                 0x00000000);
3748
    /* Memory management */
3749
    gen_low_BATs(env);
3750
    gen_74xx_soft_tlb(env, 128, 2);
3751
    init_excp_7450(env);
3752
    env->dcache_line_size = 32;
3753
    env->icache_line_size = 32;
3754
    /* Allocate hardware IRQ controller */
3755
    ppc6xx_irq_init(env);
3756
}
3757

    
3758
/* PowerPC 7450 (aka G4)                                                     */
3759
#define POWERPC_INSNS_7450   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3760
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3761
                              PPC_ALTIVEC)
3762
#define POWERPC_MSRM_7450    (0x000000000205FF77ULL)
3763
#define POWERPC_MMU_7450     (POWERPC_MMU_SOFT_74xx)
3764
#define POWERPC_EXCP_7450    (POWERPC_EXCP_74xx)
3765
#define POWERPC_INPUT_7450   (PPC_FLAGS_INPUT_6xx)
3766
#define POWERPC_BFDM_7450    (bfd_mach_ppc_7400)
3767
#define POWERPC_FLAG_7450    (POWERPC_FLAG_VRE)
3768

    
3769
__attribute__ (( unused ))
3770
static void init_proc_7450 (CPUPPCState *env)
3771
{
3772
    gen_spr_ne_601(env);
3773
    gen_spr_7xx(env);
3774
    /* Time base */
3775
    gen_tbl(env);
3776
    /* 74xx specific SPR */
3777
    gen_spr_74xx(env);
3778
    /* Level 3 cache control */
3779
    gen_l3_ctrl(env);
3780
    /* LDSTCR */
3781
    /* XXX : not implemented */
3782
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3783
                 SPR_NOACCESS, SPR_NOACCESS,
3784
                 &spr_read_generic, &spr_write_generic,
3785
                 0x00000000);
3786
    /* ICTRL */
3787
    /* XXX : not implemented */
3788
    spr_register(env, SPR_ICTRL, "ICTRL",
3789
                 SPR_NOACCESS, SPR_NOACCESS,
3790
                 &spr_read_generic, &spr_write_generic,
3791
                 0x00000000);
3792
    /* MSSSR0 */
3793
    /* XXX : not implemented */
3794
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3795
                 SPR_NOACCESS, SPR_NOACCESS,
3796
                 &spr_read_generic, &spr_write_generic,
3797
                 0x00000000);
3798
    /* PMC */
3799
    /* XXX : not implemented */
3800
    spr_register(env, SPR_PMC5, "PMC5",
3801
                 SPR_NOACCESS, SPR_NOACCESS,
3802
                 &spr_read_generic, &spr_write_generic,
3803
                 0x00000000);
3804
    /* XXX : not implemented */
3805
    spr_register(env, SPR_UPMC5, "UPMC5",
3806
                 &spr_read_ureg, SPR_NOACCESS,
3807
                 &spr_read_ureg, SPR_NOACCESS,
3808
                 0x00000000);
3809
    /* XXX : not implemented */
3810
    spr_register(env, SPR_PMC6, "PMC6",
3811
                 SPR_NOACCESS, SPR_NOACCESS,
3812
                 &spr_read_generic, &spr_write_generic,
3813
                 0x00000000);
3814
    /* XXX : not implemented */
3815
    spr_register(env, SPR_UPMC6, "UPMC6",
3816
                 &spr_read_ureg, SPR_NOACCESS,
3817
                 &spr_read_ureg, SPR_NOACCESS,
3818
                 0x00000000);
3819
    /* Memory management */
3820
    gen_low_BATs(env);
3821
    gen_74xx_soft_tlb(env, 128, 2);
3822
    init_excp_7450(env);
3823
    env->dcache_line_size = 32;
3824
    env->icache_line_size = 32;
3825
    /* Allocate hardware IRQ controller */
3826
    ppc6xx_irq_init(env);
3827
}
3828

    
3829
/* PowerPC 7445 (aka G4)                                                     */
3830
#define POWERPC_INSNS_7445   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3831
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3832
                              PPC_ALTIVEC)
3833
#define POWERPC_MSRM_7445    (0x000000000205FF77ULL)
3834
#define POWERPC_MMU_7445     (POWERPC_MMU_SOFT_74xx)
3835
#define POWERPC_EXCP_7445    (POWERPC_EXCP_74xx)
3836
#define POWERPC_INPUT_7445   (PPC_FLAGS_INPUT_6xx)
3837
#define POWERPC_BFDM_7445    (bfd_mach_ppc_7400)
3838
#define POWERPC_FLAG_7445    (POWERPC_FLAG_VRE)
3839

    
3840
__attribute__ (( unused ))
3841
static void init_proc_7445 (CPUPPCState *env)
3842
{
3843
    gen_spr_ne_601(env);
3844
    gen_spr_7xx(env);
3845
    /* Time base */
3846
    gen_tbl(env);
3847
    /* 74xx specific SPR */
3848
    gen_spr_74xx(env);
3849
    /* LDSTCR */
3850
    /* XXX : not implemented */
3851
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3852
                 SPR_NOACCESS, SPR_NOACCESS,
3853
                 &spr_read_generic, &spr_write_generic,
3854
                 0x00000000);
3855
    /* ICTRL */
3856
    /* XXX : not implemented */
3857
    spr_register(env, SPR_ICTRL, "ICTRL",
3858
                 SPR_NOACCESS, SPR_NOACCESS,
3859
                 &spr_read_generic, &spr_write_generic,
3860
                 0x00000000);
3861
    /* MSSSR0 */
3862
    /* XXX : not implemented */
3863
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3864
                 SPR_NOACCESS, SPR_NOACCESS,
3865
                 &spr_read_generic, &spr_write_generic,
3866
                 0x00000000);
3867
    /* PMC */
3868
    /* XXX : not implemented */
3869
    spr_register(env, SPR_PMC5, "PMC5",
3870
                 SPR_NOACCESS, SPR_NOACCESS,
3871
                 &spr_read_generic, &spr_write_generic,
3872
                 0x00000000);
3873
    /* XXX : not implemented */
3874
    spr_register(env, SPR_UPMC5, "UPMC5",
3875
                 &spr_read_ureg, SPR_NOACCESS,
3876
                 &spr_read_ureg, SPR_NOACCESS,
3877
                 0x00000000);
3878
    /* XXX : not implemented */
3879
    spr_register(env, SPR_PMC6, "PMC6",
3880
                 SPR_NOACCESS, SPR_NOACCESS,
3881
                 &spr_read_generic, &spr_write_generic,
3882
                 0x00000000);
3883
    /* XXX : not implemented */
3884
    spr_register(env, SPR_UPMC6, "UPMC6",
3885
                 &spr_read_ureg, SPR_NOACCESS,
3886
                 &spr_read_ureg, SPR_NOACCESS,
3887
                 0x00000000);
3888
    /* SPRGs */
3889
    spr_register(env, SPR_SPRG4, "SPRG4",
3890
                 SPR_NOACCESS, SPR_NOACCESS,
3891
                 &spr_read_generic, &spr_write_generic,
3892
                 0x00000000);
3893
    spr_register(env, SPR_USPRG4, "USPRG4",
3894
                 &spr_read_ureg, SPR_NOACCESS,
3895
                 &spr_read_ureg, SPR_NOACCESS,
3896
                 0x00000000);
3897
    spr_register(env, SPR_SPRG5, "SPRG5",
3898
                 SPR_NOACCESS, SPR_NOACCESS,
3899
                 &spr_read_generic, &spr_write_generic,
3900
                 0x00000000);
3901
    spr_register(env, SPR_USPRG5, "USPRG5",
3902
                 &spr_read_ureg, SPR_NOACCESS,
3903
                 &spr_read_ureg, SPR_NOACCESS,
3904
                 0x00000000);
3905
    spr_register(env, SPR_SPRG6, "SPRG6",
3906
                 SPR_NOACCESS, SPR_NOACCESS,
3907
                 &spr_read_generic, &spr_write_generic,
3908
                 0x00000000);
3909
    spr_register(env, SPR_USPRG6, "USPRG6",
3910
                 &spr_read_ureg, SPR_NOACCESS,
3911
                 &spr_read_ureg, SPR_NOACCESS,
3912
                 0x00000000);
3913
    spr_register(env, SPR_SPRG7, "SPRG7",
3914
                 SPR_NOACCESS, SPR_NOACCESS,
3915
                 &spr_read_generic, &spr_write_generic,
3916
                 0x00000000);
3917
    spr_register(env, SPR_USPRG7, "USPRG7",
3918
                 &spr_read_ureg, SPR_NOACCESS,
3919
                 &spr_read_ureg, SPR_NOACCESS,
3920
                 0x00000000);
3921
    /* Memory management */
3922
    gen_low_BATs(env);
3923
    gen_high_BATs(env);
3924
    gen_74xx_soft_tlb(env, 128, 2);
3925
    init_excp_7450(env);
3926
    env->dcache_line_size = 32;
3927
    env->icache_line_size = 32;
3928
    /* Allocate hardware IRQ controller */
3929
    ppc6xx_irq_init(env);
3930
}
3931

    
3932
/* PowerPC 7455 (aka G4)                                                     */
3933
#define POWERPC_INSNS_7455   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3934
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3935
                              PPC_ALTIVEC)
3936
#define POWERPC_MSRM_7455    (0x000000000205FF77ULL)
3937
#define POWERPC_MMU_7455     (POWERPC_MMU_SOFT_74xx)
3938
#define POWERPC_EXCP_7455    (POWERPC_EXCP_74xx)
3939
#define POWERPC_INPUT_7455   (PPC_FLAGS_INPUT_6xx)
3940
#define POWERPC_BFDM_7455    (bfd_mach_ppc_7400)
3941
#define POWERPC_FLAG_7455    (POWERPC_FLAG_VRE)
3942

    
3943
__attribute__ (( unused ))
3944
static void init_proc_7455 (CPUPPCState *env)
3945
{
3946
    gen_spr_ne_601(env);
3947
    gen_spr_7xx(env);
3948
    /* Time base */
3949
    gen_tbl(env);
3950
    /* 74xx specific SPR */
3951
    gen_spr_74xx(env);
3952
    /* Level 3 cache control */
3953
    gen_l3_ctrl(env);
3954
    /* LDSTCR */
3955
    /* XXX : not implemented */
3956
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3957
                 SPR_NOACCESS, SPR_NOACCESS,
3958
                 &spr_read_generic, &spr_write_generic,
3959
                 0x00000000);
3960
    /* ICTRL */
3961
    /* XXX : not implemented */
3962
    spr_register(env, SPR_ICTRL, "ICTRL",
3963
                 SPR_NOACCESS, SPR_NOACCESS,
3964
                 &spr_read_generic, &spr_write_generic,
3965
                 0x00000000);
3966
    /* MSSSR0 */
3967
    /* XXX : not implemented */
3968
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3969
                 SPR_NOACCESS, SPR_NOACCESS,
3970
                 &spr_read_generic, &spr_write_generic,
3971
                 0x00000000);
3972
    /* PMC */
3973
    /* XXX : not implemented */
3974
    spr_register(env, SPR_PMC5, "PMC5",
3975
                 SPR_NOACCESS, SPR_NOACCESS,
3976
                 &spr_read_generic, &spr_write_generic,
3977
                 0x00000000);
3978
    /* XXX : not implemented */
3979
    spr_register(env, SPR_UPMC5, "UPMC5",
3980
                 &spr_read_ureg, SPR_NOACCESS,
3981
                 &spr_read_ureg, SPR_NOACCESS,
3982
                 0x00000000);
3983
    /* XXX : not implemented */
3984
    spr_register(env, SPR_PMC6, "PMC6",
3985
                 SPR_NOACCESS, SPR_NOACCESS,
3986
                 &spr_read_generic, &spr_write_generic,
3987
                 0x00000000);
3988
    /* XXX : not implemented */
3989
    spr_register(env, SPR_UPMC6, "UPMC6",
3990
                 &spr_read_ureg, SPR_NOACCESS,
3991
                 &spr_read_ureg, SPR_NOACCESS,
3992
                 0x00000000);
3993
    /* SPRGs */
3994
    spr_register(env, SPR_SPRG4, "SPRG4",
3995
                 SPR_NOACCESS, SPR_NOACCESS,
3996
                 &spr_read_generic, &spr_write_generic,
3997
                 0x00000000);
3998
    spr_register(env, SPR_USPRG4, "USPRG4",
3999
                 &spr_read_ureg, SPR_NOACCESS,
4000
                 &spr_read_ureg, SPR_NOACCESS,
4001
                 0x00000000);
4002
    spr_register(env, SPR_SPRG5, "SPRG5",
4003
                 SPR_NOACCESS, SPR_NOACCESS,
4004
                 &spr_read_generic, &spr_write_generic,
4005
                 0x00000000);
4006
    spr_register(env, SPR_USPRG5, "USPRG5",
4007
                 &spr_read_ureg, SPR_NOACCESS,
4008
                 &spr_read_ureg, SPR_NOACCESS,
4009
                 0x00000000);
4010
    spr_register(env, SPR_SPRG6, "SPRG6",
4011
                 SPR_NOACCESS, SPR_NOACCESS,
4012
                 &spr_read_generic, &spr_write_generic,
4013
                 0x00000000);
4014
    spr_register(env, SPR_USPRG6, "USPRG6",
4015
                 &spr_read_ureg, SPR_NOACCESS,
4016
                 &spr_read_ureg, SPR_NOACCESS,
4017
                 0x00000000);
4018
    spr_register(env, SPR_SPRG7, "SPRG7",
4019
                 SPR_NOACCESS, SPR_NOACCESS,
4020
                 &spr_read_generic, &spr_write_generic,
4021
                 0x00000000);
4022
    spr_register(env, SPR_USPRG7, "USPRG7",
4023
                 &spr_read_ureg, SPR_NOACCESS,
4024
                 &spr_read_ureg, SPR_NOACCESS,
4025
                 0x00000000);
4026
    /* Memory management */
4027
    gen_low_BATs(env);
4028
    gen_high_BATs(env);
4029
    gen_74xx_soft_tlb(env, 128, 2);
4030
    init_excp_7450(env);
4031
    env->dcache_line_size = 32;
4032
    env->icache_line_size = 32;
4033
    /* Allocate hardware IRQ controller */
4034
    ppc6xx_irq_init(env);
4035
}
4036

    
4037
#if defined (TARGET_PPC64)
4038
#define POWERPC_INSNS_WORK64  (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT |          \
4039
                               PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |           \
4040
                               PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX |            \
4041
                               PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
4042
/* PowerPC 970                                                               */
4043
#define POWERPC_INSNS_970    (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT |        \
4044
                              PPC_64B | PPC_ALTIVEC |                         \
4045
                              PPC_SEGMENT_64B | PPC_SLBI)
4046
#define POWERPC_MSRM_970     (0x900000000204FF36ULL)
4047
#define POWERPC_MMU_970      (POWERPC_MMU_64B)
4048
//#define POWERPC_EXCP_970     (POWERPC_EXCP_970)
4049
#define POWERPC_INPUT_970    (PPC_FLAGS_INPUT_970)
4050
#define POWERPC_BFDM_970     (bfd_mach_ppc64)
4051
#define POWERPC_FLAG_970     (POWERPC_FLAG_VRE)
4052

    
4053
#if defined(CONFIG_USER_ONLY)
4054
#define POWERPC970_HID5_INIT 0x00000080
4055
#else
4056
#define POWERPC970_HID5_INIT 0x00000000
4057
#endif
4058

    
4059
static void init_proc_970 (CPUPPCState *env)
4060
{
4061
    gen_spr_ne_601(env);
4062
    gen_spr_7xx(env);
4063
    /* Time base */
4064
    gen_tbl(env);
4065
    /* Hardware implementation registers */
4066
    /* XXX : not implemented */
4067
    spr_register(env, SPR_HID0, "HID0",
4068
                 SPR_NOACCESS, SPR_NOACCESS,
4069
                 &spr_read_generic, &spr_write_clear,
4070
                 0x60000000);
4071
    /* XXX : not implemented */
4072
    spr_register(env, SPR_HID1, "HID1",
4073
                 SPR_NOACCESS, SPR_NOACCESS,
4074
                 &spr_read_generic, &spr_write_generic,
4075
                 0x00000000);
4076
    /* XXX : not implemented */
4077
    spr_register(env, SPR_750_HID2, "HID2",
4078
                 SPR_NOACCESS, SPR_NOACCESS,
4079
                 &spr_read_generic, &spr_write_generic,
4080
                 0x00000000);
4081
    /* XXX : not implemented */
4082
    spr_register(env, SPR_970_HID5, "HID5",
4083
                 SPR_NOACCESS, SPR_NOACCESS,
4084
                 &spr_read_generic, &spr_write_generic,
4085
                 POWERPC970_HID5_INIT);
4086
    /* Memory management */
4087
    /* XXX: not correct */
4088
    gen_low_BATs(env);
4089
    /* XXX : not implemented */
4090
    spr_register(env, SPR_MMUCFG, "MMUCFG",
4091
                 SPR_NOACCESS, SPR_NOACCESS,
4092
                 &spr_read_generic, SPR_NOACCESS,
4093
                 0x00000000); /* TOFIX */
4094
    /* XXX : not implemented */
4095
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4096
                 SPR_NOACCESS, SPR_NOACCESS,
4097
                 &spr_read_generic, &spr_write_generic,
4098
                 0x00000000); /* TOFIX */
4099
    spr_register(env, SPR_HIOR, "SPR_HIOR",
4100
                 SPR_NOACCESS, SPR_NOACCESS,
4101
                 &spr_read_generic, &spr_write_generic,
4102
                 0xFFF00000); /* XXX: This is a hack */
4103
#if !defined(CONFIG_USER_ONLY)
4104
    env->excp_prefix = 0xFFF00000;
4105
#endif
4106
#if !defined(CONFIG_USER_ONLY)
4107
    env->slb_nr = 32;
4108
#endif
4109
    init_excp_970(env);
4110
    env->dcache_line_size = 128;
4111
    env->icache_line_size = 128;
4112
    /* Allocate hardware IRQ controller */
4113
    ppc970_irq_init(env);
4114
}
4115

    
4116
/* PowerPC 970FX (aka G5)                                                    */
4117
#define POWERPC_INSNS_970FX  (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT |        \
4118
                              PPC_64B | PPC_ALTIVEC |                         \
4119
                              PPC_SEGMENT_64B | PPC_SLBI)
4120
#define POWERPC_MSRM_970FX   (0x800000000204FF36ULL)
4121
#define POWERPC_MMU_970FX    (POWERPC_MMU_64B)
4122
#define POWERPC_EXCP_970FX   (POWERPC_EXCP_970)
4123
#define POWERPC_INPUT_970FX  (PPC_FLAGS_INPUT_970)
4124
#define POWERPC_BFDM_970FX   (bfd_mach_ppc64)
4125
#define POWERPC_FLAG_970FX   (POWERPC_FLAG_VRE)
4126

    
4127
static void init_proc_970FX (CPUPPCState *env)
4128
{
4129
    gen_spr_ne_601(env);
4130
    gen_spr_7xx(env);
4131
    /* Time base */
4132
    gen_tbl(env);
4133
    /* Hardware implementation registers */
4134
    /* XXX : not implemented */
4135
    spr_register(env, SPR_HID0, "HID0",
4136
                 SPR_NOACCESS, SPR_NOACCESS,
4137
                 &spr_read_generic, &spr_write_clear,
4138
                 0x60000000);
4139
    /* XXX : not implemented */
4140
    spr_register(env, SPR_HID1, "HID1",
4141
                 SPR_NOACCESS, SPR_NOACCESS,
4142
                 &spr_read_generic, &spr_write_generic,
4143
                 0x00000000);
4144
    /* XXX : not implemented */
4145
    spr_register(env, SPR_750_HID2, "HID2",
4146
                 SPR_NOACCESS, SPR_NOACCESS,
4147
                 &spr_read_generic, &spr_write_generic,
4148
                 0x00000000);
4149
    /* XXX : not implemented */
4150
    spr_register(env, SPR_970_HID5, "HID5",
4151
                 SPR_NOACCESS, SPR_NOACCESS,
4152
                 &spr_read_generic, &spr_write_generic,
4153
                 POWERPC970_HID5_INIT);
4154
    /* Memory management */
4155
    /* XXX: not correct */
4156
    gen_low_BATs(env);
4157
    /* XXX : not implemented */
4158
    spr_register(env, SPR_MMUCFG, "MMUCFG",
4159
                 SPR_NOACCESS, SPR_NOACCESS,
4160
                 &spr_read_generic, SPR_NOACCESS,
4161
                 0x00000000); /* TOFIX */
4162
    /* XXX : not implemented */
4163
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4164
                 SPR_NOACCESS, SPR_NOACCESS,
4165
                 &spr_read_generic, &spr_write_generic,
4166
                 0x00000000); /* TOFIX */
4167
    spr_register(env, SPR_HIOR, "SPR_HIOR",
4168
                 SPR_NOACCESS, SPR_NOACCESS,
4169
                 &spr_read_generic, &spr_write_generic,
4170
                 0xFFF00000); /* XXX: This is a hack */
4171
#if !defined(CONFIG_USER_ONLY)
4172
    env->excp_prefix = 0xFFF00000;
4173
#endif
4174
#if !defined(CONFIG_USER_ONLY)
4175
    env->slb_nr = 32;
4176
#endif
4177
    init_excp_970(env);
4178
    env->dcache_line_size = 128;
4179
    env->icache_line_size = 128;
4180
    /* Allocate hardware IRQ controller */
4181
    ppc970_irq_init(env);
4182
}
4183

    
4184
/* PowerPC 970 GX                                                            */
4185
#define POWERPC_INSNS_970GX  (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT |        \
4186
                              PPC_64B | PPC_ALTIVEC |                         \
4187
                              PPC_SEGMENT_64B | PPC_SLBI)
4188
#define POWERPC_MSRM_970GX   (0x800000000204FF36ULL)
4189
#define POWERPC_MMU_970GX    (POWERPC_MMU_64B)
4190
#define POWERPC_EXCP_970GX   (POWERPC_EXCP_970)
4191
#define POWERPC_INPUT_970GX  (PPC_FLAGS_INPUT_970)
4192
#define POWERPC_BFDM_970GX   (bfd_mach_ppc64)
4193
#define POWERPC_FLAG_970GX   (POWERPC_FLAG_VRE)
4194

    
4195
static void init_proc_970GX (CPUPPCState *env)
4196
{
4197
    gen_spr_ne_601(env);
4198
    gen_spr_7xx(env);
4199
    /* Time base */
4200
    gen_tbl(env);
4201
    /* Hardware implementation registers */
4202
    /* XXX : not implemented */
4203
    spr_register(env, SPR_HID0, "HID0",
4204
                 SPR_NOACCESS, SPR_NOACCESS,
4205
                 &spr_read_generic, &spr_write_clear,
4206
                 0x60000000);
4207
    /* XXX : not implemented */
4208
    spr_register(env, SPR_HID1, "HID1",
4209
                 SPR_NOACCESS, SPR_NOACCESS,
4210
                 &spr_read_generic, &spr_write_generic,
4211
                 0x00000000);
4212
    /* XXX : not implemented */
4213
    spr_register(env, SPR_750_HID2, "HID2",
4214
                 SPR_NOACCESS, SPR_NOACCESS,
4215
                 &spr_read_generic, &spr_write_generic,
4216
                 0x00000000);
4217
    /* XXX : not implemented */
4218
    spr_register(env, SPR_970_HID5, "HID5",
4219
                 SPR_NOACCESS, SPR_NOACCESS,
4220
                 &spr_read_generic, &spr_write_generic,
4221
                 POWERPC970_HID5_INIT);
4222
    /* Memory management */
4223
    /* XXX: not correct */
4224
    gen_low_BATs(env);
4225
    /* XXX : not implemented */
4226
    spr_register(env, SPR_MMUCFG, "MMUCFG",
4227
                 SPR_NOACCESS, SPR_NOACCESS,
4228
                 &spr_read_generic, SPR_NOACCESS,
4229
                 0x00000000); /* TOFIX */
4230
    /* XXX : not implemented */
4231
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4232
                 SPR_NOACCESS, SPR_NOACCESS,
4233
                 &spr_read_generic, &spr_write_generic,
4234
                 0x00000000); /* TOFIX */
4235
    spr_register(env, SPR_HIOR, "SPR_HIOR",
4236
                 SPR_NOACCESS, SPR_NOACCESS,
4237
                 &spr_read_generic, &spr_write_generic,
4238
                 0xFFF00000); /* XXX: This is a hack */
4239
#if !defined(CONFIG_USER_ONLY)
4240
    env->excp_prefix = 0xFFF00000;
4241
#endif
4242
#if !defined(CONFIG_USER_ONLY)
4243
    env->slb_nr = 32;
4244
#endif
4245
    init_excp_970(env);
4246
    env->dcache_line_size = 128;
4247
    env->icache_line_size = 128;
4248
    /* Allocate hardware IRQ controller */
4249
    ppc970_irq_init(env);
4250
}
4251

    
4252
/* PowerPC 620                                                               */
4253
#define POWERPC_INSNS_620    (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT |         \
4254
                              PPC_64B | PPC_SLBI)
4255
#define POWERPC_MSRM_620     (0x800000000005FF73ULL)
4256
#define POWERPC_MMU_620      (POWERPC_MMU_64B)
4257
#define POWERPC_EXCP_620     (POWERPC_EXCP_970)
4258
#define POWERPC_INPUT_620    (PPC_FLAGS_INPUT_970)
4259
#define POWERPC_BFDM_620     (bfd_mach_ppc64)
4260
#define POWERPC_FLAG_620     (POWERPC_FLAG_NONE)
4261

    
4262
__attribute__ (( unused ))
4263
static void init_proc_620 (CPUPPCState *env)
4264
{
4265
    gen_spr_ne_601(env);
4266
    gen_spr_620(env);
4267
    /* Time base */
4268
    gen_tbl(env);
4269
    /* Hardware implementation registers */
4270
    /* XXX : not implemented */
4271
    spr_register(env, SPR_HID0, "HID0",
4272
                 SPR_NOACCESS, SPR_NOACCESS,
4273
                 &spr_read_generic, &spr_write_generic,
4274
                 0x00000000);
4275
    /* Memory management */
4276
    gen_low_BATs(env);
4277
    gen_high_BATs(env);
4278
    init_excp_620(env);
4279
    env->dcache_line_size = 64;
4280
    env->icache_line_size = 64;
4281
    /* XXX: TODO: initialize internal interrupt controller */
4282
}
4283
#endif /* defined (TARGET_PPC64) */
4284

    
4285
/* Default 32 bits PowerPC target will be 604 */
4286
#define CPU_POWERPC_PPC32     CPU_POWERPC_604
4287
#define POWERPC_INSNS_PPC32   POWERPC_INSNS_604
4288
#define POWERPC_MSRM_PPC32    POWERPC_MSRM_604
4289
#define POWERPC_MMU_PPC32     POWERPC_MMU_604
4290
#define POWERPC_EXCP_PPC32    POWERPC_EXCP_604
4291
#define POWERPC_INPUT_PPC32   POWERPC_INPUT_604
4292
#define init_proc_PPC32       init_proc_604
4293
#define POWERPC_BFDM_PPC32    POWERPC_BFDM_604
4294
#define POWERPC_FLAG_PPC32    POWERPC_FLAG_604
4295

    
4296
/* Default 64 bits PowerPC target will be 970 FX */
4297
#define CPU_POWERPC_PPC64     CPU_POWERPC_970FX
4298
#define POWERPC_INSNS_PPC64   POWERPC_INSNS_970FX
4299
#define POWERPC_MSRM_PPC64    POWERPC_MSRM_970FX
4300
#define POWERPC_MMU_PPC64     POWERPC_MMU_970FX
4301
#define POWERPC_EXCP_PPC64    POWERPC_EXCP_970FX
4302
#define POWERPC_INPUT_PPC64   POWERPC_INPUT_970FX
4303
#define init_proc_PPC64       init_proc_970FX
4304
#define POWERPC_BFDM_PPC64    POWERPC_BFDM_970FX
4305
#define POWERPC_FLAG_PPC64    POWERPC_FLAG_970FX
4306

    
4307
/* Default PowerPC target will be PowerPC 32 */
4308
#if defined (TARGET_PPC64) && 0 // XXX: TODO
4309
#define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC64
4310
#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
4311
#define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC64
4312
#define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC64
4313
#define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC64
4314
#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
4315
#define init_proc_DEFAULT     init_proc_PPC64
4316
#define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC64
4317
#define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC64
4318
#else
4319
#define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC32
4320
#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
4321
#define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC32
4322
#define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC32
4323
#define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC32
4324
#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
4325
#define init_proc_DEFAULT     init_proc_PPC32
4326
#define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC32
4327
#define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC32
4328
#endif
4329

    
4330
/*****************************************************************************/
4331
/* PVR definitions for most known PowerPC                                    */
4332
enum {
4333
    /* PowerPC 401 family */
4334
    /* Generic PowerPC 401 */
4335
#define CPU_POWERPC_401       CPU_POWERPC_401G2
4336
    /* PowerPC 401 cores */
4337
    CPU_POWERPC_401A1       = 0x00210000,
4338
    CPU_POWERPC_401B2       = 0x00220000,
4339
#if 0
4340
    CPU_POWERPC_401B3       = xxx,
4341
#endif
4342
    CPU_POWERPC_401C2       = 0x00230000,
4343
    CPU_POWERPC_401D2       = 0x00240000,
4344
    CPU_POWERPC_401E2       = 0x00250000,
4345
    CPU_POWERPC_401F2       = 0x00260000,
4346
    CPU_POWERPC_401G2       = 0x00270000,
4347
    /* PowerPC 401 microcontrolers */
4348
#if 0
4349
    CPU_POWERPC_401GF       = xxx,
4350
#endif
4351
#define CPU_POWERPC_IOP480    CPU_POWERPC_401B2
4352
    /* IBM Processor for Network Resources */
4353
    CPU_POWERPC_COBRA       = 0x10100000, /* XXX: 405 ? */
4354
#if 0
4355
    CPU_POWERPC_XIPCHIP     = xxx,
4356
#endif
4357
    /* PowerPC 403 family */
4358
    /* Generic PowerPC 403 */
4359
#define CPU_POWERPC_403       CPU_POWERPC_403GC
4360
    /* PowerPC 403 microcontrollers */
4361
    CPU_POWERPC_403GA       = 0x00200011,
4362
    CPU_POWERPC_403GB       = 0x00200100,
4363
    CPU_POWERPC_403GC       = 0x00200200,
4364
    CPU_POWERPC_403GCX      = 0x00201400,
4365
#if 0
4366
    CPU_POWERPC_403GP       = xxx,
4367
#endif
4368
    /* PowerPC 405 family */
4369
    /* Generic PowerPC 405 */
4370
#define CPU_POWERPC_405       CPU_POWERPC_405D4
4371
    /* PowerPC 405 cores */
4372
#if 0
4373
    CPU_POWERPC_405A3       = xxx,
4374
#endif
4375
#if 0
4376
    CPU_POWERPC_405A4       = xxx,
4377
#endif
4378
#if 0
4379
    CPU_POWERPC_405B3       = xxx,
4380
#endif
4381
#if 0
4382
    CPU_POWERPC_405B4       = xxx,
4383
#endif
4384
#if 0
4385
    CPU_POWERPC_405C3       = xxx,
4386
#endif
4387
#if 0
4388
    CPU_POWERPC_405C4       = xxx,
4389
#endif
4390
    CPU_POWERPC_405D2       = 0x20010000,
4391
#if 0
4392
    CPU_POWERPC_405D3       = xxx,
4393
#endif
4394
    CPU_POWERPC_405D4       = 0x41810000,
4395
#if 0
4396
    CPU_POWERPC_405D5       = xxx,
4397
#endif
4398
#if 0
4399
    CPU_POWERPC_405E4       = xxx,
4400
#endif
4401
#if 0
4402
    CPU_POWERPC_405F4       = xxx,
4403
#endif
4404
#if 0
4405
    CPU_POWERPC_405F5       = xxx,
4406
#endif
4407
#if 0
4408
    CPU_POWERPC_405F6       = xxx,
4409
#endif
4410
    /* PowerPC 405 microcontrolers */
4411
    /* XXX: missing 0x200108a0 */
4412
#define CPU_POWERPC_405CR     CPU_POWERPC_405CRc
4413
    CPU_POWERPC_405CRa      = 0x40110041,
4414
    CPU_POWERPC_405CRb      = 0x401100C5,
4415
    CPU_POWERPC_405CRc      = 0x40110145,
4416
    CPU_POWERPC_405EP       = 0x51210950,
4417
#if 0
4418
    CPU_POWERPC_405EXr      = xxx,
4419
#endif
4420
    CPU_POWERPC_405EZ       = 0x41511460, /* 0x51210950 ? */
4421
#if 0
4422
    CPU_POWERPC_405FX       = xxx,
4423
#endif
4424
#define CPU_POWERPC_405GP     CPU_POWERPC_405GPd
4425
    CPU_POWERPC_405GPa      = 0x40110000,
4426
    CPU_POWERPC_405GPb      = 0x40110040,
4427
    CPU_POWERPC_405GPc      = 0x40110082,
4428
    CPU_POWERPC_405GPd      = 0x401100C4,
4429
#define CPU_POWERPC_405GPe    CPU_POWERPC_405CRc
4430
    CPU_POWERPC_405GPR      = 0x50910951,
4431
#if 0
4432
    CPU_POWERPC_405H        = xxx,
4433
#endif
4434
#if 0
4435
    CPU_POWERPC_405L        = xxx,
4436
#endif
4437
    CPU_POWERPC_405LP       = 0x41F10000,
4438
#if 0
4439
    CPU_POWERPC_405PM       = xxx,
4440
#endif
4441
#if 0
4442
    CPU_POWERPC_405PS       = xxx,
4443
#endif
4444
#if 0
4445
    CPU_POWERPC_405S        = xxx,
4446
#endif
4447
    /* IBM network processors */
4448
    CPU_POWERPC_NPE405H     = 0x414100C0,
4449
    CPU_POWERPC_NPE405H2    = 0x41410140,
4450
    CPU_POWERPC_NPE405L     = 0x416100C0,
4451
    CPU_POWERPC_NPE4GS3     = 0x40B10000,
4452
#if 0
4453
    CPU_POWERPC_NPCxx1      = xxx,
4454
#endif
4455
#if 0
4456
    CPU_POWERPC_NPR161      = xxx,
4457
#endif
4458
#if 0
4459
    CPU_POWERPC_LC77700     = xxx,
4460
#endif
4461
    /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4462
#if 0
4463
    CPU_POWERPC_STB01000    = xxx,
4464
#endif
4465
#if 0
4466
    CPU_POWERPC_STB01010    = xxx,
4467
#endif
4468
#if 0
4469
    CPU_POWERPC_STB0210     = xxx, /* 401B3 */
4470
#endif
4471
    CPU_POWERPC_STB03       = 0x40310000, /* 0x40130000 ? */
4472
#if 0
4473
    CPU_POWERPC_STB043      = xxx,
4474
#endif
4475
#if 0
4476
    CPU_POWERPC_STB045      = xxx,
4477
#endif
4478
    CPU_POWERPC_STB04       = 0x41810000,
4479
    CPU_POWERPC_STB25       = 0x51510950,
4480
#if 0
4481
    CPU_POWERPC_STB130      = xxx,
4482
#endif
4483
    /* Xilinx cores */
4484
    CPU_POWERPC_X2VP4       = 0x20010820,
4485
#define CPU_POWERPC_X2VP7     CPU_POWERPC_X2VP4
4486
    CPU_POWERPC_X2VP20      = 0x20010860,
4487
#define CPU_POWERPC_X2VP50    CPU_POWERPC_X2VP20
4488
#if 0
4489
    CPU_POWERPC_ZL10310     = xxx,
4490
#endif
4491
#if 0
4492
    CPU_POWERPC_ZL10311     = xxx,
4493
#endif
4494
#if 0
4495
    CPU_POWERPC_ZL10320     = xxx,
4496
#endif
4497
#if 0
4498
    CPU_POWERPC_ZL10321     = xxx,
4499
#endif
4500
    /* PowerPC 440 family */
4501
    /* Generic PowerPC 440 */
4502
#define CPU_POWERPC_440       CPU_POWERPC_440GXf
4503
    /* PowerPC 440 cores */
4504
#if 0
4505
    CPU_POWERPC_440A4       = xxx,
4506
#endif
4507
#if 0
4508
    CPU_POWERPC_440A5       = xxx,
4509
#endif
4510
#if 0
4511
    CPU_POWERPC_440B4       = xxx,
4512
#endif
4513
#if 0
4514
    CPU_POWERPC_440F5       = xxx,
4515
#endif
4516
#if 0
4517
    CPU_POWERPC_440G5       = xxx,
4518
#endif
4519
#if 0
4520
    CPU_POWERPC_440H4       = xxx,
4521
#endif
4522
#if 0
4523
    CPU_POWERPC_440H6       = xxx,
4524
#endif
4525
    /* PowerPC 440 microcontrolers */
4526
#define CPU_POWERPC_440EP     CPU_POWERPC_440EPb
4527
    CPU_POWERPC_440EPa      = 0x42221850,
4528
    CPU_POWERPC_440EPb      = 0x422218D3,
4529
#define CPU_POWERPC_440GP     CPU_POWERPC_440GPc
4530
    CPU_POWERPC_440GPb      = 0x40120440,
4531
    CPU_POWERPC_440GPc      = 0x40120481,
4532
#define CPU_POWERPC_440GR     CPU_POWERPC_440GRa
4533
#define CPU_POWERPC_440GRa    CPU_POWERPC_440EPb
4534
    CPU_POWERPC_440GRX      = 0x200008D0,
4535
#define CPU_POWERPC_440EPX    CPU_POWERPC_440GRX
4536
#define CPU_POWERPC_440GX     CPU_POWERPC_440GXf
4537
    CPU_POWERPC_440GXa      = 0x51B21850,
4538
    CPU_POWERPC_440GXb      = 0x51B21851,
4539
    CPU_POWERPC_440GXc      = 0x51B21892,
4540
    CPU_POWERPC_440GXf      = 0x51B21894,
4541
#if 0
4542
    CPU_POWERPC_440S        = xxx,
4543
#endif
4544
    CPU_POWERPC_440SP       = 0x53221850,
4545
    CPU_POWERPC_440SP2      = 0x53221891,
4546
    CPU_POWERPC_440SPE      = 0x53421890,
4547
    /* PowerPC 460 family */
4548
#if 0
4549
    /* Generic PowerPC 464 */
4550
#define CPU_POWERPC_464       CPU_POWERPC_464H90
4551
#endif
4552
    /* PowerPC 464 microcontrolers */
4553
#if 0
4554
    CPU_POWERPC_464H90      = xxx,
4555
#endif
4556
#if 0
4557
    CPU_POWERPC_464H90FP    = xxx,
4558
#endif
4559
    /* Freescale embedded PowerPC cores */
4560
    /* e200 family */
4561
#define CPU_POWERPC_e200      CPU_POWERPC_e200z6
4562
#if 0
4563
    CPU_POWERPC_e200z0      = xxx,
4564
#endif
4565
#if 0
4566
    CPU_POWERPC_e200z3      = xxx,
4567
#endif
4568
    CPU_POWERPC_e200z5      = 0x81000000,
4569
    CPU_POWERPC_e200z6      = 0x81120000,
4570
    /* e300 family */
4571
#define CPU_POWERPC_e300      CPU_POWERPC_e300c3
4572
    CPU_POWERPC_e300c1      = 0x00830000,
4573
    CPU_POWERPC_e300c2      = 0x00840000,
4574
    CPU_POWERPC_e300c3      = 0x00850000,
4575
    /* e500 family */
4576
#define CPU_POWERPC_e500      CPU_POWERPC_e500_v22
4577
    CPU_POWERPC_e500_v11    = 0x80200010,
4578
    CPU_POWERPC_e500_v12    = 0x80200020,
4579
    CPU_POWERPC_e500_v21    = 0x80210010,
4580
    CPU_POWERPC_e500_v22    = 0x80210020,
4581
#if 0
4582
    CPU_POWERPC_e500mc      = xxx,
4583
#endif
4584
    /* e600 family */
4585
    CPU_POWERPC_e600        = 0x80040010,
4586
    /* PowerPC MPC 5xx cores */
4587
    CPU_POWERPC_5xx         = 0x00020020,
4588
    /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4589
    CPU_POWERPC_8xx         = 0x00500000,
4590
    /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
4591
    CPU_POWERPC_82xx_HIP3   = 0x00810101,
4592
    CPU_POWERPC_82xx_HIP4   = 0x80811014,
4593
    CPU_POWERPC_827x        = 0x80822013,
4594
    /* PowerPC 6xx cores */
4595
    CPU_POWERPC_601         = 0x00010001,
4596
    CPU_POWERPC_601a        = 0x00010002,
4597
    CPU_POWERPC_602         = 0x00050100,
4598
    CPU_POWERPC_603         = 0x00030100,
4599
#define CPU_POWERPC_603E      CPU_POWERPC_603E_v41
4600
    CPU_POWERPC_603E_v11    = 0x00060101,
4601
    CPU_POWERPC_603E_v12    = 0x00060102,
4602
    CPU_POWERPC_603E_v13    = 0x00060103,
4603
    CPU_POWERPC_603E_v14    = 0x00060104,
4604
    CPU_POWERPC_603E_v22    = 0x00060202,
4605
    CPU_POWERPC_603E_v3     = 0x00060300,
4606
    CPU_POWERPC_603E_v4     = 0x00060400,
4607
    CPU_POWERPC_603E_v41    = 0x00060401,
4608
    CPU_POWERPC_603E7t      = 0x00071201,
4609
    CPU_POWERPC_603E7v      = 0x00070100,
4610
    CPU_POWERPC_603E7v1     = 0x00070101,
4611
    CPU_POWERPC_603E7v2     = 0x00070201,
4612
    CPU_POWERPC_603E7       = 0x00070200,
4613
    CPU_POWERPC_603P        = 0x00070000,
4614
#define CPU_POWERPC_603R      CPU_POWERPC_603E7t
4615
    CPU_POWERPC_G2          = 0x00810011,
4616
#if 0 // Linux pretends the MSB is zero...
4617
    CPU_POWERPC_G2H4        = 0x80811010,
4618
    CPU_POWERPC_G2gp        = 0x80821010,
4619
    CPU_POWERPC_G2ls        = 0x90810010,
4620
    CPU_POWERPC_G2LE        = 0x80820010,
4621
    CPU_POWERPC_G2LEgp      = 0x80822010,
4622
    CPU_POWERPC_G2LEls      = 0xA0822010,
4623
#else
4624
    CPU_POWERPC_G2H4        = 0x00811010,
4625
    CPU_POWERPC_G2gp        = 0x00821010,
4626
    CPU_POWERPC_G2ls        = 0x10810010,
4627
    CPU_POWERPC_G2LE        = 0x00820010,
4628
    CPU_POWERPC_G2LEgp      = 0x00822010,
4629
    CPU_POWERPC_G2LEls      = 0x20822010,
4630
#endif
4631
    CPU_POWERPC_604         = 0x00040103,
4632
#define CPU_POWERPC_604E      CPU_POWERPC_604E_v24
4633
    CPU_POWERPC_604E_v10    = 0x00090100, /* Also 2110 & 2120 */
4634
    CPU_POWERPC_604E_v22    = 0x00090202,
4635
    CPU_POWERPC_604E_v24    = 0x00090204,
4636
    CPU_POWERPC_604R        = 0x000a0101, /* Also 0x00093102 */
4637
#if 0
4638
    CPU_POWERPC_604EV       = xxx,
4639
#endif
4640
    /* PowerPC 740/750 cores (aka G3) */
4641
    /* XXX: missing 0x00084202 */
4642
#define CPU_POWERPC_7x0       CPU_POWERPC_7x0_v31
4643
    CPU_POWERPC_7x0_v20     = 0x00080200,
4644
    CPU_POWERPC_7x0_v21     = 0x00080201,
4645
    CPU_POWERPC_7x0_v22     = 0x00080202,
4646
    CPU_POWERPC_7x0_v30     = 0x00080300,
4647
    CPU_POWERPC_7x0_v31     = 0x00080301,
4648
    CPU_POWERPC_740E        = 0x00080100,
4649
    CPU_POWERPC_7x0P        = 0x10080000,
4650
    /* XXX: missing 0x00087010 (CL ?) */
4651
    CPU_POWERPC_750CL       = 0x00087200,
4652
#define CPU_POWERPC_750CX     CPU_POWERPC_750CX_v22
4653
    CPU_POWERPC_750CX_v21   = 0x00082201,
4654
    CPU_POWERPC_750CX_v22   = 0x00082202,
4655
#define CPU_POWERPC_750CXE    CPU_POWERPC_750CXE_v31b
4656
    CPU_POWERPC_750CXE_v21  = 0x00082211,
4657
    CPU_POWERPC_750CXE_v22  = 0x00082212,
4658
    CPU_POWERPC_750CXE_v23  = 0x00082213,
4659
    CPU_POWERPC_750CXE_v24  = 0x00082214,
4660
    CPU_POWERPC_750CXE_v24b = 0x00083214,
4661
    CPU_POWERPC_750CXE_v31  = 0x00083211,
4662
    CPU_POWERPC_750CXE_v31b = 0x00083311,
4663
    CPU_POWERPC_750CXR      = 0x00083410,
4664
    CPU_POWERPC_750E        = 0x00080200,
4665
    CPU_POWERPC_750FL       = 0x700A0203,
4666
#define CPU_POWERPC_750FX     CPU_POWERPC_750FX_v23
4667
    CPU_POWERPC_750FX_v10   = 0x70000100,
4668
    CPU_POWERPC_750FX_v20   = 0x70000200,
4669
    CPU_POWERPC_750FX_v21   = 0x70000201,
4670
    CPU_POWERPC_750FX_v22   = 0x70000202,
4671
    CPU_POWERPC_750FX_v23   = 0x70000203,
4672
    CPU_POWERPC_750GL       = 0x70020102,
4673
#define CPU_POWERPC_750GX     CPU_POWERPC_750GX_v12
4674
    CPU_POWERPC_750GX_v10   = 0x70020100,
4675
    CPU_POWERPC_750GX_v11   = 0x70020101,
4676
    CPU_POWERPC_750GX_v12   = 0x70020102,
4677
#define CPU_POWERPC_750L      CPU_POWERPC_750L_v32 /* Aka LoneStar */
4678
    CPU_POWERPC_750L_v22    = 0x00088202,
4679
    CPU_POWERPC_750L_v30    = 0x00088300,
4680
    CPU_POWERPC_750L_v32    = 0x00088302,
4681
    /* PowerPC 745/755 cores */
4682
#define CPU_POWERPC_7x5       CPU_POWERPC_7x5_v28
4683
    CPU_POWERPC_7x5_v10     = 0x00083100,
4684
    CPU_POWERPC_7x5_v11     = 0x00083101,
4685
    CPU_POWERPC_7x5_v20     = 0x00083200,
4686
    CPU_POWERPC_7x5_v21     = 0x00083201,
4687
    CPU_POWERPC_7x5_v22     = 0x00083202, /* aka D */
4688
    CPU_POWERPC_7x5_v23     = 0x00083203, /* aka E */
4689
    CPU_POWERPC_7x5_v24     = 0x00083204,
4690
    CPU_POWERPC_7x5_v25     = 0x00083205,
4691
    CPU_POWERPC_7x5_v26     = 0x00083206,
4692
    CPU_POWERPC_7x5_v27     = 0x00083207,
4693
    CPU_POWERPC_7x5_v28     = 0x00083208,
4694
#if 0
4695
    CPU_POWERPC_7x5P        = xxx,
4696
#endif
4697
    /* PowerPC 74xx cores (aka G4) */
4698
    /* XXX: missing 0x000C1101 */
4699
#define CPU_POWERPC_7400      CPU_POWERPC_7400_v29
4700
    CPU_POWERPC_7400_v10    = 0x000C0100,
4701
    CPU_POWERPC_7400_v11    = 0x000C0101,
4702
    CPU_POWERPC_7400_v20    = 0x000C0200,
4703
    CPU_POWERPC_7400_v22    = 0x000C0202,
4704
    CPU_POWERPC_7400_v26    = 0x000C0206,
4705
    CPU_POWERPC_7400_v27    = 0x000C0207,
4706
    CPU_POWERPC_7400_v28    = 0x000C0208,
4707
    CPU_POWERPC_7400_v29    = 0x000C0209,
4708
#define CPU_POWERPC_7410      CPU_POWERPC_7410_v14
4709
    CPU_POWERPC_7410_v10    = 0x800C1100,
4710
    CPU_POWERPC_7410_v11    = 0x800C1101,
4711
    CPU_POWERPC_7410_v12    = 0x800C1102, /* aka C */
4712
    CPU_POWERPC_7410_v13    = 0x800C1103, /* aka D */
4713
    CPU_POWERPC_7410_v14    = 0x800C1104, /* aka E */
4714
#define CPU_POWERPC_7448      CPU_POWERPC_7448_v21
4715
    CPU_POWERPC_7448_v10    = 0x80040100,
4716
    CPU_POWERPC_7448_v11    = 0x80040101,
4717
    CPU_POWERPC_7448_v20    = 0x80040200,
4718
    CPU_POWERPC_7448_v21    = 0x80040201,
4719
#define CPU_POWERPC_7450      CPU_POWERPC_7450_v21
4720
    CPU_POWERPC_7450_v10    = 0x80000100,
4721
    CPU_POWERPC_7450_v11    = 0x80000101,
4722
    CPU_POWERPC_7450_v12    = 0x80000102,
4723
    CPU_POWERPC_7450_v20    = 0x80000200, /* aka D: 2.04 */
4724
    CPU_POWERPC_7450_v21    = 0x80000201, /* aka E */
4725
    CPU_POWERPC_74x1        = 0x80000203,
4726
    CPU_POWERPC_74x1G       = 0x80000210, /* aka G: 2.3 */
4727
    /* XXX: missing 0x80010200 */
4728
#define CPU_POWERPC_74x5      CPU_POWERPC_74x5_v32
4729
    CPU_POWERPC_74x5_v10    = 0x80010100,
4730
    CPU_POWERPC_74x5_v21    = 0x80010201, /* aka C: 2.1 */
4731
    CPU_POWERPC_74x5_v32    = 0x80010302,