Revision 7a977356
b/target-cris/helper.c | ||
---|---|---|
87 | 87 |
if (miss) |
88 | 88 |
{ |
89 | 89 |
if (env->exception_index == EXCP_BUSFAULT) |
90 |
cpu_abort(env,
|
|
90 |
cpu_abort(env, |
|
91 | 91 |
"CRIS: Illegal recursive bus fault." |
92 |
"addr=%x rw=%d\n",
|
|
93 |
address, rw);
|
|
92 |
"addr=%x rw=%d\n", |
|
93 |
address, rw); |
|
94 | 94 |
|
95 | 95 |
env->pregs[PR_EDA] = address; |
96 | 96 |
env->exception_index = EXCP_BUSFAULT; |
... | ... | |
116 | 116 |
return r; |
117 | 117 |
} |
118 | 118 |
|
119 |
static void do_interruptv10(CPUState *env) |
|
120 |
{ |
|
121 |
int ex_vec = -1; |
|
122 |
|
|
123 |
D_LOG( "exception index=%d interrupt_req=%d\n", |
|
124 |
env->exception_index, |
|
125 |
env->interrupt_request); |
|
126 |
|
|
127 |
assert(!(env->pregs[PR_CCS] & PFIX_FLAG)); |
|
128 |
switch (env->exception_index) |
|
129 |
{ |
|
130 |
case EXCP_BREAK: |
|
131 |
/* These exceptions are genereated by the core itself. |
|
132 |
ERP should point to the insn following the brk. */ |
|
133 |
ex_vec = env->trap_vector; |
|
134 |
env->pregs[PR_ERP] = env->pc; |
|
135 |
break; |
|
136 |
|
|
137 |
case EXCP_NMI: |
|
138 |
/* NMI is hardwired to vector zero. */ |
|
139 |
ex_vec = 0; |
|
140 |
env->pregs[PR_CCS] &= ~M_FLAG; |
|
141 |
env->pregs[PR_NRP] = env->pc; |
|
142 |
break; |
|
143 |
|
|
144 |
case EXCP_BUSFAULT: |
|
145 |
assert(0); |
|
146 |
break; |
|
147 |
|
|
148 |
default: |
|
149 |
/* The interrupt controller gives us the vector. */ |
|
150 |
ex_vec = env->interrupt_vector; |
|
151 |
/* Normal interrupts are taken between |
|
152 |
TB's. env->pc is valid here. */ |
|
153 |
env->pregs[PR_ERP] = env->pc; |
|
154 |
break; |
|
155 |
} |
|
156 |
|
|
157 |
if (env->pregs[PR_CCS] & U_FLAG) { |
|
158 |
/* Swap stack pointers. */ |
|
159 |
env->pregs[PR_USP] = env->regs[R_SP]; |
|
160 |
env->regs[R_SP] = env->ksp; |
|
161 |
} |
|
162 |
|
|
163 |
/* Now that we are in kernel mode, load the handlers address. */ |
|
164 |
env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4); |
|
165 |
env->locked_irq = 1; |
|
166 |
|
|
167 |
qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n", |
|
168 |
__func__, env->pc, ex_vec, |
|
169 |
env->pregs[PR_CCS], |
|
170 |
env->pregs[PR_PID], |
|
171 |
env->pregs[PR_ERP]); |
|
172 |
} |
|
173 |
|
|
119 | 174 |
void do_interrupt(CPUState *env) |
120 | 175 |
{ |
121 | 176 |
int ex_vec = -1; |
122 | 177 |
|
178 |
if (env->pregs[PR_VR] < 32) |
|
179 |
return do_interruptv10(env); |
|
180 |
|
|
123 | 181 |
D_LOG( "exception index=%d interrupt_req=%d\n", |
124 | 182 |
env->exception_index, |
125 | 183 |
env->interrupt_request); |
... | ... | |
184 | 242 |
/* Now that we are in kernel mode, load the handlers address. */ |
185 | 243 |
env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4); |
186 | 244 |
|
187 |
D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
|
|
188 |
__func__, env->pc, ex_vec,
|
|
245 |
D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n", |
|
246 |
__func__, env->pc, ex_vec, |
|
189 | 247 |
env->pregs[PR_CCS], |
190 | 248 |
env->pregs[PR_PID], |
191 | 249 |
env->pregs[PR_ERP]); |
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