root / hw / acpi.c @ 7ba1e619
History | View | Annotate | Download (13 kB)
1 | 6515b203 | bellard | /*
|
---|---|---|---|
2 | 6515b203 | bellard | * ACPI implementation
|
3 | 5fafdf24 | ths | *
|
4 | 6515b203 | bellard | * Copyright (c) 2006 Fabrice Bellard
|
5 | 5fafdf24 | ths | *
|
6 | 6515b203 | bellard | * This library is free software; you can redistribute it and/or
|
7 | 6515b203 | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | 6515b203 | bellard | * License version 2 as published by the Free Software Foundation.
|
9 | 6515b203 | bellard | *
|
10 | 6515b203 | bellard | * This library is distributed in the hope that it will be useful,
|
11 | 6515b203 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
12 | 6515b203 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
13 | 6515b203 | bellard | * Lesser General Public License for more details.
|
14 | 6515b203 | bellard | *
|
15 | 6515b203 | bellard | * You should have received a copy of the GNU Lesser General Public
|
16 | 6515b203 | bellard | * License along with this library; if not, write to the Free Software
|
17 | 6515b203 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
18 | 6515b203 | bellard | */
|
19 | 87ecb68b | pbrook | #include "hw.h" |
20 | 87ecb68b | pbrook | #include "pc.h" |
21 | 87ecb68b | pbrook | #include "pci.h" |
22 | 87ecb68b | pbrook | #include "qemu-timer.h" |
23 | 87ecb68b | pbrook | #include "sysemu.h" |
24 | 87ecb68b | pbrook | #include "i2c.h" |
25 | 87ecb68b | pbrook | #include "smbus.h" |
26 | 7ba1e619 | aliguori | #include "kvm.h" |
27 | 6515b203 | bellard | |
28 | 6515b203 | bellard | //#define DEBUG
|
29 | 6515b203 | bellard | |
30 | 6515b203 | bellard | /* i82731AB (PIIX4) compatible power management function */
|
31 | 6515b203 | bellard | #define PM_FREQ 3579545 |
32 | 6515b203 | bellard | |
33 | 6515b203 | bellard | #define ACPI_DBG_IO_ADDR 0xb044 |
34 | 6515b203 | bellard | |
35 | 6515b203 | bellard | typedef struct PIIX4PMState { |
36 | 6515b203 | bellard | PCIDevice dev; |
37 | 6515b203 | bellard | uint16_t pmsts; |
38 | 6515b203 | bellard | uint16_t pmen; |
39 | 6515b203 | bellard | uint16_t pmcntrl; |
40 | ab1e34ad | bellard | uint8_t apmc; |
41 | ab1e34ad | bellard | uint8_t apms; |
42 | 6515b203 | bellard | QEMUTimer *tmr_timer; |
43 | 6515b203 | bellard | int64_t tmr_overflow_time; |
44 | 0ff596d0 | pbrook | i2c_bus *smbus; |
45 | 3fffc223 | ths | uint8_t smb_stat; |
46 | 3fffc223 | ths | uint8_t smb_ctl; |
47 | 3fffc223 | ths | uint8_t smb_cmd; |
48 | 3fffc223 | ths | uint8_t smb_addr; |
49 | 3fffc223 | ths | uint8_t smb_data0; |
50 | 3fffc223 | ths | uint8_t smb_data1; |
51 | 3fffc223 | ths | uint8_t smb_data[32];
|
52 | 3fffc223 | ths | uint8_t smb_index; |
53 | cf7a2fe2 | aurel32 | qemu_irq irq; |
54 | 6515b203 | bellard | } PIIX4PMState; |
55 | 6515b203 | bellard | |
56 | 6515b203 | bellard | #define RTC_EN (1 << 10) |
57 | 6515b203 | bellard | #define PWRBTN_EN (1 << 8) |
58 | 6515b203 | bellard | #define GBL_EN (1 << 5) |
59 | 6515b203 | bellard | #define TMROF_EN (1 << 0) |
60 | 6515b203 | bellard | |
61 | 6515b203 | bellard | #define SCI_EN (1 << 0) |
62 | 6515b203 | bellard | |
63 | 6515b203 | bellard | #define SUS_EN (1 << 13) |
64 | 6515b203 | bellard | |
65 | 24bc1cbc | ths | #define ACPI_ENABLE 0xf1 |
66 | 24bc1cbc | ths | #define ACPI_DISABLE 0xf0 |
67 | 24bc1cbc | ths | |
68 | 3fffc223 | ths | #define SMBHSTSTS 0x00 |
69 | 3fffc223 | ths | #define SMBHSTCNT 0x02 |
70 | 3fffc223 | ths | #define SMBHSTCMD 0x03 |
71 | 3fffc223 | ths | #define SMBHSTADD 0x04 |
72 | 3fffc223 | ths | #define SMBHSTDAT0 0x05 |
73 | 3fffc223 | ths | #define SMBHSTDAT1 0x06 |
74 | 3fffc223 | ths | #define SMBBLKDAT 0x07 |
75 | 3fffc223 | ths | |
76 | 9669d3c5 | aurel32 | static PIIX4PMState *pm_state;
|
77 | cf7a2fe2 | aurel32 | |
78 | 6515b203 | bellard | static uint32_t get_pmtmr(PIIX4PMState *s)
|
79 | 6515b203 | bellard | { |
80 | 7546c016 | balrog | uint32_t d; |
81 | 7546c016 | balrog | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
82 | 7546c016 | balrog | return d & 0xffffff; |
83 | 6515b203 | bellard | } |
84 | 6515b203 | bellard | |
85 | 6515b203 | bellard | static int get_pmsts(PIIX4PMState *s) |
86 | 6515b203 | bellard | { |
87 | 7546c016 | balrog | int64_t d; |
88 | 7546c016 | balrog | int pmsts;
|
89 | 7546c016 | balrog | pmsts = s->pmsts; |
90 | 7546c016 | balrog | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
91 | 7546c016 | balrog | if (d >= s->tmr_overflow_time)
|
92 | 7546c016 | balrog | s->pmsts |= TMROF_EN; |
93 | 7546c016 | balrog | return pmsts;
|
94 | 6515b203 | bellard | } |
95 | 6515b203 | bellard | |
96 | 6515b203 | bellard | static void pm_update_sci(PIIX4PMState *s) |
97 | 6515b203 | bellard | { |
98 | 7546c016 | balrog | int sci_level, pmsts;
|
99 | 7546c016 | balrog | int64_t expire_time; |
100 | 7546c016 | balrog | |
101 | 7546c016 | balrog | pmsts = get_pmsts(s); |
102 | 7546c016 | balrog | sci_level = (((pmsts & s->pmen) & |
103 | 7546c016 | balrog | (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
|
104 | 7546c016 | balrog | qemu_set_irq(s->irq, sci_level); |
105 | 7546c016 | balrog | /* schedule a timer interruption if needed */
|
106 | 7546c016 | balrog | if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
|
107 | 7546c016 | balrog | expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ); |
108 | 7546c016 | balrog | qemu_mod_timer(s->tmr_timer, expire_time); |
109 | 7546c016 | balrog | } else {
|
110 | 7546c016 | balrog | qemu_del_timer(s->tmr_timer); |
111 | 7546c016 | balrog | } |
112 | 6515b203 | bellard | } |
113 | 6515b203 | bellard | |
114 | 6515b203 | bellard | static void pm_tmr_timer(void *opaque) |
115 | 6515b203 | bellard | { |
116 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
117 | 7546c016 | balrog | pm_update_sci(s); |
118 | 6515b203 | bellard | } |
119 | 6515b203 | bellard | |
120 | 6515b203 | bellard | static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
121 | 6515b203 | bellard | { |
122 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
123 | 6515b203 | bellard | addr &= 0x3f;
|
124 | 6515b203 | bellard | switch(addr) {
|
125 | 6515b203 | bellard | case 0x00: |
126 | 7546c016 | balrog | { |
127 | 7546c016 | balrog | int64_t d; |
128 | 7546c016 | balrog | int pmsts;
|
129 | 7546c016 | balrog | pmsts = get_pmsts(s); |
130 | 7546c016 | balrog | if (pmsts & val & TMROF_EN) {
|
131 | 7546c016 | balrog | /* if TMRSTS is reset, then compute the new overflow time */
|
132 | 7546c016 | balrog | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
133 | 7546c016 | balrog | s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; |
134 | 7546c016 | balrog | } |
135 | 7546c016 | balrog | s->pmsts &= ~val; |
136 | 7546c016 | balrog | pm_update_sci(s); |
137 | 7546c016 | balrog | } |
138 | 6515b203 | bellard | break;
|
139 | 6515b203 | bellard | case 0x02: |
140 | 6515b203 | bellard | s->pmen = val; |
141 | 6515b203 | bellard | pm_update_sci(s); |
142 | 6515b203 | bellard | break;
|
143 | 6515b203 | bellard | case 0x04: |
144 | 6515b203 | bellard | { |
145 | 6515b203 | bellard | int sus_typ;
|
146 | 6515b203 | bellard | s->pmcntrl = val & ~(SUS_EN); |
147 | 6515b203 | bellard | if (val & SUS_EN) {
|
148 | 6515b203 | bellard | /* change suspend type */
|
149 | f99ed40a | aurel32 | sus_typ = (val >> 10) & 7; |
150 | 6515b203 | bellard | switch(sus_typ) {
|
151 | 6515b203 | bellard | case 0: /* soft power off */ |
152 | 6515b203 | bellard | qemu_system_shutdown_request(); |
153 | 6515b203 | bellard | break;
|
154 | 6515b203 | bellard | default:
|
155 | 6515b203 | bellard | break;
|
156 | 6515b203 | bellard | } |
157 | 6515b203 | bellard | } |
158 | 6515b203 | bellard | } |
159 | 6515b203 | bellard | break;
|
160 | 6515b203 | bellard | default:
|
161 | 6515b203 | bellard | break;
|
162 | 6515b203 | bellard | } |
163 | 6515b203 | bellard | #ifdef DEBUG
|
164 | 6515b203 | bellard | printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
|
165 | 6515b203 | bellard | #endif
|
166 | 6515b203 | bellard | } |
167 | 6515b203 | bellard | |
168 | 6515b203 | bellard | static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) |
169 | 6515b203 | bellard | { |
170 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
171 | 6515b203 | bellard | uint32_t val; |
172 | 6515b203 | bellard | |
173 | 6515b203 | bellard | addr &= 0x3f;
|
174 | 6515b203 | bellard | switch(addr) {
|
175 | 6515b203 | bellard | case 0x00: |
176 | 6515b203 | bellard | val = get_pmsts(s); |
177 | 6515b203 | bellard | break;
|
178 | 6515b203 | bellard | case 0x02: |
179 | 6515b203 | bellard | val = s->pmen; |
180 | 6515b203 | bellard | break;
|
181 | 6515b203 | bellard | case 0x04: |
182 | 6515b203 | bellard | val = s->pmcntrl; |
183 | 6515b203 | bellard | break;
|
184 | 6515b203 | bellard | default:
|
185 | 6515b203 | bellard | val = 0;
|
186 | 6515b203 | bellard | break;
|
187 | 6515b203 | bellard | } |
188 | 6515b203 | bellard | #ifdef DEBUG
|
189 | 6515b203 | bellard | printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
|
190 | 6515b203 | bellard | #endif
|
191 | 6515b203 | bellard | return val;
|
192 | 6515b203 | bellard | } |
193 | 6515b203 | bellard | |
194 | 6515b203 | bellard | static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
195 | 6515b203 | bellard | { |
196 | 6515b203 | bellard | // PIIX4PMState *s = opaque;
|
197 | 6515b203 | bellard | addr &= 0x3f;
|
198 | 6515b203 | bellard | #ifdef DEBUG
|
199 | 6515b203 | bellard | printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
|
200 | 6515b203 | bellard | #endif
|
201 | 6515b203 | bellard | } |
202 | 6515b203 | bellard | |
203 | 6515b203 | bellard | static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) |
204 | 6515b203 | bellard | { |
205 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
206 | 6515b203 | bellard | uint32_t val; |
207 | 6515b203 | bellard | |
208 | 6515b203 | bellard | addr &= 0x3f;
|
209 | 6515b203 | bellard | switch(addr) {
|
210 | 6515b203 | bellard | case 0x08: |
211 | 6515b203 | bellard | val = get_pmtmr(s); |
212 | 6515b203 | bellard | break;
|
213 | 6515b203 | bellard | default:
|
214 | 6515b203 | bellard | val = 0;
|
215 | 6515b203 | bellard | break;
|
216 | 6515b203 | bellard | } |
217 | 6515b203 | bellard | #ifdef DEBUG
|
218 | 6515b203 | bellard | printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
|
219 | 6515b203 | bellard | #endif
|
220 | 6515b203 | bellard | return val;
|
221 | 6515b203 | bellard | } |
222 | 6515b203 | bellard | |
223 | ab1e34ad | bellard | static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val) |
224 | 6515b203 | bellard | { |
225 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
226 | ab1e34ad | bellard | addr &= 1;
|
227 | 6515b203 | bellard | #ifdef DEBUG
|
228 | ab1e34ad | bellard | printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
|
229 | 6515b203 | bellard | #endif
|
230 | ab1e34ad | bellard | if (addr == 0) { |
231 | ab1e34ad | bellard | s->apmc = val; |
232 | 24bc1cbc | ths | |
233 | 24bc1cbc | ths | /* ACPI specs 3.0, 4.7.2.5 */
|
234 | 24bc1cbc | ths | if (val == ACPI_ENABLE) {
|
235 | 24bc1cbc | ths | s->pmcntrl |= SCI_EN; |
236 | 24bc1cbc | ths | } else if (val == ACPI_DISABLE) { |
237 | 24bc1cbc | ths | s->pmcntrl &= ~SCI_EN; |
238 | 24bc1cbc | ths | } |
239 | 24bc1cbc | ths | |
240 | 47d02f6d | bellard | if (s->dev.config[0x5b] & (1 << 1)) { |
241 | 47d02f6d | bellard | cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); |
242 | ab1e34ad | bellard | } |
243 | ab1e34ad | bellard | } else {
|
244 | ab1e34ad | bellard | s->apms = val; |
245 | 6515b203 | bellard | } |
246 | 6515b203 | bellard | } |
247 | 6515b203 | bellard | |
248 | ab1e34ad | bellard | static uint32_t pm_smi_readb(void *opaque, uint32_t addr) |
249 | ab1e34ad | bellard | { |
250 | ab1e34ad | bellard | PIIX4PMState *s = opaque; |
251 | ab1e34ad | bellard | uint32_t val; |
252 | 3b46e624 | ths | |
253 | ab1e34ad | bellard | addr &= 1;
|
254 | ab1e34ad | bellard | if (addr == 0) { |
255 | ab1e34ad | bellard | val = s->apmc; |
256 | ab1e34ad | bellard | } else {
|
257 | ab1e34ad | bellard | val = s->apms; |
258 | ab1e34ad | bellard | } |
259 | ab1e34ad | bellard | #ifdef DEBUG
|
260 | ab1e34ad | bellard | printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
|
261 | ab1e34ad | bellard | #endif
|
262 | ab1e34ad | bellard | return val;
|
263 | ab1e34ad | bellard | } |
264 | ab1e34ad | bellard | |
265 | 6515b203 | bellard | static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) |
266 | 6515b203 | bellard | { |
267 | 6515b203 | bellard | #if defined(DEBUG)
|
268 | 6515b203 | bellard | printf("ACPI: DBG: 0x%08x\n", val);
|
269 | 6515b203 | bellard | #endif
|
270 | 6515b203 | bellard | } |
271 | 6515b203 | bellard | |
272 | 3fffc223 | ths | static void smb_transaction(PIIX4PMState *s) |
273 | 3fffc223 | ths | { |
274 | 3fffc223 | ths | uint8_t prot = (s->smb_ctl >> 2) & 0x07; |
275 | 3fffc223 | ths | uint8_t read = s->smb_addr & 0x01;
|
276 | 3fffc223 | ths | uint8_t cmd = s->smb_cmd; |
277 | 3fffc223 | ths | uint8_t addr = s->smb_addr >> 1;
|
278 | 0ff596d0 | pbrook | i2c_bus *bus = s->smbus; |
279 | 3fffc223 | ths | |
280 | 3fffc223 | ths | #ifdef DEBUG
|
281 | 3fffc223 | ths | printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
|
282 | 3fffc223 | ths | #endif
|
283 | 3fffc223 | ths | switch(prot) {
|
284 | 3fffc223 | ths | case 0x0: |
285 | 0ff596d0 | pbrook | smbus_quick_command(bus, addr, read); |
286 | 3fffc223 | ths | break;
|
287 | 3fffc223 | ths | case 0x1: |
288 | 3fffc223 | ths | if (read) {
|
289 | 0ff596d0 | pbrook | s->smb_data0 = smbus_receive_byte(bus, addr); |
290 | 0ff596d0 | pbrook | } else {
|
291 | 0ff596d0 | pbrook | smbus_send_byte(bus, addr, cmd); |
292 | 3fffc223 | ths | } |
293 | 3fffc223 | ths | break;
|
294 | 3fffc223 | ths | case 0x2: |
295 | 3fffc223 | ths | if (read) {
|
296 | 0ff596d0 | pbrook | s->smb_data0 = smbus_read_byte(bus, addr, cmd); |
297 | 0ff596d0 | pbrook | } else {
|
298 | 0ff596d0 | pbrook | smbus_write_byte(bus, addr, cmd, s->smb_data0); |
299 | 3fffc223 | ths | } |
300 | 3fffc223 | ths | break;
|
301 | 3fffc223 | ths | case 0x3: |
302 | 3fffc223 | ths | if (read) {
|
303 | 3fffc223 | ths | uint16_t val; |
304 | 0ff596d0 | pbrook | val = smbus_read_word(bus, addr, cmd); |
305 | 3fffc223 | ths | s->smb_data0 = val; |
306 | 3fffc223 | ths | s->smb_data1 = val >> 8;
|
307 | 0ff596d0 | pbrook | } else {
|
308 | 0ff596d0 | pbrook | smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
|
309 | 3fffc223 | ths | } |
310 | 3fffc223 | ths | break;
|
311 | 3fffc223 | ths | case 0x5: |
312 | 3fffc223 | ths | if (read) {
|
313 | 0ff596d0 | pbrook | s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data); |
314 | 0ff596d0 | pbrook | } else {
|
315 | 0ff596d0 | pbrook | smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0); |
316 | 3fffc223 | ths | } |
317 | 3fffc223 | ths | break;
|
318 | 3fffc223 | ths | default:
|
319 | 3fffc223 | ths | goto error;
|
320 | 3fffc223 | ths | } |
321 | 3fffc223 | ths | return;
|
322 | 3fffc223 | ths | |
323 | 3fffc223 | ths | error:
|
324 | 3fffc223 | ths | s->smb_stat |= 0x04;
|
325 | 3fffc223 | ths | } |
326 | 3fffc223 | ths | |
327 | 3fffc223 | ths | static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
328 | 3fffc223 | ths | { |
329 | 3fffc223 | ths | PIIX4PMState *s = opaque; |
330 | 3fffc223 | ths | addr &= 0x3f;
|
331 | 3fffc223 | ths | #ifdef DEBUG
|
332 | 3fffc223 | ths | printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
|
333 | 3fffc223 | ths | #endif
|
334 | 3fffc223 | ths | switch(addr) {
|
335 | 3fffc223 | ths | case SMBHSTSTS:
|
336 | 3fffc223 | ths | s->smb_stat = 0;
|
337 | 3fffc223 | ths | s->smb_index = 0;
|
338 | 3fffc223 | ths | break;
|
339 | 3fffc223 | ths | case SMBHSTCNT:
|
340 | 3fffc223 | ths | s->smb_ctl = val; |
341 | 3fffc223 | ths | if (val & 0x40) |
342 | 3fffc223 | ths | smb_transaction(s); |
343 | 3fffc223 | ths | break;
|
344 | 3fffc223 | ths | case SMBHSTCMD:
|
345 | 3fffc223 | ths | s->smb_cmd = val; |
346 | 3fffc223 | ths | break;
|
347 | 3fffc223 | ths | case SMBHSTADD:
|
348 | 3fffc223 | ths | s->smb_addr = val; |
349 | 3fffc223 | ths | break;
|
350 | 3fffc223 | ths | case SMBHSTDAT0:
|
351 | 3fffc223 | ths | s->smb_data0 = val; |
352 | 3fffc223 | ths | break;
|
353 | 3fffc223 | ths | case SMBHSTDAT1:
|
354 | 3fffc223 | ths | s->smb_data1 = val; |
355 | 3fffc223 | ths | break;
|
356 | 3fffc223 | ths | case SMBBLKDAT:
|
357 | 3fffc223 | ths | s->smb_data[s->smb_index++] = val; |
358 | 3fffc223 | ths | if (s->smb_index > 31) |
359 | 3fffc223 | ths | s->smb_index = 0;
|
360 | 3fffc223 | ths | break;
|
361 | 3fffc223 | ths | default:
|
362 | 3fffc223 | ths | break;
|
363 | 3fffc223 | ths | } |
364 | 3fffc223 | ths | } |
365 | 3fffc223 | ths | |
366 | 3fffc223 | ths | static uint32_t smb_ioport_readb(void *opaque, uint32_t addr) |
367 | 3fffc223 | ths | { |
368 | 3fffc223 | ths | PIIX4PMState *s = opaque; |
369 | 3fffc223 | ths | uint32_t val; |
370 | 3fffc223 | ths | |
371 | 3fffc223 | ths | addr &= 0x3f;
|
372 | 3fffc223 | ths | switch(addr) {
|
373 | 3fffc223 | ths | case SMBHSTSTS:
|
374 | 3fffc223 | ths | val = s->smb_stat; |
375 | 3fffc223 | ths | break;
|
376 | 3fffc223 | ths | case SMBHSTCNT:
|
377 | 3fffc223 | ths | s->smb_index = 0;
|
378 | 3fffc223 | ths | val = s->smb_ctl & 0x1f;
|
379 | 3fffc223 | ths | break;
|
380 | 3fffc223 | ths | case SMBHSTCMD:
|
381 | 3fffc223 | ths | val = s->smb_cmd; |
382 | 3fffc223 | ths | break;
|
383 | 3fffc223 | ths | case SMBHSTADD:
|
384 | 3fffc223 | ths | val = s->smb_addr; |
385 | 3fffc223 | ths | break;
|
386 | 3fffc223 | ths | case SMBHSTDAT0:
|
387 | 3fffc223 | ths | val = s->smb_data0; |
388 | 3fffc223 | ths | break;
|
389 | 3fffc223 | ths | case SMBHSTDAT1:
|
390 | 3fffc223 | ths | val = s->smb_data1; |
391 | 3fffc223 | ths | break;
|
392 | 3fffc223 | ths | case SMBBLKDAT:
|
393 | 3fffc223 | ths | val = s->smb_data[s->smb_index++]; |
394 | 3fffc223 | ths | if (s->smb_index > 31) |
395 | 3fffc223 | ths | s->smb_index = 0;
|
396 | 3fffc223 | ths | break;
|
397 | 3fffc223 | ths | default:
|
398 | 3fffc223 | ths | val = 0;
|
399 | 3fffc223 | ths | break;
|
400 | 3fffc223 | ths | } |
401 | 3fffc223 | ths | #ifdef DEBUG
|
402 | 3fffc223 | ths | printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
|
403 | 3fffc223 | ths | #endif
|
404 | 3fffc223 | ths | return val;
|
405 | 3fffc223 | ths | } |
406 | 3fffc223 | ths | |
407 | ab1e34ad | bellard | static void pm_io_space_update(PIIX4PMState *s) |
408 | ab1e34ad | bellard | { |
409 | ab1e34ad | bellard | uint32_t pm_io_base; |
410 | ab1e34ad | bellard | |
411 | ab1e34ad | bellard | if (s->dev.config[0x80] & 1) { |
412 | ab1e34ad | bellard | pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
|
413 | bf367b54 | ths | pm_io_base &= 0xffc0;
|
414 | ab1e34ad | bellard | |
415 | ab1e34ad | bellard | /* XXX: need to improve memory and ioport allocation */
|
416 | ab1e34ad | bellard | #if defined(DEBUG)
|
417 | ab1e34ad | bellard | printf("PM: mapping to 0x%x\n", pm_io_base);
|
418 | ab1e34ad | bellard | #endif
|
419 | ab1e34ad | bellard | register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); |
420 | ab1e34ad | bellard | register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); |
421 | ab1e34ad | bellard | register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); |
422 | ab1e34ad | bellard | register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s); |
423 | ab1e34ad | bellard | } |
424 | ab1e34ad | bellard | } |
425 | ab1e34ad | bellard | |
426 | 5fafdf24 | ths | static void pm_write_config(PCIDevice *d, |
427 | ab1e34ad | bellard | uint32_t address, uint32_t val, int len)
|
428 | ab1e34ad | bellard | { |
429 | ab1e34ad | bellard | pci_default_write_config(d, address, val, len); |
430 | ab1e34ad | bellard | if (address == 0x80) |
431 | ab1e34ad | bellard | pm_io_space_update((PIIX4PMState *)d); |
432 | ab1e34ad | bellard | } |
433 | ab1e34ad | bellard | |
434 | ab1e34ad | bellard | static void pm_save(QEMUFile* f,void *opaque) |
435 | ab1e34ad | bellard | { |
436 | ab1e34ad | bellard | PIIX4PMState *s = opaque; |
437 | ab1e34ad | bellard | |
438 | ab1e34ad | bellard | pci_device_save(&s->dev, f); |
439 | ab1e34ad | bellard | |
440 | ab1e34ad | bellard | qemu_put_be16s(f, &s->pmsts); |
441 | ab1e34ad | bellard | qemu_put_be16s(f, &s->pmen); |
442 | ab1e34ad | bellard | qemu_put_be16s(f, &s->pmcntrl); |
443 | ab1e34ad | bellard | qemu_put_8s(f, &s->apmc); |
444 | ab1e34ad | bellard | qemu_put_8s(f, &s->apms); |
445 | ab1e34ad | bellard | qemu_put_timer(f, s->tmr_timer); |
446 | bee8d684 | ths | qemu_put_be64(f, s->tmr_overflow_time); |
447 | ab1e34ad | bellard | } |
448 | ab1e34ad | bellard | |
449 | ab1e34ad | bellard | static int pm_load(QEMUFile* f,void* opaque,int version_id) |
450 | ab1e34ad | bellard | { |
451 | ab1e34ad | bellard | PIIX4PMState *s = opaque; |
452 | ab1e34ad | bellard | int ret;
|
453 | ab1e34ad | bellard | |
454 | ab1e34ad | bellard | if (version_id > 1) |
455 | ab1e34ad | bellard | return -EINVAL;
|
456 | ab1e34ad | bellard | |
457 | ab1e34ad | bellard | ret = pci_device_load(&s->dev, f); |
458 | ab1e34ad | bellard | if (ret < 0) |
459 | ab1e34ad | bellard | return ret;
|
460 | ab1e34ad | bellard | |
461 | ab1e34ad | bellard | qemu_get_be16s(f, &s->pmsts); |
462 | ab1e34ad | bellard | qemu_get_be16s(f, &s->pmen); |
463 | ab1e34ad | bellard | qemu_get_be16s(f, &s->pmcntrl); |
464 | ab1e34ad | bellard | qemu_get_8s(f, &s->apmc); |
465 | ab1e34ad | bellard | qemu_get_8s(f, &s->apms); |
466 | ab1e34ad | bellard | qemu_get_timer(f, s->tmr_timer); |
467 | bee8d684 | ths | s->tmr_overflow_time=qemu_get_be64(f); |
468 | ab1e34ad | bellard | |
469 | ab1e34ad | bellard | pm_io_space_update(s); |
470 | ab1e34ad | bellard | |
471 | ab1e34ad | bellard | return 0; |
472 | ab1e34ad | bellard | } |
473 | ab1e34ad | bellard | |
474 | cf7a2fe2 | aurel32 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
475 | cf7a2fe2 | aurel32 | qemu_irq sci_irq) |
476 | 6515b203 | bellard | { |
477 | 6515b203 | bellard | PIIX4PMState *s; |
478 | 6515b203 | bellard | uint8_t *pci_conf; |
479 | 6515b203 | bellard | |
480 | 6515b203 | bellard | s = (PIIX4PMState *)pci_register_device(bus, |
481 | 6515b203 | bellard | "PM", sizeof(PIIX4PMState), |
482 | ab1e34ad | bellard | devfn, NULL, pm_write_config);
|
483 | cf7a2fe2 | aurel32 | pm_state = s; |
484 | 6515b203 | bellard | pci_conf = s->dev.config; |
485 | 6515b203 | bellard | pci_conf[0x00] = 0x86; |
486 | 6515b203 | bellard | pci_conf[0x01] = 0x80; |
487 | 6515b203 | bellard | pci_conf[0x02] = 0x13; |
488 | 7ef4da1c | bellard | pci_conf[0x03] = 0x71; |
489 | bf367b54 | ths | pci_conf[0x06] = 0x80; |
490 | bf367b54 | ths | pci_conf[0x07] = 0x02; |
491 | a78b03cb | balrog | pci_conf[0x08] = 0x03; // revision number |
492 | 6515b203 | bellard | pci_conf[0x09] = 0x00; |
493 | 6515b203 | bellard | pci_conf[0x0a] = 0x80; // other bridge device |
494 | 6515b203 | bellard | pci_conf[0x0b] = 0x06; // bridge device |
495 | 6515b203 | bellard | pci_conf[0x0e] = 0x00; // header_type |
496 | 6515b203 | bellard | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
497 | 3b46e624 | ths | |
498 | ab1e34ad | bellard | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
499 | 3b46e624 | ths | |
500 | ab1e34ad | bellard | register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s); |
501 | ab1e34ad | bellard | register_ioport_read(0xb2, 2, 1, pm_smi_readb, s); |
502 | ab1e34ad | bellard | |
503 | 6515b203 | bellard | register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); |
504 | 6515b203 | bellard | |
505 | 7ba1e619 | aliguori | if (kvm_enabled()) {
|
506 | 7ba1e619 | aliguori | /* Mark SMM as already inited to prevent SMM from running. KVM does not
|
507 | 7ba1e619 | aliguori | * support SMM mode. */
|
508 | 7ba1e619 | aliguori | pci_conf[0x5B] = 0x02; |
509 | 7ba1e619 | aliguori | } |
510 | 7ba1e619 | aliguori | |
511 | 1ce549ab | bellard | /* XXX: which specification is used ? The i82731AB has different
|
512 | 1ce549ab | bellard | mappings */
|
513 | 1ce549ab | bellard | pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10; |
514 | 1ce549ab | bellard | pci_conf[0x63] = 0x60; |
515 | 1ce549ab | bellard | pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) | |
516 | 1ce549ab | bellard | (serial_hds[1] != NULL ? 0x90 : 0); |
517 | 1ce549ab | bellard | |
518 | 3fffc223 | ths | pci_conf[0x90] = smb_io_base | 1; |
519 | 3fffc223 | ths | pci_conf[0x91] = smb_io_base >> 8; |
520 | 3fffc223 | ths | pci_conf[0xd2] = 0x09; |
521 | 3fffc223 | ths | register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s); |
522 | 3fffc223 | ths | register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s); |
523 | 3fffc223 | ths | |
524 | 6515b203 | bellard | s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s); |
525 | 6515b203 | bellard | |
526 | ab1e34ad | bellard | register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s); |
527 | 3fffc223 | ths | |
528 | 0ff596d0 | pbrook | s->smbus = i2c_init_bus(); |
529 | cf7a2fe2 | aurel32 | s->irq = sci_irq; |
530 | 0ff596d0 | pbrook | return s->smbus;
|
531 | 6515b203 | bellard | } |
532 | cf7a2fe2 | aurel32 | |
533 | cf7a2fe2 | aurel32 | #if defined(TARGET_I386)
|
534 | cf7a2fe2 | aurel32 | void qemu_system_powerdown(void) |
535 | cf7a2fe2 | aurel32 | { |
536 | 9669d3c5 | aurel32 | if (!pm_state) {
|
537 | 9669d3c5 | aurel32 | qemu_system_shutdown_request(); |
538 | 9669d3c5 | aurel32 | } else if (pm_state->pmen & PWRBTN_EN) { |
539 | cf7a2fe2 | aurel32 | pm_state->pmsts |= PWRBTN_EN; |
540 | cf7a2fe2 | aurel32 | pm_update_sci(pm_state); |
541 | cf7a2fe2 | aurel32 | } |
542 | cf7a2fe2 | aurel32 | } |
543 | cf7a2fe2 | aurel32 | #endif |