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/*
2
 * ACPI implementation
3
 *
4
 * Copyright (c) 2006 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
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 * License version 2 as published by the Free Software Foundation.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "hw.h"
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#include "pc.h"
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#include "pci.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "i2c.h"
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#include "smbus.h"
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#include "kvm.h"
27

    
28
//#define DEBUG
29

    
30
/* i82731AB (PIIX4) compatible power management function */
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#define PM_FREQ 3579545
32

    
33
#define ACPI_DBG_IO_ADDR  0xb044
34

    
35
typedef struct PIIX4PMState {
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    PCIDevice dev;
37
    uint16_t pmsts;
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    uint16_t pmen;
39
    uint16_t pmcntrl;
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    uint8_t apmc;
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    uint8_t apms;
42
    QEMUTimer *tmr_timer;
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    int64_t tmr_overflow_time;
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    i2c_bus *smbus;
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    uint8_t smb_stat;
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    uint8_t smb_ctl;
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    uint8_t smb_cmd;
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    uint8_t smb_addr;
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    uint8_t smb_data0;
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    uint8_t smb_data1;
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    uint8_t smb_data[32];
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    uint8_t smb_index;
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    qemu_irq irq;
54
} PIIX4PMState;
55

    
56
#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
58
#define GBL_EN (1 << 5)
59
#define TMROF_EN (1 << 0)
60

    
61
#define SCI_EN (1 << 0)
62

    
63
#define SUS_EN (1 << 13)
64

    
65
#define ACPI_ENABLE 0xf1
66
#define ACPI_DISABLE 0xf0
67

    
68
#define SMBHSTSTS 0x00
69
#define SMBHSTCNT 0x02
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#define SMBHSTCMD 0x03
71
#define SMBHSTADD 0x04
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#define SMBHSTDAT0 0x05
73
#define SMBHSTDAT1 0x06
74
#define SMBBLKDAT 0x07
75

    
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static PIIX4PMState *pm_state;
77

    
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static uint32_t get_pmtmr(PIIX4PMState *s)
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{
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    uint32_t d;
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    d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
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    return d & 0xffffff;
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}
84

    
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static int get_pmsts(PIIX4PMState *s)
86
{
87
    int64_t d;
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    int pmsts;
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    pmsts = s->pmsts;
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    d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
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    if (d >= s->tmr_overflow_time)
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        s->pmsts |= TMROF_EN;
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    return pmsts;
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}
95

    
96
static void pm_update_sci(PIIX4PMState *s)
97
{
98
    int sci_level, pmsts;
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    int64_t expire_time;
100

    
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    pmsts = get_pmsts(s);
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    sci_level = (((pmsts & s->pmen) &
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                  (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
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    qemu_set_irq(s->irq, sci_level);
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    /* schedule a timer interruption if needed */
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    if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
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        expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
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        qemu_mod_timer(s->tmr_timer, expire_time);
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    } else {
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        qemu_del_timer(s->tmr_timer);
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    }
112
}
113

    
114
static void pm_tmr_timer(void *opaque)
115
{
116
    PIIX4PMState *s = opaque;
117
    pm_update_sci(s);
118
}
119

    
120
static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
121
{
122
    PIIX4PMState *s = opaque;
123
    addr &= 0x3f;
124
    switch(addr) {
125
    case 0x00:
126
        {
127
            int64_t d;
128
            int pmsts;
129
            pmsts = get_pmsts(s);
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            if (pmsts & val & TMROF_EN) {
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                /* if TMRSTS is reset, then compute the new overflow time */
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                d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
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                s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
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            }
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            s->pmsts &= ~val;
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            pm_update_sci(s);
137
        }
138
        break;
139
    case 0x02:
140
        s->pmen = val;
141
        pm_update_sci(s);
142
        break;
143
    case 0x04:
144
        {
145
            int sus_typ;
146
            s->pmcntrl = val & ~(SUS_EN);
147
            if (val & SUS_EN) {
148
                /* change suspend type */
149
                sus_typ = (val >> 10) & 7;
150
                switch(sus_typ) {
151
                case 0: /* soft power off */
152
                    qemu_system_shutdown_request();
153
                    break;
154
                default:
155
                    break;
156
                }
157
            }
158
        }
159
        break;
160
    default:
161
        break;
162
    }
163
#ifdef DEBUG
164
    printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
165
#endif
166
}
167

    
168
static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
169
{
170
    PIIX4PMState *s = opaque;
171
    uint32_t val;
172

    
173
    addr &= 0x3f;
174
    switch(addr) {
175
    case 0x00:
176
        val = get_pmsts(s);
177
        break;
178
    case 0x02:
179
        val = s->pmen;
180
        break;
181
    case 0x04:
182
        val = s->pmcntrl;
183
        break;
184
    default:
185
        val = 0;
186
        break;
187
    }
188
#ifdef DEBUG
189
    printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
190
#endif
191
    return val;
192
}
193

    
194
static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
195
{
196
    //    PIIX4PMState *s = opaque;
197
    addr &= 0x3f;
198
#ifdef DEBUG
199
    printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
200
#endif
201
}
202

    
203
static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
204
{
205
    PIIX4PMState *s = opaque;
206
    uint32_t val;
207

    
208
    addr &= 0x3f;
209
    switch(addr) {
210
    case 0x08:
211
        val = get_pmtmr(s);
212
        break;
213
    default:
214
        val = 0;
215
        break;
216
    }
217
#ifdef DEBUG
218
    printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
219
#endif
220
    return val;
221
}
222

    
223
static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
224
{
225
    PIIX4PMState *s = opaque;
226
    addr &= 1;
227
#ifdef DEBUG
228
    printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
229
#endif
230
    if (addr == 0) {
231
        s->apmc = val;
232

    
233
        /* ACPI specs 3.0, 4.7.2.5 */
234
        if (val == ACPI_ENABLE) {
235
            s->pmcntrl |= SCI_EN;
236
        } else if (val == ACPI_DISABLE) {
237
            s->pmcntrl &= ~SCI_EN;
238
        }
239

    
240
        if (s->dev.config[0x5b] & (1 << 1)) {
241
            cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
242
        }
243
    } else {
244
        s->apms = val;
245
    }
246
}
247

    
248
static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
249
{
250
    PIIX4PMState *s = opaque;
251
    uint32_t val;
252

    
253
    addr &= 1;
254
    if (addr == 0) {
255
        val = s->apmc;
256
    } else {
257
        val = s->apms;
258
    }
259
#ifdef DEBUG
260
    printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
261
#endif
262
    return val;
263
}
264

    
265
static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
266
{
267
#if defined(DEBUG)
268
    printf("ACPI: DBG: 0x%08x\n", val);
269
#endif
270
}
271

    
272
static void smb_transaction(PIIX4PMState *s)
273
{
274
    uint8_t prot = (s->smb_ctl >> 2) & 0x07;
275
    uint8_t read = s->smb_addr & 0x01;
276
    uint8_t cmd = s->smb_cmd;
277
    uint8_t addr = s->smb_addr >> 1;
278
    i2c_bus *bus = s->smbus;
279

    
280
#ifdef DEBUG
281
    printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
282
#endif
283
    switch(prot) {
284
    case 0x0:
285
        smbus_quick_command(bus, addr, read);
286
        break;
287
    case 0x1:
288
        if (read) {
289
            s->smb_data0 = smbus_receive_byte(bus, addr);
290
        } else {
291
            smbus_send_byte(bus, addr, cmd);
292
        }
293
        break;
294
    case 0x2:
295
        if (read) {
296
            s->smb_data0 = smbus_read_byte(bus, addr, cmd);
297
        } else {
298
            smbus_write_byte(bus, addr, cmd, s->smb_data0);
299
        }
300
        break;
301
    case 0x3:
302
        if (read) {
303
            uint16_t val;
304
            val = smbus_read_word(bus, addr, cmd);
305
            s->smb_data0 = val;
306
            s->smb_data1 = val >> 8;
307
        } else {
308
            smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
309
        }
310
        break;
311
    case 0x5:
312
        if (read) {
313
            s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
314
        } else {
315
            smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
316
        }
317
        break;
318
    default:
319
        goto error;
320
    }
321
    return;
322

    
323
  error:
324
    s->smb_stat |= 0x04;
325
}
326

    
327
static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
328
{
329
    PIIX4PMState *s = opaque;
330
    addr &= 0x3f;
331
#ifdef DEBUG
332
    printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
333
#endif
334
    switch(addr) {
335
    case SMBHSTSTS:
336
        s->smb_stat = 0;
337
        s->smb_index = 0;
338
        break;
339
    case SMBHSTCNT:
340
        s->smb_ctl = val;
341
        if (val & 0x40)
342
            smb_transaction(s);
343
        break;
344
    case SMBHSTCMD:
345
        s->smb_cmd = val;
346
        break;
347
    case SMBHSTADD:
348
        s->smb_addr = val;
349
        break;
350
    case SMBHSTDAT0:
351
        s->smb_data0 = val;
352
        break;
353
    case SMBHSTDAT1:
354
        s->smb_data1 = val;
355
        break;
356
    case SMBBLKDAT:
357
        s->smb_data[s->smb_index++] = val;
358
        if (s->smb_index > 31)
359
            s->smb_index = 0;
360
        break;
361
    default:
362
        break;
363
    }
364
}
365

    
366
static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
367
{
368
    PIIX4PMState *s = opaque;
369
    uint32_t val;
370

    
371
    addr &= 0x3f;
372
    switch(addr) {
373
    case SMBHSTSTS:
374
        val = s->smb_stat;
375
        break;
376
    case SMBHSTCNT:
377
        s->smb_index = 0;
378
        val = s->smb_ctl & 0x1f;
379
        break;
380
    case SMBHSTCMD:
381
        val = s->smb_cmd;
382
        break;
383
    case SMBHSTADD:
384
        val = s->smb_addr;
385
        break;
386
    case SMBHSTDAT0:
387
        val = s->smb_data0;
388
        break;
389
    case SMBHSTDAT1:
390
        val = s->smb_data1;
391
        break;
392
    case SMBBLKDAT:
393
        val = s->smb_data[s->smb_index++];
394
        if (s->smb_index > 31)
395
            s->smb_index = 0;
396
        break;
397
    default:
398
        val = 0;
399
        break;
400
    }
401
#ifdef DEBUG
402
    printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
403
#endif
404
    return val;
405
}
406

    
407
static void pm_io_space_update(PIIX4PMState *s)
408
{
409
    uint32_t pm_io_base;
410

    
411
    if (s->dev.config[0x80] & 1) {
412
        pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
413
        pm_io_base &= 0xffc0;
414

    
415
        /* XXX: need to improve memory and ioport allocation */
416
#if defined(DEBUG)
417
        printf("PM: mapping to 0x%x\n", pm_io_base);
418
#endif
419
        register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
420
        register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
421
        register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
422
        register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
423
    }
424
}
425

    
426
static void pm_write_config(PCIDevice *d,
427
                            uint32_t address, uint32_t val, int len)
428
{
429
    pci_default_write_config(d, address, val, len);
430
    if (address == 0x80)
431
        pm_io_space_update((PIIX4PMState *)d);
432
}
433

    
434
static void pm_save(QEMUFile* f,void *opaque)
435
{
436
    PIIX4PMState *s = opaque;
437

    
438
    pci_device_save(&s->dev, f);
439

    
440
    qemu_put_be16s(f, &s->pmsts);
441
    qemu_put_be16s(f, &s->pmen);
442
    qemu_put_be16s(f, &s->pmcntrl);
443
    qemu_put_8s(f, &s->apmc);
444
    qemu_put_8s(f, &s->apms);
445
    qemu_put_timer(f, s->tmr_timer);
446
    qemu_put_be64(f, s->tmr_overflow_time);
447
}
448

    
449
static int pm_load(QEMUFile* f,void* opaque,int version_id)
450
{
451
    PIIX4PMState *s = opaque;
452
    int ret;
453

    
454
    if (version_id > 1)
455
        return -EINVAL;
456

    
457
    ret = pci_device_load(&s->dev, f);
458
    if (ret < 0)
459
        return ret;
460

    
461
    qemu_get_be16s(f, &s->pmsts);
462
    qemu_get_be16s(f, &s->pmen);
463
    qemu_get_be16s(f, &s->pmcntrl);
464
    qemu_get_8s(f, &s->apmc);
465
    qemu_get_8s(f, &s->apms);
466
    qemu_get_timer(f, s->tmr_timer);
467
    s->tmr_overflow_time=qemu_get_be64(f);
468

    
469
    pm_io_space_update(s);
470

    
471
    return 0;
472
}
473

    
474
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
475
                       qemu_irq sci_irq)
476
{
477
    PIIX4PMState *s;
478
    uint8_t *pci_conf;
479

    
480
    s = (PIIX4PMState *)pci_register_device(bus,
481
                                         "PM", sizeof(PIIX4PMState),
482
                                         devfn, NULL, pm_write_config);
483
    pm_state = s;
484
    pci_conf = s->dev.config;
485
    pci_conf[0x00] = 0x86;
486
    pci_conf[0x01] = 0x80;
487
    pci_conf[0x02] = 0x13;
488
    pci_conf[0x03] = 0x71;
489
    pci_conf[0x06] = 0x80;
490
    pci_conf[0x07] = 0x02;
491
    pci_conf[0x08] = 0x03; // revision number
492
    pci_conf[0x09] = 0x00;
493
    pci_conf[0x0a] = 0x80; // other bridge device
494
    pci_conf[0x0b] = 0x06; // bridge device
495
    pci_conf[0x0e] = 0x00; // header_type
496
    pci_conf[0x3d] = 0x01; // interrupt pin 1
497

    
498
    pci_conf[0x40] = 0x01; /* PM io base read only bit */
499

    
500
    register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
501
    register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
502

    
503
    register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
504

    
505
    if (kvm_enabled()) {
506
        /* Mark SMM as already inited to prevent SMM from running.  KVM does not
507
         * support SMM mode. */
508
        pci_conf[0x5B] = 0x02;
509
    }
510

    
511
    /* XXX: which specification is used ? The i82731AB has different
512
       mappings */
513
    pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
514
    pci_conf[0x63] = 0x60;
515
    pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
516
        (serial_hds[1] != NULL ? 0x90 : 0);
517

    
518
    pci_conf[0x90] = smb_io_base | 1;
519
    pci_conf[0x91] = smb_io_base >> 8;
520
    pci_conf[0xd2] = 0x09;
521
    register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
522
    register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
523

    
524
    s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
525

    
526
    register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
527

    
528
    s->smbus = i2c_init_bus();
529
    s->irq = sci_irq;
530
    return s->smbus;
531
}
532

    
533
#if defined(TARGET_I386)
534
void qemu_system_powerdown(void)
535
{
536
    if (!pm_state) {
537
        qemu_system_shutdown_request();
538
    } else if (pm_state->pmen & PWRBTN_EN) {
539
        pm_state->pmsts |= PWRBTN_EN;
540
        pm_update_sci(pm_state);
541
    }
542
}
543
#endif