Revision 7bd427d8 hw/pxa2xx.c
| b/hw/pxa2xx.c | ||
|---|---|---|
| 921 | 921 |
|
| 922 | 922 |
static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) |
| 923 | 923 |
{
|
| 924 |
int64_t rt = qemu_get_clock(rt_clock); |
|
| 924 |
int64_t rt = qemu_get_clock_ms(rt_clock);
|
|
| 925 | 925 |
s->last_rcnr += ((rt - s->last_hz) << 15) / |
| 926 | 926 |
(1000 * ((s->rttr & 0xffff) + 1)); |
| 927 | 927 |
s->last_rdcr += ((rt - s->last_hz) << 15) / |
| ... | ... | |
| 931 | 931 |
|
| 932 | 932 |
static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) |
| 933 | 933 |
{
|
| 934 |
int64_t rt = qemu_get_clock(rt_clock); |
|
| 934 |
int64_t rt = qemu_get_clock_ms(rt_clock);
|
|
| 935 | 935 |
if (s->rtsr & (1 << 12)) |
| 936 | 936 |
s->last_swcr += (rt - s->last_sw) / 10; |
| 937 | 937 |
s->last_sw = rt; |
| ... | ... | |
| 939 | 939 |
|
| 940 | 940 |
static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) |
| 941 | 941 |
{
|
| 942 |
int64_t rt = qemu_get_clock(rt_clock); |
|
| 942 |
int64_t rt = qemu_get_clock_ms(rt_clock);
|
|
| 943 | 943 |
if (s->rtsr & (1 << 15)) |
| 944 | 944 |
s->last_swcr += rt - s->last_pi; |
| 945 | 945 |
s->last_pi = rt; |
| ... | ... | |
| 1064 | 1064 |
case PIAR: |
| 1065 | 1065 |
return s->piar; |
| 1066 | 1066 |
case RCNR: |
| 1067 |
return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) / |
|
| 1067 |
return s->last_rcnr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
|
|
| 1068 | 1068 |
(1000 * ((s->rttr & 0xffff) + 1)); |
| 1069 | 1069 |
case RDCR: |
| 1070 |
return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) / |
|
| 1070 |
return s->last_rdcr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
|
|
| 1071 | 1071 |
(1000 * ((s->rttr & 0xffff) + 1)); |
| 1072 | 1072 |
case RYCR: |
| 1073 | 1073 |
return s->last_rycr; |
| 1074 | 1074 |
case SWCR: |
| 1075 | 1075 |
if (s->rtsr & (1 << 12)) |
| 1076 |
return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10; |
|
| 1076 |
return s->last_swcr + (qemu_get_clock_ms(rt_clock) - s->last_sw) / 10;
|
|
| 1077 | 1077 |
else |
| 1078 | 1078 |
return s->last_swcr; |
| 1079 | 1079 |
default: |
| ... | ... | |
| 1219 | 1219 |
s->last_swcr = (tm.tm_hour << 19) | |
| 1220 | 1220 |
(tm.tm_min << 13) | (tm.tm_sec << 7); |
| 1221 | 1221 |
s->last_rtcpicr = 0; |
| 1222 |
s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock); |
|
| 1223 |
|
|
| 1224 |
s->rtc_hz = qemu_new_timer(rt_clock, pxa2xx_rtc_hz_tick, s); |
|
| 1225 |
s->rtc_rdal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal1_tick, s); |
|
| 1226 |
s->rtc_rdal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal2_tick, s); |
|
| 1227 |
s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s); |
|
| 1228 |
s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s); |
|
| 1229 |
s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s); |
|
| 1222 |
s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rt_clock);
|
|
| 1223 |
|
|
| 1224 |
s->rtc_hz = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_hz_tick, s);
|
|
| 1225 |
s->rtc_rdal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal1_tick, s);
|
|
| 1226 |
s->rtc_rdal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal2_tick, s);
|
|
| 1227 |
s->rtc_swal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal1_tick, s);
|
|
| 1228 |
s->rtc_swal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal2_tick, s);
|
|
| 1229 |
s->rtc_pi = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_pi_tick, s);
|
|
| 1230 | 1230 |
|
| 1231 | 1231 |
sysbus_init_irq(dev, &s->rtc_irq); |
| 1232 | 1232 |
|
Also available in: Unified diff