root / op-i386.c @ 7bfdb6d1
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1 | 7bfdb6d1 | bellard | typedef unsigned char uint8_t; |
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2 | 7bfdb6d1 | bellard | typedef unsigned short uint16_t; |
3 | 7bfdb6d1 | bellard | typedef unsigned int uint32_t; |
4 | 7bfdb6d1 | bellard | typedef unsigned long long uint64_t; |
5 | 7bfdb6d1 | bellard | |
6 | 7bfdb6d1 | bellard | typedef signed char int8_t; |
7 | 7bfdb6d1 | bellard | typedef signed short int16_t; |
8 | 7bfdb6d1 | bellard | typedef signed int int32_t; |
9 | 7bfdb6d1 | bellard | typedef signed long long int64_t; |
10 | 7bfdb6d1 | bellard | |
11 | 7bfdb6d1 | bellard | #ifdef __i386__
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12 | 7bfdb6d1 | bellard | register int T0 asm("esi"); |
13 | 7bfdb6d1 | bellard | register int T1 asm("ebx"); |
14 | 7bfdb6d1 | bellard | register int A0 asm("edi"); |
15 | 7bfdb6d1 | bellard | register struct CPU86State *env asm("ebp"); |
16 | 7bfdb6d1 | bellard | #define FORCE_RET() asm volatile ("ret"); |
17 | 7bfdb6d1 | bellard | #endif
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18 | 7bfdb6d1 | bellard | #ifdef __powerpc__
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19 | 7bfdb6d1 | bellard | register int T0 asm("r24"); |
20 | 7bfdb6d1 | bellard | register int T1 asm("r25"); |
21 | 7bfdb6d1 | bellard | register int A0 asm("r26"); |
22 | 7bfdb6d1 | bellard | register struct CPU86State *env asm("r27"); |
23 | 7bfdb6d1 | bellard | #define FORCE_RET() asm volatile ("blr"); |
24 | 7bfdb6d1 | bellard | #endif
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25 | 7bfdb6d1 | bellard | #ifdef __arm__
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26 | 7bfdb6d1 | bellard | register int T0 asm("r4"); |
27 | 7bfdb6d1 | bellard | register int T1 asm("r5"); |
28 | 7bfdb6d1 | bellard | register int A0 asm("r6"); |
29 | 7bfdb6d1 | bellard | register struct CPU86State *env asm("r7"); |
30 | 7bfdb6d1 | bellard | #define FORCE_RET() asm volatile ("mov pc, lr"); |
31 | 7bfdb6d1 | bellard | #endif
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32 | 7bfdb6d1 | bellard | #ifdef __mips__
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33 | 7bfdb6d1 | bellard | register int T0 asm("s0"); |
34 | 7bfdb6d1 | bellard | register int T1 asm("s1"); |
35 | 7bfdb6d1 | bellard | register int A0 asm("s2"); |
36 | 7bfdb6d1 | bellard | register struct CPU86State *env asm("s3"); |
37 | 7bfdb6d1 | bellard | #define FORCE_RET() asm volatile ("jr $31"); |
38 | 7bfdb6d1 | bellard | #endif
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39 | 7bfdb6d1 | bellard | #ifdef __sparc__
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40 | 7bfdb6d1 | bellard | register int T0 asm("l0"); |
41 | 7bfdb6d1 | bellard | register int T1 asm("l1"); |
42 | 7bfdb6d1 | bellard | register int A0 asm("l2"); |
43 | 7bfdb6d1 | bellard | register struct CPU86State *env asm("l3"); |
44 | 7bfdb6d1 | bellard | #define FORCE_RET() asm volatile ("retl ; nop"); |
45 | 7bfdb6d1 | bellard | #endif
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46 | 7bfdb6d1 | bellard | |
47 | 7bfdb6d1 | bellard | #ifndef OPPROTO
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48 | 7bfdb6d1 | bellard | #define OPPROTO
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49 | 7bfdb6d1 | bellard | #endif
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50 | 7bfdb6d1 | bellard | |
51 | 7bfdb6d1 | bellard | #define xglue(x, y) x ## y |
52 | 7bfdb6d1 | bellard | #define glue(x, y) xglue(x, y)
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53 | 7bfdb6d1 | bellard | |
54 | 7bfdb6d1 | bellard | #define EAX (env->regs[R_EAX])
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55 | 7bfdb6d1 | bellard | #define ECX (env->regs[R_ECX])
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56 | 7bfdb6d1 | bellard | #define EDX (env->regs[R_EDX])
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57 | 7bfdb6d1 | bellard | #define EBX (env->regs[R_EBX])
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58 | 7bfdb6d1 | bellard | #define ESP (env->regs[R_ESP])
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59 | 7bfdb6d1 | bellard | #define EBP (env->regs[R_EBP])
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60 | 7bfdb6d1 | bellard | #define ESI (env->regs[R_ESI])
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61 | 7bfdb6d1 | bellard | #define EDI (env->regs[R_EDI])
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62 | 7bfdb6d1 | bellard | #define PC (env->pc)
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63 | 7bfdb6d1 | bellard | #define DF (env->df)
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64 | 7bfdb6d1 | bellard | |
65 | 7bfdb6d1 | bellard | #define CC_SRC (env->cc_src)
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66 | 7bfdb6d1 | bellard | #define CC_DST (env->cc_dst)
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67 | 7bfdb6d1 | bellard | #define CC_OP (env->cc_op)
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68 | 7bfdb6d1 | bellard | |
69 | 7bfdb6d1 | bellard | extern int __op_param1, __op_param2, __op_param3; |
70 | 7bfdb6d1 | bellard | #define PARAM1 ((long)(&__op_param1)) |
71 | 7bfdb6d1 | bellard | #define PARAM2 ((long)(&__op_param2)) |
72 | 7bfdb6d1 | bellard | #define PARAM3 ((long)(&__op_param3)) |
73 | 7bfdb6d1 | bellard | |
74 | 7bfdb6d1 | bellard | #include "cpu-i386.h" |
75 | 7bfdb6d1 | bellard | |
76 | 7bfdb6d1 | bellard | typedef struct CCTable { |
77 | 7bfdb6d1 | bellard | int (*compute_c)(void); /* return the C flag */ |
78 | 7bfdb6d1 | bellard | int (*compute_z)(void); /* return the Z flag */ |
79 | 7bfdb6d1 | bellard | int (*compute_s)(void); /* return the S flag */ |
80 | 7bfdb6d1 | bellard | int (*compute_o)(void); /* return the O flag */ |
81 | 7bfdb6d1 | bellard | int (*compute_all)(void); /* return all the flags */ |
82 | 7bfdb6d1 | bellard | } CCTable; |
83 | 7bfdb6d1 | bellard | |
84 | 7bfdb6d1 | bellard | uint8_t parity_table[256] = {
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85 | 7bfdb6d1 | bellard | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, |
86 | 7bfdb6d1 | bellard | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, |
87 | 7bfdb6d1 | bellard | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, |
88 | 7bfdb6d1 | bellard | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, |
89 | 7bfdb6d1 | bellard | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, |
90 | 7bfdb6d1 | bellard | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, |
91 | 7bfdb6d1 | bellard | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, |
92 | 7bfdb6d1 | bellard | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, |
93 | 7bfdb6d1 | bellard | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, |
94 | 7bfdb6d1 | bellard | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, |
95 | 7bfdb6d1 | bellard | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, |
96 | 7bfdb6d1 | bellard | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, |
97 | 7bfdb6d1 | bellard | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, |
98 | 7bfdb6d1 | bellard | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, |
99 | 7bfdb6d1 | bellard | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, |
100 | 7bfdb6d1 | bellard | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, |
101 | 7bfdb6d1 | bellard | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, |
102 | 7bfdb6d1 | bellard | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, |
103 | 7bfdb6d1 | bellard | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, |
104 | 7bfdb6d1 | bellard | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, |
105 | 7bfdb6d1 | bellard | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, |
106 | 7bfdb6d1 | bellard | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, |
107 | 7bfdb6d1 | bellard | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, |
108 | 7bfdb6d1 | bellard | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, |
109 | 7bfdb6d1 | bellard | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, |
110 | 7bfdb6d1 | bellard | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, |
111 | 7bfdb6d1 | bellard | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, |
112 | 7bfdb6d1 | bellard | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, |
113 | 7bfdb6d1 | bellard | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, |
114 | 7bfdb6d1 | bellard | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, |
115 | 7bfdb6d1 | bellard | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, |
116 | 7bfdb6d1 | bellard | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, |
117 | 7bfdb6d1 | bellard | }; |
118 | 7bfdb6d1 | bellard | |
119 | 7bfdb6d1 | bellard | static int compute_eflags_all(void) |
120 | 7bfdb6d1 | bellard | { |
121 | 7bfdb6d1 | bellard | return CC_SRC;
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122 | 7bfdb6d1 | bellard | } |
123 | 7bfdb6d1 | bellard | |
124 | 7bfdb6d1 | bellard | static int compute_eflags_addb(void) |
125 | 7bfdb6d1 | bellard | { |
126 | 7bfdb6d1 | bellard | int cf, pf, af, zf, sf, of;
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127 | 7bfdb6d1 | bellard | int src1, src2;
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128 | 7bfdb6d1 | bellard | src1 = CC_SRC; |
129 | 7bfdb6d1 | bellard | src2 = CC_DST - CC_SRC; |
130 | 7bfdb6d1 | bellard | cf = (uint8_t)CC_DST < (uint8_t)src1; |
131 | 7bfdb6d1 | bellard | pf = parity_table[(uint8_t)CC_DST]; |
132 | 7bfdb6d1 | bellard | af = (CC_DST ^ src1 ^ src2) & 0x10;
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133 | 7bfdb6d1 | bellard | zf = ((uint8_t)CC_DST != 0) << 6; |
134 | 7bfdb6d1 | bellard | sf = CC_DST & 0x80;
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135 | 7bfdb6d1 | bellard | of = ((src1 ^ src2 ^ -1) & (src1 ^ CC_DST) & 0x80) << 4; |
136 | 7bfdb6d1 | bellard | return cf | pf | af | zf | sf | of;
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137 | 7bfdb6d1 | bellard | } |
138 | 7bfdb6d1 | bellard | |
139 | 7bfdb6d1 | bellard | static int compute_eflags_subb(void) |
140 | 7bfdb6d1 | bellard | { |
141 | 7bfdb6d1 | bellard | int cf, pf, af, zf, sf, of;
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142 | 7bfdb6d1 | bellard | int src1, src2;
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143 | 7bfdb6d1 | bellard | src1 = CC_SRC; |
144 | 7bfdb6d1 | bellard | src2 = CC_SRC - CC_DST; |
145 | 7bfdb6d1 | bellard | cf = (uint8_t)src1 < (uint8_t)src2; |
146 | 7bfdb6d1 | bellard | pf = parity_table[(uint8_t)CC_DST]; |
147 | 7bfdb6d1 | bellard | af = (CC_DST ^ src1 ^ src2) & 0x10;
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148 | 7bfdb6d1 | bellard | zf = ((uint8_t)CC_DST != 0) << 6; |
149 | 7bfdb6d1 | bellard | sf = CC_DST & 0x80;
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150 | 7bfdb6d1 | bellard | of = ((src1 ^ src2 ^ -1) & (src1 ^ CC_DST) & 0x80) << 4; |
151 | 7bfdb6d1 | bellard | return cf | pf | af | zf | sf | of;
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152 | 7bfdb6d1 | bellard | } |
153 | 7bfdb6d1 | bellard | |
154 | 7bfdb6d1 | bellard | static int compute_eflags_logicb(void) |
155 | 7bfdb6d1 | bellard | { |
156 | 7bfdb6d1 | bellard | cf = 0;
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157 | 7bfdb6d1 | bellard | pf = parity_table[(uint8_t)CC_DST]; |
158 | 7bfdb6d1 | bellard | af = 0;
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159 | 7bfdb6d1 | bellard | zf = ((uint8_t)CC_DST != 0) << 6; |
160 | 7bfdb6d1 | bellard | sf = CC_DST & 0x80;
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161 | 7bfdb6d1 | bellard | of = 0;
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162 | 7bfdb6d1 | bellard | return cf | pf | af | zf | sf | of;
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163 | 7bfdb6d1 | bellard | } |
164 | 7bfdb6d1 | bellard | |
165 | 7bfdb6d1 | bellard | static int compute_eflags_incb(void) |
166 | 7bfdb6d1 | bellard | { |
167 | 7bfdb6d1 | bellard | int cf, pf, af, zf, sf, of;
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168 | 7bfdb6d1 | bellard | int src2;
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169 | 7bfdb6d1 | bellard | src1 = CC_DST - 1;
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170 | 7bfdb6d1 | bellard | src2 = 1;
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171 | 7bfdb6d1 | bellard | cf = CC_SRC; |
172 | 7bfdb6d1 | bellard | pf = parity_table[(uint8_t)CC_DST]; |
173 | 7bfdb6d1 | bellard | af = (CC_DST ^ src1 ^ src2) & 0x10;
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174 | 7bfdb6d1 | bellard | zf = ((uint8_t)CC_DST != 0) << 6; |
175 | 7bfdb6d1 | bellard | sf = CC_DST & 0x80;
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176 | 7bfdb6d1 | bellard | of = ((src1 ^ src2 ^ -1) & (src1 ^ CC_DST) & 0x80) << 4; |
177 | 7bfdb6d1 | bellard | return cf | pf | af | zf | sf | of;
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178 | 7bfdb6d1 | bellard | } |
179 | 7bfdb6d1 | bellard | |
180 | 7bfdb6d1 | bellard | static int compute_eflags_decb(void) |
181 | 7bfdb6d1 | bellard | { |
182 | 7bfdb6d1 | bellard | int cf, pf, af, zf, sf, of;
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183 | 7bfdb6d1 | bellard | int src1, src2;
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184 | 7bfdb6d1 | bellard | src1 = CC_DST + 1;
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185 | 7bfdb6d1 | bellard | src2 = 1;
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186 | 7bfdb6d1 | bellard | cf = (uint8_t)src1 < (uint8_t)src2; |
187 | 7bfdb6d1 | bellard | pf = parity_table[(uint8_t)CC_DST]; |
188 | 7bfdb6d1 | bellard | af = (CC_DST ^ src1 ^ src2) & 0x10;
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189 | 7bfdb6d1 | bellard | zf = ((uint8_t)CC_DST != 0) << 6; |
190 | 7bfdb6d1 | bellard | sf = CC_DST & 0x80;
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191 | 7bfdb6d1 | bellard | of = ((src1 ^ src2 ^ -1) & (src1 ^ CC_DST) & 0x80) << 4; |
192 | 7bfdb6d1 | bellard | return cf | pf | af | zf | sf | of;
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193 | 7bfdb6d1 | bellard | } |
194 | 7bfdb6d1 | bellard | |
195 | 7bfdb6d1 | bellard | static int compute_eflags_shlb(void) |
196 | 7bfdb6d1 | bellard | { |
197 | 7bfdb6d1 | bellard | cf = CC_SRC; |
198 | 7bfdb6d1 | bellard | pf = parity_table[(uint8_t)CC_DST]; |
199 | 7bfdb6d1 | bellard | af = 0; /* undefined */ |
200 | 7bfdb6d1 | bellard | zf = ((uint8_t)CC_DST != 0) << 6; |
201 | 7bfdb6d1 | bellard | sf = CC_DST & 0x80;
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202 | 7bfdb6d1 | bellard | of = 0; /* undefined */ |
203 | 7bfdb6d1 | bellard | return cf | pf | af | zf | sf | of;
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204 | 7bfdb6d1 | bellard | } |
205 | 7bfdb6d1 | bellard | |
206 | 7bfdb6d1 | bellard | static int compute_eflags_shrb(void) |
207 | 7bfdb6d1 | bellard | { |
208 | 7bfdb6d1 | bellard | cf = CC_SRC & 1;
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209 | 7bfdb6d1 | bellard | pf = parity_table[(uint8_t)CC_DST]; |
210 | 7bfdb6d1 | bellard | af = 0; /* undefined */ |
211 | 7bfdb6d1 | bellard | zf = ((uint8_t)CC_DST != 0) << 6; |
212 | 7bfdb6d1 | bellard | sf = CC_DST & 0x80;
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213 | 7bfdb6d1 | bellard | of = sf << 4;
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214 | 7bfdb6d1 | bellard | return cf | pf | af | zf | sf | of;
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215 | 7bfdb6d1 | bellard | } |
216 | 7bfdb6d1 | bellard | |
217 | 7bfdb6d1 | bellard | static int compute_eflags_mul(void) |
218 | 7bfdb6d1 | bellard | { |
219 | 7bfdb6d1 | bellard | cf = (CC_SRC != 0);
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220 | 7bfdb6d1 | bellard | pf = 0; /* undefined */ |
221 | 7bfdb6d1 | bellard | af = 0; /* undefined */ |
222 | 7bfdb6d1 | bellard | zf = 0; /* undefined */ |
223 | 7bfdb6d1 | bellard | sf = 0; /* undefined */ |
224 | 7bfdb6d1 | bellard | of = cf << 11;
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225 | 7bfdb6d1 | bellard | return cf | pf | af | zf | sf | of;
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226 | 7bfdb6d1 | bellard | } |
227 | 7bfdb6d1 | bellard | |
228 | 7bfdb6d1 | bellard | CTable cc_table[CC_OP_NB] = { |
229 | 7bfdb6d1 | bellard | [CC_OP_DYNAMIC] = { NULL, NULL, NULL }, |
230 | 7bfdb6d1 | bellard | [CC_OP_EFLAGS] = { NULL, NULL, NULL }, |
231 | 7bfdb6d1 | bellard | |
232 | 7bfdb6d1 | bellard | }; |
233 | 7bfdb6d1 | bellard | |
234 | 7bfdb6d1 | bellard | /* we define the various pieces of code used by the JIT */
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235 | 7bfdb6d1 | bellard | |
236 | 7bfdb6d1 | bellard | #define REG EAX
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237 | 7bfdb6d1 | bellard | #define REGNAME _EAX
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238 | 7bfdb6d1 | bellard | #include "opreg_template.h" |
239 | 7bfdb6d1 | bellard | #undef REG
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240 | 7bfdb6d1 | bellard | #undef REGNAME
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241 | 7bfdb6d1 | bellard | |
242 | 7bfdb6d1 | bellard | #define REG ECX
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243 | 7bfdb6d1 | bellard | #define REGNAME _ECX
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244 | 7bfdb6d1 | bellard | #include "opreg_template.h" |
245 | 7bfdb6d1 | bellard | #undef REG
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246 | 7bfdb6d1 | bellard | #undef REGNAME
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247 | 7bfdb6d1 | bellard | |
248 | 7bfdb6d1 | bellard | #define REG EDX
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249 | 7bfdb6d1 | bellard | #define REGNAME _EDX
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250 | 7bfdb6d1 | bellard | #include "opreg_template.h" |
251 | 7bfdb6d1 | bellard | #undef REG
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252 | 7bfdb6d1 | bellard | #undef REGNAME
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253 | 7bfdb6d1 | bellard | |
254 | 7bfdb6d1 | bellard | #define REG EBX
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255 | 7bfdb6d1 | bellard | #define REGNAME _EBX
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256 | 7bfdb6d1 | bellard | #include "opreg_template.h" |
257 | 7bfdb6d1 | bellard | #undef REG
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258 | 7bfdb6d1 | bellard | #undef REGNAME
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259 | 7bfdb6d1 | bellard | |
260 | 7bfdb6d1 | bellard | #define REG ESP
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261 | 7bfdb6d1 | bellard | #define REGNAME _ESP
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262 | 7bfdb6d1 | bellard | #include "opreg_template.h" |
263 | 7bfdb6d1 | bellard | #undef REG
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264 | 7bfdb6d1 | bellard | #undef REGNAME
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265 | 7bfdb6d1 | bellard | |
266 | 7bfdb6d1 | bellard | #define REG EBP
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267 | 7bfdb6d1 | bellard | #define REGNAME _EBP
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268 | 7bfdb6d1 | bellard | #include "opreg_template.h" |
269 | 7bfdb6d1 | bellard | #undef REG
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270 | 7bfdb6d1 | bellard | #undef REGNAME
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271 | 7bfdb6d1 | bellard | |
272 | 7bfdb6d1 | bellard | #define REG ESI
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273 | 7bfdb6d1 | bellard | #define REGNAME _ESI
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274 | 7bfdb6d1 | bellard | #include "opreg_template.h" |
275 | 7bfdb6d1 | bellard | #undef REG
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276 | 7bfdb6d1 | bellard | #undef REGNAME
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277 | 7bfdb6d1 | bellard | |
278 | 7bfdb6d1 | bellard | #define REG EDI
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279 | 7bfdb6d1 | bellard | #define REGNAME _EDI
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280 | 7bfdb6d1 | bellard | #include "opreg_template.h" |
281 | 7bfdb6d1 | bellard | #undef REG
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282 | 7bfdb6d1 | bellard | #undef REGNAME
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283 | 7bfdb6d1 | bellard | |
284 | 7bfdb6d1 | bellard | /* operations */
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285 | 7bfdb6d1 | bellard | |
286 | 7bfdb6d1 | bellard | void OPPROTO op_addl_T0_T1_cc(void) |
287 | 7bfdb6d1 | bellard | { |
288 | 7bfdb6d1 | bellard | CC_SRC = T0; |
289 | 7bfdb6d1 | bellard | T0 += T1; |
290 | 7bfdb6d1 | bellard | CC_DST = T0; |
291 | 7bfdb6d1 | bellard | } |
292 | 7bfdb6d1 | bellard | |
293 | 7bfdb6d1 | bellard | void OPPROTO op_orl_T0_T1_cc(void) |
294 | 7bfdb6d1 | bellard | { |
295 | 7bfdb6d1 | bellard | T0 |= T1; |
296 | 7bfdb6d1 | bellard | CC_DST = T0; |
297 | 7bfdb6d1 | bellard | } |
298 | 7bfdb6d1 | bellard | |
299 | 7bfdb6d1 | bellard | void OPPROTO op_adcl_T0_T1_cc(void) |
300 | 7bfdb6d1 | bellard | { |
301 | 7bfdb6d1 | bellard | CC_SRC = T0; |
302 | 7bfdb6d1 | bellard | T0 = T0 + T1 + cc_table[CC_OP].compute_c(); |
303 | 7bfdb6d1 | bellard | CC_DST = T0; |
304 | 7bfdb6d1 | bellard | } |
305 | 7bfdb6d1 | bellard | |
306 | 7bfdb6d1 | bellard | void OPPROTO op_sbbl_T0_T1_cc(void) |
307 | 7bfdb6d1 | bellard | { |
308 | 7bfdb6d1 | bellard | CC_SRC = T0; |
309 | 7bfdb6d1 | bellard | T0 = T0 - T1 - cc_table[CC_OP].compute_c(); |
310 | 7bfdb6d1 | bellard | CC_DST = T0; |
311 | 7bfdb6d1 | bellard | } |
312 | 7bfdb6d1 | bellard | |
313 | 7bfdb6d1 | bellard | void OPPROTO op_andl_T0_T1_cc(void) |
314 | 7bfdb6d1 | bellard | { |
315 | 7bfdb6d1 | bellard | T0 &= T1; |
316 | 7bfdb6d1 | bellard | CC_DST = T0; |
317 | 7bfdb6d1 | bellard | } |
318 | 7bfdb6d1 | bellard | |
319 | 7bfdb6d1 | bellard | void OPPROTO op_subl_T0_T1_cc(void) |
320 | 7bfdb6d1 | bellard | { |
321 | 7bfdb6d1 | bellard | CC_SRC = T0; |
322 | 7bfdb6d1 | bellard | T0 -= T1; |
323 | 7bfdb6d1 | bellard | CC_DST = T0; |
324 | 7bfdb6d1 | bellard | } |
325 | 7bfdb6d1 | bellard | |
326 | 7bfdb6d1 | bellard | void OPPROTO op_xorl_T0_T1_cc(void) |
327 | 7bfdb6d1 | bellard | { |
328 | 7bfdb6d1 | bellard | T0 ^= T1; |
329 | 7bfdb6d1 | bellard | CC_DST = T0; |
330 | 7bfdb6d1 | bellard | } |
331 | 7bfdb6d1 | bellard | |
332 | 7bfdb6d1 | bellard | void OPPROTO op_cmpl_T0_T1_cc(void) |
333 | 7bfdb6d1 | bellard | { |
334 | 7bfdb6d1 | bellard | CC_SRC = T0; |
335 | 7bfdb6d1 | bellard | CC_DST = T0 - T1; |
336 | 7bfdb6d1 | bellard | } |
337 | 7bfdb6d1 | bellard | |
338 | 7bfdb6d1 | bellard | void OPPROTO op_notl_T0(void) |
339 | 7bfdb6d1 | bellard | { |
340 | 7bfdb6d1 | bellard | T0 = ~T0; |
341 | 7bfdb6d1 | bellard | } |
342 | 7bfdb6d1 | bellard | |
343 | 7bfdb6d1 | bellard | void OPPROTO op_negl_T0_cc(void) |
344 | 7bfdb6d1 | bellard | { |
345 | 7bfdb6d1 | bellard | CC_SRC = 0;
|
346 | 7bfdb6d1 | bellard | T0 = -T0; |
347 | 7bfdb6d1 | bellard | CC_DST = T0; |
348 | 7bfdb6d1 | bellard | } |
349 | 7bfdb6d1 | bellard | |
350 | 7bfdb6d1 | bellard | void OPPROTO op_incl_T0_cc(void) |
351 | 7bfdb6d1 | bellard | { |
352 | 7bfdb6d1 | bellard | T0++; |
353 | 7bfdb6d1 | bellard | CC_DST = T0; |
354 | 7bfdb6d1 | bellard | } |
355 | 7bfdb6d1 | bellard | |
356 | 7bfdb6d1 | bellard | void OPPROTO op_decl_T0_cc(void) |
357 | 7bfdb6d1 | bellard | { |
358 | 7bfdb6d1 | bellard | T0--; |
359 | 7bfdb6d1 | bellard | CC_DST = T0; |
360 | 7bfdb6d1 | bellard | } |
361 | 7bfdb6d1 | bellard | |
362 | 7bfdb6d1 | bellard | void OPPROTO op_testl_T0_T1_cc(void) |
363 | 7bfdb6d1 | bellard | { |
364 | 7bfdb6d1 | bellard | CC_SRC = T0; |
365 | 7bfdb6d1 | bellard | CC_DST = T0 & T1; |
366 | 7bfdb6d1 | bellard | } |
367 | 7bfdb6d1 | bellard | |
368 | 7bfdb6d1 | bellard | /* shifts */
|
369 | 7bfdb6d1 | bellard | |
370 | 7bfdb6d1 | bellard | void OPPROTO op_roll_T0_T1_cc(void) |
371 | 7bfdb6d1 | bellard | { |
372 | 7bfdb6d1 | bellard | int count;
|
373 | 7bfdb6d1 | bellard | count = T1 & 0x1f;
|
374 | 7bfdb6d1 | bellard | if (count) {
|
375 | 7bfdb6d1 | bellard | CC_SRC = T0; |
376 | 7bfdb6d1 | bellard | T0 = (T0 << count) | (T0 >> (32 - count));
|
377 | 7bfdb6d1 | bellard | CC_DST = T0; |
378 | 7bfdb6d1 | bellard | CC_OP = CC_OP_ROLL; |
379 | 7bfdb6d1 | bellard | } |
380 | 7bfdb6d1 | bellard | } |
381 | 7bfdb6d1 | bellard | |
382 | 7bfdb6d1 | bellard | void OPPROTO op_rolw_T0_T1_cc(void) |
383 | 7bfdb6d1 | bellard | { |
384 | 7bfdb6d1 | bellard | int count;
|
385 | 7bfdb6d1 | bellard | count = T1 & 0xf;
|
386 | 7bfdb6d1 | bellard | if (count) {
|
387 | 7bfdb6d1 | bellard | T0 = T0 & 0xffff;
|
388 | 7bfdb6d1 | bellard | CC_SRC = T0; |
389 | 7bfdb6d1 | bellard | T0 = (T0 << count) | (T0 >> (16 - count));
|
390 | 7bfdb6d1 | bellard | CC_DST = T0; |
391 | 7bfdb6d1 | bellard | CC_OP = CC_OP_ROLW; |
392 | 7bfdb6d1 | bellard | } |
393 | 7bfdb6d1 | bellard | } |
394 | 7bfdb6d1 | bellard | |
395 | 7bfdb6d1 | bellard | void OPPROTO op_rolb_T0_T1_cc(void) |
396 | 7bfdb6d1 | bellard | { |
397 | 7bfdb6d1 | bellard | int count;
|
398 | 7bfdb6d1 | bellard | count = T1 & 0x7;
|
399 | 7bfdb6d1 | bellard | if (count) {
|
400 | 7bfdb6d1 | bellard | T0 = T0 & 0xff;
|
401 | 7bfdb6d1 | bellard | CC_SRC = T0; |
402 | 7bfdb6d1 | bellard | T0 = (T0 << count) | (T0 >> (8 - count));
|
403 | 7bfdb6d1 | bellard | CC_DST = T0; |
404 | 7bfdb6d1 | bellard | CC_OP = CC_OP_ROLB; |
405 | 7bfdb6d1 | bellard | } |
406 | 7bfdb6d1 | bellard | } |
407 | 7bfdb6d1 | bellard | |
408 | 7bfdb6d1 | bellard | void OPPROTO op_rorl_T0_T1_cc(void) |
409 | 7bfdb6d1 | bellard | { |
410 | 7bfdb6d1 | bellard | int count;
|
411 | 7bfdb6d1 | bellard | count = T1 & 0x1f;
|
412 | 7bfdb6d1 | bellard | if (count) {
|
413 | 7bfdb6d1 | bellard | CC_SRC = T0; |
414 | 7bfdb6d1 | bellard | T0 = (T0 >> count) | (T0 << (32 - count));
|
415 | 7bfdb6d1 | bellard | CC_DST = T0; |
416 | 7bfdb6d1 | bellard | CC_OP = CC_OP_RORB; |
417 | 7bfdb6d1 | bellard | } |
418 | 7bfdb6d1 | bellard | } |
419 | 7bfdb6d1 | bellard | |
420 | 7bfdb6d1 | bellard | void OPPROTO op_rorw_T0_T1_cc(void) |
421 | 7bfdb6d1 | bellard | { |
422 | 7bfdb6d1 | bellard | int count;
|
423 | 7bfdb6d1 | bellard | count = T1 & 0xf;
|
424 | 7bfdb6d1 | bellard | if (count) {
|
425 | 7bfdb6d1 | bellard | CC_SRC = T0; |
426 | 7bfdb6d1 | bellard | T0 = (T0 >> count) | (T0 << (16 - count));
|
427 | 7bfdb6d1 | bellard | CC_DST = T0; |
428 | 7bfdb6d1 | bellard | CC_OP = CC_OP_RORW; |
429 | 7bfdb6d1 | bellard | } |
430 | 7bfdb6d1 | bellard | } |
431 | 7bfdb6d1 | bellard | |
432 | 7bfdb6d1 | bellard | void OPPROTO op_rorb_T0_T1_cc(void) |
433 | 7bfdb6d1 | bellard | { |
434 | 7bfdb6d1 | bellard | int count;
|
435 | 7bfdb6d1 | bellard | count = T1 & 0x7;
|
436 | 7bfdb6d1 | bellard | if (count) {
|
437 | 7bfdb6d1 | bellard | CC_SRC = T0; |
438 | 7bfdb6d1 | bellard | T0 = (T0 >> count) | (T0 << (8 - count));
|
439 | 7bfdb6d1 | bellard | CC_DST = T0; |
440 | 7bfdb6d1 | bellard | CC_OP = CC_OP_RORL; |
441 | 7bfdb6d1 | bellard | } |
442 | 7bfdb6d1 | bellard | } |
443 | 7bfdb6d1 | bellard | |
444 | 7bfdb6d1 | bellard | /* modulo 17 table */
|
445 | 7bfdb6d1 | bellard | const uint8_t rclw_table[32] = { |
446 | 7bfdb6d1 | bellard | 0, 1, 2, 3, 4, 5, 6, 7, |
447 | 7bfdb6d1 | bellard | 8, 9,10,11,12,13,14,15, |
448 | 7bfdb6d1 | bellard | 16, 0, 1, 2, 3, 4, 5, 6, |
449 | 7bfdb6d1 | bellard | 7, 8, 9,10,11,12,13,14, |
450 | 7bfdb6d1 | bellard | }; |
451 | 7bfdb6d1 | bellard | |
452 | 7bfdb6d1 | bellard | /* modulo 9 table */
|
453 | 7bfdb6d1 | bellard | const uint8_t rclb_table[32] = { |
454 | 7bfdb6d1 | bellard | 0, 1, 2, 3, 4, 5, 6, 7, |
455 | 7bfdb6d1 | bellard | 8, 0, 1, 2, 3, 4, 5, 6, |
456 | 7bfdb6d1 | bellard | 7, 8, 0, 1, 2, 3, 4, 5, |
457 | 7bfdb6d1 | bellard | 6, 7, 8, 0, 1, 2, 3, 4, |
458 | 7bfdb6d1 | bellard | }; |
459 | 7bfdb6d1 | bellard | |
460 | 7bfdb6d1 | bellard | void helper_rcll_T0_T1_cc(void) |
461 | 7bfdb6d1 | bellard | { |
462 | 7bfdb6d1 | bellard | int count, res;
|
463 | 7bfdb6d1 | bellard | |
464 | 7bfdb6d1 | bellard | count = T1 & 0x1f;
|
465 | 7bfdb6d1 | bellard | if (count) {
|
466 | 7bfdb6d1 | bellard | CC_SRC = T0; |
467 | 7bfdb6d1 | bellard | res = (T0 << count) | (cc_table[CC_OP].compute_c() << (count - 1));
|
468 | 7bfdb6d1 | bellard | if (count > 1) |
469 | 7bfdb6d1 | bellard | res |= T0 >> (33 - count);
|
470 | 7bfdb6d1 | bellard | T0 = res; |
471 | 7bfdb6d1 | bellard | CC_DST = T0 ^ CC_SRC; /* O is in bit 31 */
|
472 | 7bfdb6d1 | bellard | CC_SRC >>= (32 - count); /* CC is in bit 0 */ |
473 | 7bfdb6d1 | bellard | CC_OP = CC_OP_RCLL; |
474 | 7bfdb6d1 | bellard | } |
475 | 7bfdb6d1 | bellard | } |
476 | 7bfdb6d1 | bellard | |
477 | 7bfdb6d1 | bellard | void OPPROTO op_rcll_T0_T1_cc(void) |
478 | 7bfdb6d1 | bellard | { |
479 | 7bfdb6d1 | bellard | helper_rcll_T0_T1_cc(); |
480 | 7bfdb6d1 | bellard | } |
481 | 7bfdb6d1 | bellard | |
482 | 7bfdb6d1 | bellard | void OPPROTO op_rclw_T0_T1_cc(void) |
483 | 7bfdb6d1 | bellard | { |
484 | 7bfdb6d1 | bellard | int count;
|
485 | 7bfdb6d1 | bellard | count = rclw_table[T1 & 0x1f];
|
486 | 7bfdb6d1 | bellard | if (count) {
|
487 | 7bfdb6d1 | bellard | T0 = T0 & 0xffff;
|
488 | 7bfdb6d1 | bellard | CC_SRC = T0; |
489 | 7bfdb6d1 | bellard | T0 = (T0 << count) | (cc_table[CC_OP].compute_c() << (count - 1)) |
|
490 | 7bfdb6d1 | bellard | (T0 >> (17 - count));
|
491 | 7bfdb6d1 | bellard | CC_DST = T0 ^ CC_SRC; |
492 | 7bfdb6d1 | bellard | CC_SRC >>= (16 - count);
|
493 | 7bfdb6d1 | bellard | CC_OP = CC_OP_RCLW; |
494 | 7bfdb6d1 | bellard | } |
495 | 7bfdb6d1 | bellard | } |
496 | 7bfdb6d1 | bellard | |
497 | 7bfdb6d1 | bellard | void OPPROTO op_rclb_T0_T1_cc(void) |
498 | 7bfdb6d1 | bellard | { |
499 | 7bfdb6d1 | bellard | int count;
|
500 | 7bfdb6d1 | bellard | count = rclb_table[T1 & 0x1f];
|
501 | 7bfdb6d1 | bellard | if (count) {
|
502 | 7bfdb6d1 | bellard | T0 = T0 & 0xff;
|
503 | 7bfdb6d1 | bellard | CC_SRC = T0; |
504 | 7bfdb6d1 | bellard | T0 = (T0 << count) | (cc_table[CC_OP].compute_c() << (count - 1)) |
|
505 | 7bfdb6d1 | bellard | (T0 >> (9 - count));
|
506 | 7bfdb6d1 | bellard | CC_DST = T0 ^ CC_SRC; |
507 | 7bfdb6d1 | bellard | CC_SRC >>= (8 - count);
|
508 | 7bfdb6d1 | bellard | CC_OP = CC_OP_RCLB; |
509 | 7bfdb6d1 | bellard | } |
510 | 7bfdb6d1 | bellard | } |
511 | 7bfdb6d1 | bellard | |
512 | 7bfdb6d1 | bellard | void OPPROTO op_rcrl_T0_T1_cc(void) |
513 | 7bfdb6d1 | bellard | { |
514 | 7bfdb6d1 | bellard | int count, res;
|
515 | 7bfdb6d1 | bellard | count = T1 & 0x1f;
|
516 | 7bfdb6d1 | bellard | if (count) {
|
517 | 7bfdb6d1 | bellard | CC_SRC = T0; |
518 | 7bfdb6d1 | bellard | res = (T0 >> count) | (cc_table[CC_OP].compute_c() << (32 - count));
|
519 | 7bfdb6d1 | bellard | if (count > 1) |
520 | 7bfdb6d1 | bellard | res |= T0 << (33 - count);
|
521 | 7bfdb6d1 | bellard | T0 = res; |
522 | 7bfdb6d1 | bellard | CC_DST = T0 ^ CC_SRC; |
523 | 7bfdb6d1 | bellard | CC_SRC >>= (count - 1);
|
524 | 7bfdb6d1 | bellard | CC_OP = CC_OP_RCLL; |
525 | 7bfdb6d1 | bellard | } |
526 | 7bfdb6d1 | bellard | } |
527 | 7bfdb6d1 | bellard | |
528 | 7bfdb6d1 | bellard | void OPPROTO op_rcrw_T0_T1_cc(void) |
529 | 7bfdb6d1 | bellard | { |
530 | 7bfdb6d1 | bellard | int count;
|
531 | 7bfdb6d1 | bellard | count = rclw_table[T1 & 0x1f];
|
532 | 7bfdb6d1 | bellard | if (count) {
|
533 | 7bfdb6d1 | bellard | T0 = T0 & 0xffff;
|
534 | 7bfdb6d1 | bellard | CC_SRC = T0; |
535 | 7bfdb6d1 | bellard | T0 = (T0 >> count) | (cc_table[CC_OP].compute_c() << (16 - count)) |
|
536 | 7bfdb6d1 | bellard | (T0 << (17 - count));
|
537 | 7bfdb6d1 | bellard | CC_DST = T0 ^ CC_SRC; |
538 | 7bfdb6d1 | bellard | CC_SRC >>= (count - 1);
|
539 | 7bfdb6d1 | bellard | CC_OP = CC_OP_RCLW; |
540 | 7bfdb6d1 | bellard | } |
541 | 7bfdb6d1 | bellard | } |
542 | 7bfdb6d1 | bellard | |
543 | 7bfdb6d1 | bellard | void OPPROTO op_rcrb_T0_T1_cc(void) |
544 | 7bfdb6d1 | bellard | { |
545 | 7bfdb6d1 | bellard | int count;
|
546 | 7bfdb6d1 | bellard | count = rclb_table[T1 & 0x1f];
|
547 | 7bfdb6d1 | bellard | if (count) {
|
548 | 7bfdb6d1 | bellard | T0 = T0 & 0xff;
|
549 | 7bfdb6d1 | bellard | CC_SRC = T0; |
550 | 7bfdb6d1 | bellard | T0 = (T0 >> count) | (cc_table[CC_OP].compute_c() << (8 - count)) |
|
551 | 7bfdb6d1 | bellard | (T0 << (9 - count));
|
552 | 7bfdb6d1 | bellard | CC_DST = T0 ^ CC_SRC; |
553 | 7bfdb6d1 | bellard | CC_SRC >>= (count - 1);
|
554 | 7bfdb6d1 | bellard | CC_OP = CC_OP_RCLB; |
555 | 7bfdb6d1 | bellard | } |
556 | 7bfdb6d1 | bellard | } |
557 | 7bfdb6d1 | bellard | |
558 | 7bfdb6d1 | bellard | void OPPROTO op_shll_T0_T1_cc(void) |
559 | 7bfdb6d1 | bellard | { |
560 | 7bfdb6d1 | bellard | int count;
|
561 | 7bfdb6d1 | bellard | count = T1 & 0x1f;
|
562 | 7bfdb6d1 | bellard | if (count == 1) { |
563 | 7bfdb6d1 | bellard | CC_SRC = T0; |
564 | 7bfdb6d1 | bellard | T0 = T0 << 1;
|
565 | 7bfdb6d1 | bellard | CC_DST = T0; |
566 | 7bfdb6d1 | bellard | CC_OP = CC_OP_ADDL; |
567 | 7bfdb6d1 | bellard | } else if (count) { |
568 | 7bfdb6d1 | bellard | CC_SRC = T0 >> (32 - count);
|
569 | 7bfdb6d1 | bellard | T0 = T0 << count; |
570 | 7bfdb6d1 | bellard | CC_DST = T0; |
571 | 7bfdb6d1 | bellard | CC_OP = CC_OP_SHLL; |
572 | 7bfdb6d1 | bellard | } |
573 | 7bfdb6d1 | bellard | } |
574 | 7bfdb6d1 | bellard | |
575 | 7bfdb6d1 | bellard | void OPPROTO op_shlw_T0_T1_cc(void) |
576 | 7bfdb6d1 | bellard | { |
577 | 7bfdb6d1 | bellard | int count;
|
578 | 7bfdb6d1 | bellard | count = T1 & 0x1f;
|
579 | 7bfdb6d1 | bellard | if (count == 1) { |
580 | 7bfdb6d1 | bellard | CC_SRC = T0; |
581 | 7bfdb6d1 | bellard | T0 = T0 << 1;
|
582 | 7bfdb6d1 | bellard | CC_DST = T0; |
583 | 7bfdb6d1 | bellard | CC_OP = CC_OP_ADDW; |
584 | 7bfdb6d1 | bellard | } else if (count) { |
585 | 7bfdb6d1 | bellard | CC_SRC = T0 >> (16 - count);
|
586 | 7bfdb6d1 | bellard | T0 = T0 << count; |
587 | 7bfdb6d1 | bellard | CC_DST = T0; |
588 | 7bfdb6d1 | bellard | CC_OP = CC_OP_SHLW; |
589 | 7bfdb6d1 | bellard | } |
590 | 7bfdb6d1 | bellard | } |
591 | 7bfdb6d1 | bellard | |
592 | 7bfdb6d1 | bellard | void OPPROTO op_shlb_T0_T1_cc(void) |
593 | 7bfdb6d1 | bellard | { |
594 | 7bfdb6d1 | bellard | int count;
|
595 | 7bfdb6d1 | bellard | count = T1 & 0x1f;
|
596 | 7bfdb6d1 | bellard | if (count == 1) { |
597 | 7bfdb6d1 | bellard | CC_SRC = T0; |
598 | 7bfdb6d1 | bellard | T0 = T0 << 1;
|
599 | 7bfdb6d1 | bellard | CC_DST = T0; |
600 | 7bfdb6d1 | bellard | CC_OP = CC_OP_ADDB; |
601 | 7bfdb6d1 | bellard | } else if (count) { |
602 | 7bfdb6d1 | bellard | CC_SRC = T0 >> (8 - count);
|
603 | 7bfdb6d1 | bellard | T0 = T0 << count; |
604 | 7bfdb6d1 | bellard | CC_DST = T0; |
605 | 7bfdb6d1 | bellard | CC_OP = CC_OP_SHLB; |
606 | 7bfdb6d1 | bellard | } |
607 | 7bfdb6d1 | bellard | } |
608 | 7bfdb6d1 | bellard | |
609 | 7bfdb6d1 | bellard | void OPPROTO op_shrl_T0_T1_cc(void) |
610 | 7bfdb6d1 | bellard | { |
611 | 7bfdb6d1 | bellard | int count;
|
612 | 7bfdb6d1 | bellard | count = T1 & 0x1f;
|
613 | 7bfdb6d1 | bellard | if (count == 1) { |
614 | 7bfdb6d1 | bellard | CC_SRC = T0; |
615 | 7bfdb6d1 | bellard | T0 = T0 >> 1;
|
616 | 7bfdb6d1 | bellard | CC_DST = T0; |
617 | 7bfdb6d1 | bellard | CC_OP = CC_OP_SHRL; |
618 | 7bfdb6d1 | bellard | } else if (count) { |
619 | 7bfdb6d1 | bellard | CC_SRC = T0 >> (count - 1);
|
620 | 7bfdb6d1 | bellard | T0 = T0 >> count; |
621 | 7bfdb6d1 | bellard | CC_DST = T0; |
622 | 7bfdb6d1 | bellard | CC_OP = CC_OP_SHLL; |
623 | 7bfdb6d1 | bellard | } |
624 | 7bfdb6d1 | bellard | } |
625 | 7bfdb6d1 | bellard | |
626 | 7bfdb6d1 | bellard | void OPPROTO op_shrw_T0_T1_cc(void) |
627 | 7bfdb6d1 | bellard | { |
628 | 7bfdb6d1 | bellard | int count;
|
629 | 7bfdb6d1 | bellard | count = T1 & 0x1f;
|
630 | 7bfdb6d1 | bellard | if (count == 1) { |
631 | 7bfdb6d1 | bellard | T0 = T0 & 0xffff;
|
632 | 7bfdb6d1 | bellard | CC_SRC = T0; |
633 | 7bfdb6d1 | bellard | T0 = T0 >> 1;
|
634 | 7bfdb6d1 | bellard | CC_DST = T0; |
635 | 7bfdb6d1 | bellard | CC_OP = CC_OP_SHRW; |
636 | 7bfdb6d1 | bellard | } else if (count) { |
637 | 7bfdb6d1 | bellard | T0 = T0 & 0xffff;
|
638 | 7bfdb6d1 | bellard | CC_SRC = T0 >> (count - 1);
|
639 | 7bfdb6d1 | bellard | T0 = T0 >> count; |
640 | 7bfdb6d1 | bellard | CC_DST = T0; |
641 | 7bfdb6d1 | bellard | CC_OP = CC_OP_SHLW; |
642 | 7bfdb6d1 | bellard | } |
643 | 7bfdb6d1 | bellard | } |
644 | 7bfdb6d1 | bellard | |
645 | 7bfdb6d1 | bellard | void OPPROTO op_shrb_T0_T1_cc(void) |
646 | 7bfdb6d1 | bellard | { |
647 | 7bfdb6d1 | bellard | int count;
|
648 | 7bfdb6d1 | bellard | count = T1 & 0x1f;
|
649 | 7bfdb6d1 | bellard | if (count == 1) { |
650 | 7bfdb6d1 | bellard | T0 = T0 & 0xff;
|
651 | 7bfdb6d1 | bellard | CC_SRC = T0; |
652 | 7bfdb6d1 | bellard | T0 = T0 >> 1;
|
653 | 7bfdb6d1 | bellard | CC_DST = T0; |
654 | 7bfdb6d1 | bellard | CC_OP = CC_OP_SHRB; |
655 | 7bfdb6d1 | bellard | } else if (count) { |
656 | 7bfdb6d1 | bellard | T0 = T0 & 0xff;
|
657 | 7bfdb6d1 | bellard | CC_SRC = T0 >> (count - 1);
|
658 | 7bfdb6d1 | bellard | T0 = T0 >> count; |
659 | 7bfdb6d1 | bellard | CC_DST = T0; |
660 | 7bfdb6d1 | bellard | CC_OP = CC_OP_SHLB; |
661 | 7bfdb6d1 | bellard | } |
662 | 7bfdb6d1 | bellard | } |
663 | 7bfdb6d1 | bellard | |
664 | 7bfdb6d1 | bellard | void OPPROTO op_sarl_T0_T1_cc(void) |
665 | 7bfdb6d1 | bellard | { |
666 | 7bfdb6d1 | bellard | int count;
|
667 | 7bfdb6d1 | bellard | count = T1 & 0x1f;
|
668 | 7bfdb6d1 | bellard | if (count) {
|
669 | 7bfdb6d1 | bellard | CC_SRC = (int32_t)T0 >> (count - 1);
|
670 | 7bfdb6d1 | bellard | T0 = (int32_t)T0 >> count; |
671 | 7bfdb6d1 | bellard | CC_DST = T0; |
672 | 7bfdb6d1 | bellard | CC_OP = CC_OP_SHLL; |
673 | 7bfdb6d1 | bellard | } |
674 | 7bfdb6d1 | bellard | } |
675 | 7bfdb6d1 | bellard | |
676 | 7bfdb6d1 | bellard | void OPPROTO op_sarw_T0_T1_cc(void) |
677 | 7bfdb6d1 | bellard | { |
678 | 7bfdb6d1 | bellard | int count;
|
679 | 7bfdb6d1 | bellard | count = T1 & 0x1f;
|
680 | 7bfdb6d1 | bellard | if (count) {
|
681 | 7bfdb6d1 | bellard | CC_SRC = (int16_t)T0 >> (count - 1);
|
682 | 7bfdb6d1 | bellard | T0 = (int16_t)T0 >> count; |
683 | 7bfdb6d1 | bellard | CC_DST = T0; |
684 | 7bfdb6d1 | bellard | CC_OP = CC_OP_SHLW; |
685 | 7bfdb6d1 | bellard | } |
686 | 7bfdb6d1 | bellard | } |
687 | 7bfdb6d1 | bellard | |
688 | 7bfdb6d1 | bellard | void OPPROTO op_sarb_T0_T1_cc(void) |
689 | 7bfdb6d1 | bellard | { |
690 | 7bfdb6d1 | bellard | int count;
|
691 | 7bfdb6d1 | bellard | count = T1 & 0x1f;
|
692 | 7bfdb6d1 | bellard | if (count) {
|
693 | 7bfdb6d1 | bellard | CC_SRC = (int8_t)T0 >> (count - 1);
|
694 | 7bfdb6d1 | bellard | T0 = (int8_t)T0 >> count; |
695 | 7bfdb6d1 | bellard | CC_DST = T0; |
696 | 7bfdb6d1 | bellard | CC_OP = CC_OP_SHLB; |
697 | 7bfdb6d1 | bellard | } |
698 | 7bfdb6d1 | bellard | } |
699 | 7bfdb6d1 | bellard | |
700 | 7bfdb6d1 | bellard | /* multiply/divide */
|
701 | 7bfdb6d1 | bellard | void OPPROTO op_mulb_AL_T0(void) |
702 | 7bfdb6d1 | bellard | { |
703 | 7bfdb6d1 | bellard | unsigned int res; |
704 | 7bfdb6d1 | bellard | res = (uint8_t)EAX * (uint8_t)T0; |
705 | 7bfdb6d1 | bellard | EAX = (EAX & 0xffff0000) | res;
|
706 | 7bfdb6d1 | bellard | CC_SRC = (res & 0xff00);
|
707 | 7bfdb6d1 | bellard | } |
708 | 7bfdb6d1 | bellard | |
709 | 7bfdb6d1 | bellard | void OPPROTO op_imulb_AL_T0(void) |
710 | 7bfdb6d1 | bellard | { |
711 | 7bfdb6d1 | bellard | int res;
|
712 | 7bfdb6d1 | bellard | res = (int8_t)EAX * (int8_t)T0; |
713 | 7bfdb6d1 | bellard | EAX = (EAX & 0xffff0000) | (res & 0xffff); |
714 | 7bfdb6d1 | bellard | CC_SRC = (res != (int8_t)res); |
715 | 7bfdb6d1 | bellard | } |
716 | 7bfdb6d1 | bellard | |
717 | 7bfdb6d1 | bellard | void OPPROTO op_mulw_AX_T0(void) |
718 | 7bfdb6d1 | bellard | { |
719 | 7bfdb6d1 | bellard | unsigned int res; |
720 | 7bfdb6d1 | bellard | res = (uint16_t)EAX * (uint16_t)T0; |
721 | 7bfdb6d1 | bellard | EAX = (EAX & 0xffff0000) | (res & 0xffff); |
722 | 7bfdb6d1 | bellard | EDX = (EDX & 0xffff0000) | ((res >> 16) & 0xffff); |
723 | 7bfdb6d1 | bellard | CC_SRC = res >> 16;
|
724 | 7bfdb6d1 | bellard | } |
725 | 7bfdb6d1 | bellard | |
726 | 7bfdb6d1 | bellard | void OPPROTO op_imulw_AX_T0(void) |
727 | 7bfdb6d1 | bellard | { |
728 | 7bfdb6d1 | bellard | int res;
|
729 | 7bfdb6d1 | bellard | res = (int16_t)EAX * (int16_t)T0; |
730 | 7bfdb6d1 | bellard | EAX = (EAX & 0xffff0000) | (res & 0xffff); |
731 | 7bfdb6d1 | bellard | EDX = (EDX & 0xffff0000) | ((res >> 16) & 0xffff); |
732 | 7bfdb6d1 | bellard | CC_SRC = (res != (int16_t)res); |
733 | 7bfdb6d1 | bellard | } |
734 | 7bfdb6d1 | bellard | |
735 | 7bfdb6d1 | bellard | void OPPROTO op_mull_EAX_T0(void) |
736 | 7bfdb6d1 | bellard | { |
737 | 7bfdb6d1 | bellard | uint64_t res; |
738 | 7bfdb6d1 | bellard | res = (uint64_t)((uint32_t)EAX) * (uint64_t)((uint32_t)T0); |
739 | 7bfdb6d1 | bellard | EAX = res; |
740 | 7bfdb6d1 | bellard | EDX = res >> 32;
|
741 | 7bfdb6d1 | bellard | CC_SRC = res >> 32;
|
742 | 7bfdb6d1 | bellard | } |
743 | 7bfdb6d1 | bellard | |
744 | 7bfdb6d1 | bellard | void OPPROTO op_imull_EAX_T0(void) |
745 | 7bfdb6d1 | bellard | { |
746 | 7bfdb6d1 | bellard | int64_t res; |
747 | 7bfdb6d1 | bellard | res = (int64_t)((int32_t)EAX) * (int64_t)((int32_t)T0); |
748 | 7bfdb6d1 | bellard | EAX = res; |
749 | 7bfdb6d1 | bellard | EDX = res >> 32;
|
750 | 7bfdb6d1 | bellard | CC_SRC = (res != (int32_t)res); |
751 | 7bfdb6d1 | bellard | } |
752 | 7bfdb6d1 | bellard | |
753 | 7bfdb6d1 | bellard | void OPPROTO op_imulw_T0_T1(void) |
754 | 7bfdb6d1 | bellard | { |
755 | 7bfdb6d1 | bellard | int res;
|
756 | 7bfdb6d1 | bellard | res = (int16_t)T0 * (int16_t)T1; |
757 | 7bfdb6d1 | bellard | T0 = res; |
758 | 7bfdb6d1 | bellard | CC_SRC = (res != (int16_t)res); |
759 | 7bfdb6d1 | bellard | } |
760 | 7bfdb6d1 | bellard | |
761 | 7bfdb6d1 | bellard | void OPPROTO op_imull_T0_T1(void) |
762 | 7bfdb6d1 | bellard | { |
763 | 7bfdb6d1 | bellard | int64_t res; |
764 | 7bfdb6d1 | bellard | res = (int64_t)((int32_t)EAX) * (int64_t)((int32_t)T1); |
765 | 7bfdb6d1 | bellard | T0 = res; |
766 | 7bfdb6d1 | bellard | CC_SRC = (res != (int32_t)res); |
767 | 7bfdb6d1 | bellard | } |
768 | 7bfdb6d1 | bellard | |
769 | 7bfdb6d1 | bellard | /* division, flags are undefined */
|
770 | 7bfdb6d1 | bellard | /* XXX: add exceptions for overflow & div by zero */
|
771 | 7bfdb6d1 | bellard | void OPPROTO op_divb_AL_T0(void) |
772 | 7bfdb6d1 | bellard | { |
773 | 7bfdb6d1 | bellard | unsigned int num, den, q, r; |
774 | 7bfdb6d1 | bellard | |
775 | 7bfdb6d1 | bellard | num = (EAX & 0xffff);
|
776 | 7bfdb6d1 | bellard | den = (T0 & 0xff);
|
777 | 7bfdb6d1 | bellard | q = (num / den) & 0xff;
|
778 | 7bfdb6d1 | bellard | r = (num % den) & 0xff;
|
779 | 7bfdb6d1 | bellard | EAX = (EAX & 0xffff0000) | (r << 8) | q; |
780 | 7bfdb6d1 | bellard | } |
781 | 7bfdb6d1 | bellard | |
782 | 7bfdb6d1 | bellard | void OPPROTO op_idivb_AL_T0(void) |
783 | 7bfdb6d1 | bellard | { |
784 | 7bfdb6d1 | bellard | int num, den, q, r;
|
785 | 7bfdb6d1 | bellard | |
786 | 7bfdb6d1 | bellard | num = (int16_t)EAX; |
787 | 7bfdb6d1 | bellard | den = (int8_t)T0; |
788 | 7bfdb6d1 | bellard | q = (num / den) & 0xff;
|
789 | 7bfdb6d1 | bellard | r = (num % den) & 0xff;
|
790 | 7bfdb6d1 | bellard | EAX = (EAX & 0xffff0000) | (r << 8) | q; |
791 | 7bfdb6d1 | bellard | } |
792 | 7bfdb6d1 | bellard | |
793 | 7bfdb6d1 | bellard | void OPPROTO op_divw_AX_T0(void) |
794 | 7bfdb6d1 | bellard | { |
795 | 7bfdb6d1 | bellard | unsigned int num, den, q, r; |
796 | 7bfdb6d1 | bellard | |
797 | 7bfdb6d1 | bellard | num = (EAX & 0xffff) | ((EDX & 0xffff) << 16); |
798 | 7bfdb6d1 | bellard | den = (T0 & 0xffff);
|
799 | 7bfdb6d1 | bellard | q = (num / den) & 0xffff;
|
800 | 7bfdb6d1 | bellard | r = (num % den) & 0xffff;
|
801 | 7bfdb6d1 | bellard | EAX = (EAX & 0xffff0000) | q;
|
802 | 7bfdb6d1 | bellard | EDX = (EDX & 0xffff0000) | r;
|
803 | 7bfdb6d1 | bellard | } |
804 | 7bfdb6d1 | bellard | |
805 | 7bfdb6d1 | bellard | void OPPROTO op_idivw_AX_T0(void) |
806 | 7bfdb6d1 | bellard | { |
807 | 7bfdb6d1 | bellard | int num, den, q, r;
|
808 | 7bfdb6d1 | bellard | |
809 | 7bfdb6d1 | bellard | num = (EAX & 0xffff) | ((EDX & 0xffff) << 16); |
810 | 7bfdb6d1 | bellard | den = (int16_t)T0; |
811 | 7bfdb6d1 | bellard | q = (num / den) & 0xffff;
|
812 | 7bfdb6d1 | bellard | r = (num % den) & 0xffff;
|
813 | 7bfdb6d1 | bellard | EAX = (EAX & 0xffff0000) | q;
|
814 | 7bfdb6d1 | bellard | EDX = (EDX & 0xffff0000) | r;
|
815 | 7bfdb6d1 | bellard | } |
816 | 7bfdb6d1 | bellard | |
817 | 7bfdb6d1 | bellard | void OPPROTO op_divl_EAX_T0(void) |
818 | 7bfdb6d1 | bellard | { |
819 | 7bfdb6d1 | bellard | unsigned int den, q, r; |
820 | 7bfdb6d1 | bellard | uint64_t num; |
821 | 7bfdb6d1 | bellard | |
822 | 7bfdb6d1 | bellard | num = EAX | ((uint64_t)EDX << 32);
|
823 | 7bfdb6d1 | bellard | den = T0; |
824 | 7bfdb6d1 | bellard | q = (num / den); |
825 | 7bfdb6d1 | bellard | r = (num % den); |
826 | 7bfdb6d1 | bellard | EAX = q; |
827 | 7bfdb6d1 | bellard | EDX = r; |
828 | 7bfdb6d1 | bellard | } |
829 | 7bfdb6d1 | bellard | |
830 | 7bfdb6d1 | bellard | void OPPROTO op_idivl_EAX_T0(void) |
831 | 7bfdb6d1 | bellard | { |
832 | 7bfdb6d1 | bellard | int den, q, r;
|
833 | 7bfdb6d1 | bellard | int16_t num; |
834 | 7bfdb6d1 | bellard | |
835 | 7bfdb6d1 | bellard | num = EAX | ((uint64_t)EDX << 32);
|
836 | 7bfdb6d1 | bellard | den = (int16_t)T0; |
837 | 7bfdb6d1 | bellard | q = (num / den); |
838 | 7bfdb6d1 | bellard | r = (num % den); |
839 | 7bfdb6d1 | bellard | EAX = q; |
840 | 7bfdb6d1 | bellard | EDX = r; |
841 | 7bfdb6d1 | bellard | } |
842 | 7bfdb6d1 | bellard | |
843 | 7bfdb6d1 | bellard | /* constant load */
|
844 | 7bfdb6d1 | bellard | |
845 | 7bfdb6d1 | bellard | void OPPROTO op1_movl_T0_im(void) |
846 | 7bfdb6d1 | bellard | { |
847 | 7bfdb6d1 | bellard | T0 = PARAM1; |
848 | 7bfdb6d1 | bellard | } |
849 | 7bfdb6d1 | bellard | |
850 | 7bfdb6d1 | bellard | void OPPROTO op1_movl_T1_im(void) |
851 | 7bfdb6d1 | bellard | { |
852 | 7bfdb6d1 | bellard | T1 = PARAM1; |
853 | 7bfdb6d1 | bellard | } |
854 | 7bfdb6d1 | bellard | |
855 | 7bfdb6d1 | bellard | void OPPROTO op1_movl_A0_im(void) |
856 | 7bfdb6d1 | bellard | { |
857 | 7bfdb6d1 | bellard | A0 = PARAM1; |
858 | 7bfdb6d1 | bellard | } |
859 | 7bfdb6d1 | bellard | |
860 | 7bfdb6d1 | bellard | /* memory access */
|
861 | 7bfdb6d1 | bellard | |
862 | 7bfdb6d1 | bellard | void OPPROTO op_ldub_T0_A0(void) |
863 | 7bfdb6d1 | bellard | { |
864 | 7bfdb6d1 | bellard | T0 = ldub((uint8_t *)A0); |
865 | 7bfdb6d1 | bellard | } |
866 | 7bfdb6d1 | bellard | |
867 | 7bfdb6d1 | bellard | void OPPROTO op_ldsb_T0_A0(void) |
868 | 7bfdb6d1 | bellard | { |
869 | 7bfdb6d1 | bellard | T0 = ldsb((int8_t *)A0); |
870 | 7bfdb6d1 | bellard | } |
871 | 7bfdb6d1 | bellard | |
872 | 7bfdb6d1 | bellard | void OPPROTO op_lduw_T0_A0(void) |
873 | 7bfdb6d1 | bellard | { |
874 | 7bfdb6d1 | bellard | T0 = lduw((uint8_t *)A0); |
875 | 7bfdb6d1 | bellard | } |
876 | 7bfdb6d1 | bellard | |
877 | 7bfdb6d1 | bellard | void OPPROTO op_ldsw_T0_A0(void) |
878 | 7bfdb6d1 | bellard | { |
879 | 7bfdb6d1 | bellard | T0 = ldsw((int8_t *)A0); |
880 | 7bfdb6d1 | bellard | } |
881 | 7bfdb6d1 | bellard | |
882 | 7bfdb6d1 | bellard | void OPPROTO op_ldl_T0_A0(void) |
883 | 7bfdb6d1 | bellard | { |
884 | 7bfdb6d1 | bellard | T0 = ldl((uint8_t *)A0); |
885 | 7bfdb6d1 | bellard | } |
886 | 7bfdb6d1 | bellard | |
887 | 7bfdb6d1 | bellard | void OPPROTO op_ldub_T1_A0(void) |
888 | 7bfdb6d1 | bellard | { |
889 | 7bfdb6d1 | bellard | T1 = ldub((uint8_t *)A0); |
890 | 7bfdb6d1 | bellard | } |
891 | 7bfdb6d1 | bellard | |
892 | 7bfdb6d1 | bellard | void OPPROTO op_ldsb_T1_A0(void) |
893 | 7bfdb6d1 | bellard | { |
894 | 7bfdb6d1 | bellard | T1 = ldsb((int8_t *)A0); |
895 | 7bfdb6d1 | bellard | } |
896 | 7bfdb6d1 | bellard | |
897 | 7bfdb6d1 | bellard | void OPPROTO op_lduw_T1_A0(void) |
898 | 7bfdb6d1 | bellard | { |
899 | 7bfdb6d1 | bellard | T1 = lduw((uint8_t *)A0); |
900 | 7bfdb6d1 | bellard | } |
901 | 7bfdb6d1 | bellard | |
902 | 7bfdb6d1 | bellard | void OPPROTO op_ldsw_T1_A0(void) |
903 | 7bfdb6d1 | bellard | { |
904 | 7bfdb6d1 | bellard | T1 = ldsw((int8_t *)A0); |
905 | 7bfdb6d1 | bellard | } |
906 | 7bfdb6d1 | bellard | |
907 | 7bfdb6d1 | bellard | void OPPROTO op_ldl_T1_A0(void) |
908 | 7bfdb6d1 | bellard | { |
909 | 7bfdb6d1 | bellard | T1 = ldl((uint8_t *)A0); |
910 | 7bfdb6d1 | bellard | } |
911 | 7bfdb6d1 | bellard | |
912 | 7bfdb6d1 | bellard | void OPPROTO op_stb_T0_A0(void) |
913 | 7bfdb6d1 | bellard | { |
914 | 7bfdb6d1 | bellard | stb((uint8_t *)A0, T0); |
915 | 7bfdb6d1 | bellard | } |
916 | 7bfdb6d1 | bellard | |
917 | 7bfdb6d1 | bellard | void OPPROTO op_stw_T0_A0(void) |
918 | 7bfdb6d1 | bellard | { |
919 | 7bfdb6d1 | bellard | stw((uint8_t *)A0, T0); |
920 | 7bfdb6d1 | bellard | } |
921 | 7bfdb6d1 | bellard | |
922 | 7bfdb6d1 | bellard | void OPPROTO op_stl_T0_A0(void) |
923 | 7bfdb6d1 | bellard | { |
924 | 7bfdb6d1 | bellard | stl((uint8_t *)A0, T0); |
925 | 7bfdb6d1 | bellard | } |
926 | 7bfdb6d1 | bellard | |
927 | 7bfdb6d1 | bellard | /* flags */
|
928 | 7bfdb6d1 | bellard | |
929 | 7bfdb6d1 | bellard | void OPPROTO op_set_cc_op(void) |
930 | 7bfdb6d1 | bellard | { |
931 | 7bfdb6d1 | bellard | CC_OP = PARAM1; |
932 | 7bfdb6d1 | bellard | } |
933 | 7bfdb6d1 | bellard | |
934 | 7bfdb6d1 | bellard | void OPPROTO op_movl_eflags_T0(void) |
935 | 7bfdb6d1 | bellard | { |
936 | 7bfdb6d1 | bellard | CC_SRC = T0; |
937 | 7bfdb6d1 | bellard | DF = (T0 & DIRECTION_FLAG) ? -1 : 1; |
938 | 7bfdb6d1 | bellard | } |
939 | 7bfdb6d1 | bellard | |
940 | 7bfdb6d1 | bellard | void OPPROTO op_movb_eflags_T0(void) |
941 | 7bfdb6d1 | bellard | { |
942 | 7bfdb6d1 | bellard | int cc_o;
|
943 | 7bfdb6d1 | bellard | cc_o = cc_table[CC_OP].compute_o(); |
944 | 7bfdb6d1 | bellard | CC_SRC = T0 | (cc_o << 11);
|
945 | 7bfdb6d1 | bellard | } |
946 | 7bfdb6d1 | bellard | |
947 | 7bfdb6d1 | bellard | void OPPROTO op_movl_T0_eflags(void) |
948 | 7bfdb6d1 | bellard | { |
949 | 7bfdb6d1 | bellard | cc_table[CC_OP].compute_eflags(); |
950 | 7bfdb6d1 | bellard | } |
951 | 7bfdb6d1 | bellard | |
952 | 7bfdb6d1 | bellard | void OPPROTO op_cld(void) |
953 | 7bfdb6d1 | bellard | { |
954 | 7bfdb6d1 | bellard | DF = 1;
|
955 | 7bfdb6d1 | bellard | } |
956 | 7bfdb6d1 | bellard | |
957 | 7bfdb6d1 | bellard | void OPPROTO op_std(void) |
958 | 7bfdb6d1 | bellard | { |
959 | 7bfdb6d1 | bellard | DF = -1;
|
960 | 7bfdb6d1 | bellard | } |
961 | 7bfdb6d1 | bellard | |
962 | 7bfdb6d1 | bellard | /* jumps */
|
963 | 7bfdb6d1 | bellard | |
964 | 7bfdb6d1 | bellard | /* indirect jump */
|
965 | 7bfdb6d1 | bellard | void OPPROTO op_jmp_T0(void) |
966 | 7bfdb6d1 | bellard | { |
967 | 7bfdb6d1 | bellard | PC = T0; |
968 | 7bfdb6d1 | bellard | } |
969 | 7bfdb6d1 | bellard | |
970 | 7bfdb6d1 | bellard | void OPPROTO op_jmp_im(void) |
971 | 7bfdb6d1 | bellard | { |
972 | 7bfdb6d1 | bellard | PC = PARAM1; |
973 | 7bfdb6d1 | bellard | } |
974 | 7bfdb6d1 | bellard | |
975 | 7bfdb6d1 | bellard | void OPPROTO op_jne_b(void) |
976 | 7bfdb6d1 | bellard | { |
977 | 7bfdb6d1 | bellard | if ((uint8_t)CC_DST != 0) |
978 | 7bfdb6d1 | bellard | PC += PARAM1; |
979 | 7bfdb6d1 | bellard | else
|
980 | 7bfdb6d1 | bellard | PC += PARAM2; |
981 | 7bfdb6d1 | bellard | FORCE_RET(); |
982 | 7bfdb6d1 | bellard | } |
983 | 7bfdb6d1 | bellard | |
984 | 7bfdb6d1 | bellard | void OPPROTO op_jne_w(void) |
985 | 7bfdb6d1 | bellard | { |
986 | 7bfdb6d1 | bellard | if ((uint16_t)CC_DST != 0) |
987 | 7bfdb6d1 | bellard | PC += PARAM1; |
988 | 7bfdb6d1 | bellard | else
|
989 | 7bfdb6d1 | bellard | PC += PARAM2; |
990 | 7bfdb6d1 | bellard | FORCE_RET(); |
991 | 7bfdb6d1 | bellard | } |
992 | 7bfdb6d1 | bellard | |
993 | 7bfdb6d1 | bellard | void OPPROTO op_jne_l(void) |
994 | 7bfdb6d1 | bellard | { |
995 | 7bfdb6d1 | bellard | if (CC_DST != 0) |
996 | 7bfdb6d1 | bellard | PC += PARAM1; |
997 | 7bfdb6d1 | bellard | else
|
998 | 7bfdb6d1 | bellard | PC += PARAM2; |
999 | 7bfdb6d1 | bellard | FORCE_RET(); /* generate a return so that gcc does not generate an
|
1000 | 7bfdb6d1 | bellard | early function return */
|
1001 | 7bfdb6d1 | bellard | } |
1002 | 7bfdb6d1 | bellard | |
1003 | 7bfdb6d1 | bellard | /* string ops */
|
1004 | 7bfdb6d1 | bellard | |
1005 | 7bfdb6d1 | bellard | #define ldul ldl
|
1006 | 7bfdb6d1 | bellard | |
1007 | 7bfdb6d1 | bellard | #define SUFFIX b
|
1008 | 7bfdb6d1 | bellard | #define SHIFT 0 |
1009 | 7bfdb6d1 | bellard | #include "opstring_template.h" |
1010 | 7bfdb6d1 | bellard | #undef SUFFIX
|
1011 | 7bfdb6d1 | bellard | #undef SHIFT
|
1012 | 7bfdb6d1 | bellard | |
1013 | 7bfdb6d1 | bellard | #define SUFFIX w
|
1014 | 7bfdb6d1 | bellard | #define SHIFT 1 |
1015 | 7bfdb6d1 | bellard | #include "opstring_template.h" |
1016 | 7bfdb6d1 | bellard | #undef SUFFIX
|
1017 | 7bfdb6d1 | bellard | #undef SHIFT
|
1018 | 7bfdb6d1 | bellard | |
1019 | 7bfdb6d1 | bellard | #define SUFFIX l
|
1020 | 7bfdb6d1 | bellard | #define SHIFT 2 |
1021 | 7bfdb6d1 | bellard | #include "opstring_template.h" |
1022 | 7bfdb6d1 | bellard | #undef SUFFIX
|
1023 | 7bfdb6d1 | bellard | #undef SHIFT
|
1024 | 7bfdb6d1 | bellard | |
1025 | 7bfdb6d1 | bellard | /* sign extend */
|
1026 | 7bfdb6d1 | bellard | |
1027 | 7bfdb6d1 | bellard | void OPPROTO op_movsbl_T0_T0(void) |
1028 | 7bfdb6d1 | bellard | { |
1029 | 7bfdb6d1 | bellard | T0 = (int8_t)T0; |
1030 | 7bfdb6d1 | bellard | } |
1031 | 7bfdb6d1 | bellard | |
1032 | 7bfdb6d1 | bellard | void OPPROTO op_movzbl_T0_T0(void) |
1033 | 7bfdb6d1 | bellard | { |
1034 | 7bfdb6d1 | bellard | T0 = (uint8_t)T0; |
1035 | 7bfdb6d1 | bellard | } |
1036 | 7bfdb6d1 | bellard | |
1037 | 7bfdb6d1 | bellard | void OPPROTO op_movswl_T0_T0(void) |
1038 | 7bfdb6d1 | bellard | { |
1039 | 7bfdb6d1 | bellard | T0 = (int16_t)T0; |
1040 | 7bfdb6d1 | bellard | } |
1041 | 7bfdb6d1 | bellard | |
1042 | 7bfdb6d1 | bellard | void OPPROTO op_movzwl_T0_T0(void) |
1043 | 7bfdb6d1 | bellard | { |
1044 | 7bfdb6d1 | bellard | T0 = (uint16_t)T0; |
1045 | 7bfdb6d1 | bellard | } |
1046 | 7bfdb6d1 | bellard | |
1047 | 7bfdb6d1 | bellard | void OPPROTO op_movswl_EAX_AX(void) |
1048 | 7bfdb6d1 | bellard | { |
1049 | 7bfdb6d1 | bellard | EAX = (int16_t)EAX; |
1050 | 7bfdb6d1 | bellard | } |
1051 | 7bfdb6d1 | bellard | |
1052 | 7bfdb6d1 | bellard | void OPPROTO op_movsbw_AX_AL(void) |
1053 | 7bfdb6d1 | bellard | { |
1054 | 7bfdb6d1 | bellard | EAX = (EAX & 0xffff0000) | ((int8_t)EAX & 0xffff); |
1055 | 7bfdb6d1 | bellard | } |
1056 | 7bfdb6d1 | bellard | |
1057 | 7bfdb6d1 | bellard | void OPPROTO op_movslq_EDX_EAX(void) |
1058 | 7bfdb6d1 | bellard | { |
1059 | 7bfdb6d1 | bellard | EDX = (int32_t)EAX >> 31;
|
1060 | 7bfdb6d1 | bellard | } |
1061 | 7bfdb6d1 | bellard | |
1062 | 7bfdb6d1 | bellard | void OPPROTO op_movswl_DX_AX(void) |
1063 | 7bfdb6d1 | bellard | { |
1064 | 7bfdb6d1 | bellard | EDX = (EDX & 0xffff0000) | (((int16_t)EAX >> 15) & 0xffff); |
1065 | 7bfdb6d1 | bellard | } |
1066 | 7bfdb6d1 | bellard | |
1067 | 7bfdb6d1 | bellard | /* push/pop */
|
1068 | 7bfdb6d1 | bellard | /* XXX: add 16 bit operand/16 bit seg variants */
|
1069 | 7bfdb6d1 | bellard | |
1070 | 7bfdb6d1 | bellard | void op_pushl_T0(void) |
1071 | 7bfdb6d1 | bellard | { |
1072 | 7bfdb6d1 | bellard | uint32_t offset; |
1073 | 7bfdb6d1 | bellard | offset = ESP - 4;
|
1074 | 7bfdb6d1 | bellard | stl((void *)offset, T0);
|
1075 | 7bfdb6d1 | bellard | /* modify ESP after to handle exceptions correctly */
|
1076 | 7bfdb6d1 | bellard | ESP = offset; |
1077 | 7bfdb6d1 | bellard | } |
1078 | 7bfdb6d1 | bellard | |
1079 | 7bfdb6d1 | bellard | void op_pushl_T1(void) |
1080 | 7bfdb6d1 | bellard | { |
1081 | 7bfdb6d1 | bellard | uint32_t offset; |
1082 | 7bfdb6d1 | bellard | offset = ESP - 4;
|
1083 | 7bfdb6d1 | bellard | stl((void *)offset, T1);
|
1084 | 7bfdb6d1 | bellard | /* modify ESP after to handle exceptions correctly */
|
1085 | 7bfdb6d1 | bellard | ESP = offset; |
1086 | 7bfdb6d1 | bellard | } |
1087 | 7bfdb6d1 | bellard | |
1088 | 7bfdb6d1 | bellard | void op_popl_T0(void) |
1089 | 7bfdb6d1 | bellard | { |
1090 | 7bfdb6d1 | bellard | T0 = ldl((void *)ESP);
|
1091 | 7bfdb6d1 | bellard | ESP += 4;
|
1092 | 7bfdb6d1 | bellard | } |
1093 | 7bfdb6d1 | bellard | |
1094 | 7bfdb6d1 | bellard | void op_addl_ESP_im(void) |
1095 | 7bfdb6d1 | bellard | { |
1096 | 7bfdb6d1 | bellard | ESP += PARAM1; |
1097 | 7bfdb6d1 | bellard | } |