commit 7c60cc4bcaee6614b7b9a713f974b5d8e536e9c6
Author: bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>
Date:   Sat May 10 10:58:20 2008 +0000

    suppressed fixed registers
    
    git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4408 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 42e8991..9327eac 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -188,7 +188,6 @@ typedef struct trap_state {
 typedef struct CPUSPARCState {
     target_ulong gregs[8]; /* general registers */
     target_ulong *regwptr; /* pointer to current register window */
-    float32 fpr[TARGET_FPREGS];  /* floating point registers */
     target_ulong pc;       /* program counter */
     target_ulong npc;      /* next program counter */
     target_ulong y;        /* multiply/divide register */
@@ -197,8 +196,13 @@ typedef struct CPUSPARCState {
     target_ulong cc_src, cc_src2;
     target_ulong cc_dst;
 
+    target_ulong t0, t1; /* temporaries live across basic blocks */
+    target_ulong cond; /* conditional branch result (XXX: save it in a
+                          temporary register when possible) */
+
     uint32_t psr;      /* processor state register */
     target_ulong fsr;      /* FPU state register */
+    float32 fpr[TARGET_FPREGS];  /* floating point registers */
     uint32_t cwp;      /* index of current register window (extracted
                           from PSR) */
     uint32_t wim;      /* window invalid mask */
@@ -271,7 +275,6 @@ typedef struct CPUSPARCState {
     uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr;
     void *hstick; // UA 2005
 #endif
-    target_ulong t1, t2;
     uint32_t features;
 } CPUSPARCState;
 
diff --git a/target-sparc/exec.h b/target-sparc/exec.h
index 7d67b2d..d47163e 100644
--- a/target-sparc/exec.h
+++ b/target-sparc/exec.h
@@ -4,36 +4,7 @@
 #include "dyngen-exec.h"
 
 register struct CPUSPARCState *env asm(AREG0);
-
-#ifdef TARGET_SPARC64
-#define T0 (env->t0)
-#define T2 (env->t2)
 #define REGWPTR env->regwptr
-#else
-register uint32_t T0 asm(AREG1);
-
-#undef REG_REGWPTR // Broken
-#ifdef REG_REGWPTR
-#if defined(__sparc__)
-register uint32_t *REGWPTR asm(AREG4);
-#else
-register uint32_t *REGWPTR asm(AREG3);
-#endif
-#define reg_REGWPTR
-
-#ifdef AREG4
-register uint32_t T2 asm(AREG4);
-#define reg_T2
-#else
-#define T2 (env->t2)
-#endif
-
-#else
-#define REGWPTR env->regwptr
-register uint32_t T2 asm(AREG3);
-#endif
-#define reg_T2
-#endif
 
 #define FT0 (env->ft0)
 #define FT1 (env->ft1)
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 825145b..9f83e00 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -2189,33 +2189,6 @@ uint64_t helper_pack64(target_ulong high, target_ulong low)
 #define ADDR(x) (x)
 #endif
 
-#ifdef __i386__
-void helper_std_i386(target_ulong addr, int mem_idx)
-{
-    uint64_t tmp = ((uint64_t)env->t1 << 32) | (uint64_t)(env->t2 & 0xffffffff);
-
-#if !defined(CONFIG_USER_ONLY)
-    switch (mem_idx) {
-    case 0:
-        stq_user(ADDR(addr), tmp);
-        break;
-    case 1:
-        stq_kernel(ADDR(addr), tmp);
-        break;
-#ifdef TARGET_SPARC64
-    case 2:
-        stq_hypv(ADDR(addr), tmp);
-        break;
-#endif
-    default:
-        break;
-    }
-#else
-    stq_raw(ADDR(addr), tmp);
-#endif
-}
-#endif /* __i386__ */
-
 void helper_stdf(target_ulong addr, int mem_idx)
 {
 #if !defined(CONFIG_USER_ONLY)
@@ -2894,7 +2867,7 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
             if (tb) {
                 /* the PC is inside the translated code. It means that we have
                    a virtual CPU fault */
-                cpu_restore_state(tb, env, pc, (void *)T2);
+                cpu_restore_state(tb, env, pc, (void *)env->cond);
             }
         }
         cpu_loop_exit();
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index a65a3bf..a2b519f 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -46,7 +46,7 @@
                          according to jump_pc[T2] */
 
 /* global register indexes */
-static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
+static TCGv cpu_env, cpu_T[2], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
 static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
 static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
 #ifdef TARGET_SPARC64
@@ -4223,16 +4223,9 @@ static void disas_sparc_insn(DisasContext * dc)
                         tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
                         r_low = tcg_temp_new(TCG_TYPE_I32);
                         gen_movl_reg_TN(rd + 1, r_low);
-#ifndef __i386__
                         tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
                                            r_low);
                         tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
-#else /* __i386__ */
-                        tcg_gen_st_tl(cpu_val, cpu_env, offsetof(CPUState, t1));
-                        tcg_gen_st_tl(r_low, cpu_env, offsetof(CPUState, t2));
-                        tcg_gen_helper_0_2(helper_std_i386, cpu_addr,
-                                           tcg_const_i32(dc->mem_idx));
-#endif /* __i386__ */
                     }
                     break;
 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
@@ -4475,8 +4468,6 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
     cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
     cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
 
-    cpu_cond = cpu_T[2];
-
     do {
         if (env->nb_breakpoints > 0) {
             for(j = 0; j < env->nb_breakpoints; j++) {
@@ -4599,22 +4590,18 @@ void gen_intermediate_code_init(CPUSPARCState *env)
         cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
                                          offsetof(CPUState, regwptr),
                                          "regwptr");
-        //#if TARGET_LONG_BITS > HOST_LONG_BITS
 #ifdef TARGET_SPARC64
-        cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
-                                      TCG_AREG0, offsetof(CPUState, t0), "T0");
-        cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
-                                      TCG_AREG0, offsetof(CPUState, t1), "T1");
-        cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
-                                      TCG_AREG0, offsetof(CPUState, t2), "T2");
         cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
                                      TCG_AREG0, offsetof(CPUState, xcc),
                                      "xcc");
-#else
-        cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
-        cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
-        cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
 #endif
+        /* XXX: T0 and T1 should be temporaries */
+        cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
+                                      TCG_AREG0, offsetof(CPUState, t0), "T0");
+        cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
+                                      TCG_AREG0, offsetof(CPUState, t1), "T1");
+        cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
+                                      TCG_AREG0, offsetof(CPUState, cond), "cond");
         cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
                                         TCG_AREG0, offsetof(CPUState, cc_src),
                                         "cc_src");
