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/*
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 * QEMU Ultrasparc APB PCI host
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 *
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 * Copyright (c) 2006 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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/* XXX This file and most of its contents are somewhat misnamed.  The
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   Ultrasparc PCI host is called the PCI Bus Module (PBM).  The APB is
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   the secondary PCI bridge.  */
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#include "sysbus.h"
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#include "pci.h"
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#include "pci_host.h"
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#include "rwhandler.h"
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#include "apb_pci.h"
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#include "sysemu.h"
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/* debug APB */
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//#define DEBUG_APB
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#ifdef DEBUG_APB
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#define APB_DPRINTF(fmt, ...) \
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do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define APB_DPRINTF(fmt, ...)
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#endif
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/*
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 * Chipset docs:
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 * PBM: "UltraSPARC IIi User's Manual",
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 * http://www.sun.com/processors/manuals/805-0087.pdf
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 *
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 * APB: "Advanced PCI Bridge (APB) User's Manual",
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 * http://www.sun.com/processors/manuals/805-1251.pdf
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 */
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#define PBM_PCI_IMR_MASK    0x7fffffff
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#define PBM_PCI_IMR_ENABLED 0x80000000
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#define POR          (1 << 31)
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#define SOFT_POR     (1 << 30)
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#define SOFT_XIR     (1 << 29)
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#define BTN_POR      (1 << 28)
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#define BTN_XIR      (1 << 27)
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#define RESET_MASK   0xf8000000
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#define RESET_WCMASK 0x98000000
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#define RESET_WMASK  0x60000000
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typedef struct APBState {
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    SysBusDevice busdev;
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    PCIBus      *bus;
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    ReadWriteHandler pci_config_handler;
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    uint32_t iommu[4];
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    uint32_t pci_control[16];
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    uint32_t pci_irq_map[8];
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    uint32_t obio_irq_map[32];
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    qemu_irq pci_irqs[32];
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    uint32_t reset_control;
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    unsigned int nr_resets;
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} APBState;
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static void apb_config_writel (void *opaque, target_phys_addr_t addr,
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                               uint32_t val)
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{
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    APBState *s = opaque;
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    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
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    switch (addr & 0xffff) {
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    case 0x30 ... 0x4f: /* DMA error registers */
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        /* XXX: not implemented yet */
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        break;
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    case 0x200 ... 0x20b: /* IOMMU */
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        s->iommu[(addr & 0xf) >> 2] = val;
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        break;
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    case 0x20c ... 0x3ff: /* IOMMU flush */
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        break;
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    case 0xc00 ... 0xc3f: /* PCI interrupt control */
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        if (addr & 4) {
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            s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
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            s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK;
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        }
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        break;
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    case 0x2000 ... 0x202f: /* PCI control */
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        s->pci_control[(addr & 0x3f) >> 2] = val;
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        break;
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    case 0xf020 ... 0xf027: /* Reset control */
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        if (addr & 4) {
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            val &= RESET_MASK;
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            s->reset_control &= ~(val & RESET_WCMASK);
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            s->reset_control |= val & RESET_WMASK;
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            if (val & SOFT_POR) {
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                s->nr_resets = 0;
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                qemu_system_reset_request();
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            } else if (val & SOFT_XIR) {
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                qemu_system_reset_request();
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            }
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        }
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        break;
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    case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
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    case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
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    case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
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    case 0xf000 ... 0xf01f: /* FFB config, memory control */
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        /* we don't care */
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    default:
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        break;
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    }
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}
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static uint32_t apb_config_readl (void *opaque,
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                                  target_phys_addr_t addr)
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{
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    APBState *s = opaque;
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    uint32_t val;
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    switch (addr & 0xffff) {
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    case 0x30 ... 0x4f: /* DMA error registers */
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        val = 0;
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        /* XXX: not implemented yet */
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        break;
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    case 0x200 ... 0x20b: /* IOMMU */
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        val = s->iommu[(addr & 0xf) >> 2];
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        break;
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    case 0x20c ... 0x3ff: /* IOMMU flush */
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        val = 0;
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        break;
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    case 0xc00 ... 0xc3f: /* PCI interrupt control */
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        if (addr & 4) {
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            val = s->pci_irq_map[(addr & 0x3f) >> 3];
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        } else {
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            val = 0;
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        }
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        break;
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    case 0x2000 ... 0x202f: /* PCI control */
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        val = s->pci_control[(addr & 0x3f) >> 2];
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        break;
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    case 0xf020 ... 0xf027: /* Reset control */
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        if (addr & 4) {
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            val = s->reset_control;
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        } else {
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            val = 0;
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        }
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        break;
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    case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
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    case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
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    case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
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    case 0xf000 ... 0xf01f: /* FFB config, memory control */
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        /* we don't care */
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    default:
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        val = 0;
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        break;
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    }
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    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);
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    return val;
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}
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static CPUWriteMemoryFunc * const apb_config_write[] = {
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    &apb_config_writel,
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    &apb_config_writel,
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    &apb_config_writel,
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};
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static CPUReadMemoryFunc * const apb_config_read[] = {
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    &apb_config_readl,
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    &apb_config_readl,
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    &apb_config_readl,
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};
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static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr,
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                                 uint32_t val, int size)
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{
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    APBState *s = container_of(h, APBState, pci_config_handler);
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    val = qemu_bswap_len(val, size);
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    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
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    pci_data_write(s->bus, addr, val, size);
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}
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static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
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                                    int size)
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{
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    uint32_t ret;
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    APBState *s = container_of(h, APBState, pci_config_handler);
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    ret = pci_data_read(s->bus, addr, size);
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    ret = qemu_bswap_len(ret, size);
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    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
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    return ret;
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}
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static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
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                                  uint32_t val)
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{
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    cpu_outb(addr & IOPORTS_MASK, val);
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}
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static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
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                                  uint32_t val)
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{
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    cpu_outw(addr & IOPORTS_MASK, bswap16(val));
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}
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static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
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                                uint32_t val)
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{
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    cpu_outl(addr & IOPORTS_MASK, bswap32(val));
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}
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static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
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{
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    uint32_t val;
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    val = cpu_inb(addr & IOPORTS_MASK);
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    return val;
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}
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static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
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{
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    uint32_t val;
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    val = bswap16(cpu_inw(addr & IOPORTS_MASK));
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    return val;
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}
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static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
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{
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    uint32_t val;
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    val = bswap32(cpu_inl(addr & IOPORTS_MASK));
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    return val;
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}
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static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
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    &pci_apb_iowriteb,
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    &pci_apb_iowritew,
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    &pci_apb_iowritel,
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};
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static CPUReadMemoryFunc * const pci_apb_ioread[] = {
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    &pci_apb_ioreadb,
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    &pci_apb_ioreadw,
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    &pci_apb_ioreadl,
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};
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/* The APB host has an IRQ line for each IRQ line of each slot.  */
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static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
266
{
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    return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
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}
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static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
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{
272
    int bus_offset;
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    if (pci_dev->devfn & 1)
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        bus_offset = 16;
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    else
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        bus_offset = 0;
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    return bus_offset + irq_num;
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}
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static void pci_apb_set_irq(void *opaque, int irq_num, int level)
281
{
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    APBState *s = opaque;
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    /* PCI IRQ map onto the first 32 INO.  */
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    if (irq_num < 32) {
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        if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
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            APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
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            qemu_set_irq(s->pci_irqs[irq_num], level);
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        } else {
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            APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
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            qemu_irq_lower(s->pci_irqs[irq_num]);
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        }
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    }
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}
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static void apb_pci_bridge_init(PCIBus *b)
297
{
298
    PCIDevice *dev = pci_bridge_get_device(b);
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300
    /*
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     * command register:
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     * According to PCI bridge spec, after reset
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     *   bus master bit is off
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     *   memory space enable bit is off
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     * According to manual (805-1251.pdf).
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     *   the reset value should be zero unless the boot pin is tied high
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     *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
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     */
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    pci_set_word(dev->config + PCI_COMMAND,
310
                 PCI_COMMAND_MEMORY);
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    pci_set_word(dev->config + PCI_STATUS,
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                 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
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                 PCI_STATUS_DEVSEL_MEDIUM);
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    pci_set_byte(dev->config + PCI_REVISION_ID, 0x11);
315
    pci_set_byte(dev->config + PCI_HEADER_TYPE,
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                 pci_get_byte(dev->config + PCI_HEADER_TYPE) |
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                 PCI_HEADER_TYPE_MULTI_FUNCTION);
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}
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PCIBus *pci_apb_init(target_phys_addr_t special_base,
321
                     target_phys_addr_t mem_base,
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                     qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
323
{
324
    DeviceState *dev;
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    SysBusDevice *s;
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    APBState *d;
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    unsigned int i;
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    /* Ultrasparc PBM main bus */
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    dev = qdev_create(NULL, "pbm");
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    qdev_init_nofail(dev);
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    s = sysbus_from_qdev(dev);
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    /* apb_config */
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    sysbus_mmio_map(s, 0, special_base);
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    /* PCI configuration space */
336
    sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
337
    /* pci_ioport */
338
    sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
339
    d = FROM_SYSBUS(APBState, s);
340

    
341
    d->bus = pci_register_bus(&d->busdev.qdev, "pci",
342
                                         pci_apb_set_irq, pci_pbm_map_irq, d,
343
                                         0, 32);
344
    pci_bus_set_mem_base(d->bus, mem_base);
345

    
346
    for (i = 0; i < 32; i++) {
347
        sysbus_connect_irq(s, i, pic[i]);
348
    }
349

    
350
    pci_create_simple(d->bus, 0, "pbm");
351

    
352
    /* APB secondary busses */
353
    *bus2 = pci_bridge_init(d->bus, PCI_DEVFN(1, 0), true,
354
                            PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
355
                            pci_apb_map_irq,
356
                            "Advanced PCI Bus secondary bridge 1");
357
    apb_pci_bridge_init(*bus2);
358

    
359
    *bus3 = pci_bridge_init(d->bus, PCI_DEVFN(1, 1), true,
360
                            PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
361
                            pci_apb_map_irq,
362
                            "Advanced PCI Bus secondary bridge 2");
363
    apb_pci_bridge_init(*bus3);
364

    
365
    return d->bus;
366
}
367

    
368
static void pci_pbm_reset(DeviceState *d)
369
{
370
    unsigned int i;
371
    APBState *s = container_of(d, APBState, busdev.qdev);
372

    
373
    for (i = 0; i < 8; i++) {
374
        s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
375
    }
376

    
377
    if (s->nr_resets++ == 0) {
378
        /* Power on reset */
379
        s->reset_control = POR;
380
    }
381
}
382

    
383
static int pci_pbm_init_device(SysBusDevice *dev)
384
{
385
    APBState *s;
386
    int pci_config, apb_config, pci_ioport;
387
    unsigned int i;
388

    
389
    s = FROM_SYSBUS(APBState, dev);
390
    for (i = 0; i < 8; i++) {
391
        s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
392
    }
393
    for (i = 0; i < 32; i++) {
394
        sysbus_init_irq(dev, &s->pci_irqs[i]);
395
    }
396

    
397
    /* apb_config */
398
    apb_config = cpu_register_io_memory(apb_config_read,
399
                                        apb_config_write, s);
400
    /* at region 0 */
401
    sysbus_init_mmio(dev, 0x10000ULL, apb_config);
402

    
403
    /* PCI configuration space */
404
    s->pci_config_handler.read = apb_pci_config_read;
405
    s->pci_config_handler.write = apb_pci_config_write;
406
    pci_config = cpu_register_io_memory_simple(&s->pci_config_handler);
407
    assert(pci_config >= 0);
408
    /* at region 1 */
409
    sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
410

    
411
    /* pci_ioport */
412
    pci_ioport = cpu_register_io_memory(pci_apb_ioread,
413
                                        pci_apb_iowrite, s);
414
    /* at region 2 */
415
    sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
416

    
417
    return 0;
418
}
419

    
420
static int pbm_pci_host_init(PCIDevice *d)
421
{
422
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN);
423
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE);
424
    pci_set_word(d->config + PCI_COMMAND,
425
                 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
426
    pci_set_word(d->config + PCI_STATUS,
427
                 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
428
                 PCI_STATUS_DEVSEL_MEDIUM);
429
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
430
    return 0;
431
}
432

    
433
static PCIDeviceInfo pbm_pci_host_info = {
434
    .qdev.name = "pbm",
435
    .qdev.size = sizeof(PCIDevice),
436
    .init      = pbm_pci_host_init,
437
    .is_bridge = 1,
438
};
439

    
440
static SysBusDeviceInfo pbm_host_info = {
441
    .qdev.name = "pbm",
442
    .qdev.size = sizeof(APBState),
443
    .qdev.reset = pci_pbm_reset,
444
    .init = pci_pbm_init_device,
445
};
446
static void pbm_register_devices(void)
447
{
448
    sysbus_register_withprop(&pbm_host_info);
449
    pci_qdev_register(&pbm_pci_host_info);
450
}
451

    
452
device_init(pbm_register_devices)