Revision 7cc0dd20
b/hw/mips_malta.c | ||
---|---|---|
435 | 435 |
cpu_register_physical_memory(base, 0x900, malta); |
436 | 436 |
cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta); |
437 | 437 |
|
438 |
s->display = qemu_chr_open("vc:320x200"); |
|
438 |
s->display = qemu_chr_open("fpga", "vc:320x200");
|
|
439 | 439 |
qemu_chr_printf(s->display, "\e[HMalta LEDBAR\r\n"); |
440 | 440 |
qemu_chr_printf(s->display, "+--------+\r\n"); |
441 | 441 |
qemu_chr_printf(s->display, "+ +\r\n"); |
... | ... | |
446 | 446 |
qemu_chr_printf(s->display, "+ +\r\n"); |
447 | 447 |
qemu_chr_printf(s->display, "+--------+\r\n"); |
448 | 448 |
|
449 |
uart_chr = qemu_chr_open("vc:80Cx24C"); |
|
449 |
uart_chr = qemu_chr_open("cbus", "vc:80Cx24C");
|
|
450 | 450 |
qemu_chr_printf(uart_chr, "CBUS UART\r\n"); |
451 | 451 |
s->uart = |
452 | 452 |
serial_mm_init(base + 0x900, 3, env->irq[2], 230400, uart_chr, 1); |
b/hw/omap1.c | ||
---|---|---|
2017 | 2017 |
s->fclk = fclk; |
2018 | 2018 |
s->irq = irq; |
2019 | 2019 |
s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16, |
2020 |
chr ?: qemu_chr_open("null"), 1); |
|
2020 |
chr ?: qemu_chr_open("null", "null"), 1);
|
|
2021 | 2021 |
|
2022 | 2022 |
return s; |
2023 | 2023 |
} |
... | ... | |
2128 | 2128 |
/* TODO: Should reuse or destroy current s->serial */ |
2129 | 2129 |
s->serial = serial_mm_init(s->base, 2, s->irq, |
2130 | 2130 |
omap_clk_getrate(s->fclk) / 16, |
2131 |
chr ?: qemu_chr_open("null"), 1); |
|
2131 |
chr ?: qemu_chr_open("null", "null"), 1);
|
|
2132 | 2132 |
} |
2133 | 2133 |
|
2134 | 2134 |
/* MPU Clock/Reset/Power Mode Control */ |
b/hw/omap2.c | ||
---|---|---|
2185 | 2185 |
s->irq = irq; |
2186 | 2186 |
omap_sti_reset(s); |
2187 | 2187 |
|
2188 |
s->chr = chr ?: qemu_chr_open("null"); |
|
2188 |
s->chr = chr ?: qemu_chr_open("null", "null");
|
|
2189 | 2189 |
|
2190 | 2190 |
iomemtype = l4_register_io_memory(0, omap_sti_readfn, |
2191 | 2191 |
omap_sti_writefn, s); |
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