Revision 7cc2cc3e
b/target-i386/kvm.c | ||
---|---|---|
263 | 263 |
} |
264 | 264 |
} |
265 | 265 |
|
266 |
static void kvm_inject_x86_mce_on(CPUState *env, struct kvm_x86_mce *mce, |
|
267 |
int flag) |
|
268 |
{ |
|
269 |
struct kvm_x86_mce_data data = { |
|
270 |
.env = env, |
|
271 |
.mce = mce, |
|
272 |
.abort_on_error = (flag & ABORT_ON_ERROR), |
|
273 |
}; |
|
274 |
|
|
275 |
if (!env->mcg_cap) { |
|
276 |
fprintf(stderr, "MCE support is not enabled!\n"); |
|
277 |
return; |
|
278 |
} |
|
279 |
|
|
280 |
run_on_cpu(env, kvm_do_inject_x86_mce, &data); |
|
281 |
} |
|
282 |
|
|
266 | 283 |
static void kvm_mce_broadcast_rest(CPUState *env); |
267 | 284 |
#endif |
268 | 285 |
|
... | ... | |
278 | 295 |
.addr = addr, |
279 | 296 |
.misc = misc, |
280 | 297 |
}; |
281 |
struct kvm_x86_mce_data data = { |
|
282 |
.env = cenv, |
|
283 |
.mce = &mce, |
|
284 |
}; |
|
285 |
|
|
286 |
if (!cenv->mcg_cap) { |
|
287 |
fprintf(stderr, "MCE support is not enabled!\n"); |
|
288 |
return; |
|
289 |
} |
|
290 | 298 |
|
291 | 299 |
if (flag & MCE_BROADCAST) { |
292 | 300 |
kvm_mce_broadcast_rest(cenv); |
293 | 301 |
} |
294 | 302 |
|
295 |
run_on_cpu(cenv, kvm_do_inject_x86_mce, &data);
|
|
303 |
kvm_inject_x86_mce_on(cenv, &mce, flag);
|
|
296 | 304 |
#else |
297 | 305 |
if (flag & ABORT_ON_ERROR) { |
298 | 306 |
abort(); |
... | ... | |
1708 | 1716 |
#ifdef KVM_CAP_MCE |
1709 | 1717 |
static void kvm_mce_broadcast_rest(CPUState *env) |
1710 | 1718 |
{ |
1719 |
struct kvm_x86_mce mce = { |
|
1720 |
.bank = 1, |
|
1721 |
.status = MCI_STATUS_VAL | MCI_STATUS_UC, |
|
1722 |
.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, |
|
1723 |
.addr = 0, |
|
1724 |
.misc = 0, |
|
1725 |
}; |
|
1711 | 1726 |
CPUState *cenv; |
1712 | 1727 |
|
1713 | 1728 |
/* Broadcast MCA signal for processor version 06H_EH and above */ |
... | ... | |
1716 | 1731 |
if (cenv == env) { |
1717 | 1732 |
continue; |
1718 | 1733 |
} |
1719 |
kvm_inject_x86_mce(cenv, 1, MCI_STATUS_VAL | MCI_STATUS_UC, |
|
1720 |
MCG_STATUS_MCIP | MCG_STATUS_RIPV, 0, 0, |
|
1721 |
ABORT_ON_ERROR); |
|
1734 |
kvm_inject_x86_mce_on(cenv, &mce, ABORT_ON_ERROR); |
|
1722 | 1735 |
} |
1723 | 1736 |
} |
1724 | 1737 |
} |
... | ... | |
1767 | 1780 |
|
1768 | 1781 |
static void kvm_mce_inj_srao_memscrub2(CPUState *env, target_phys_addr_t paddr) |
1769 | 1782 |
{ |
1770 |
uint64_t status; |
|
1771 |
|
|
1772 |
status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
|
1773 |
| MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S |
|
1774 |
| 0xc0; |
|
1775 |
kvm_inject_x86_mce(env, 9, status, |
|
1776 |
MCG_STATUS_MCIP | MCG_STATUS_RIPV, paddr, |
|
1777 |
(MCM_ADDR_PHYS << 6) | 0xc, ABORT_ON_ERROR); |
|
1783 |
struct kvm_x86_mce mce = { |
|
1784 |
.bank = 9, |
|
1785 |
.status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
|
1786 |
| MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S |
|
1787 |
| 0xc0, |
|
1788 |
.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, |
|
1789 |
.addr = paddr, |
|
1790 |
.misc = (MCM_ADDR_PHYS << 6) | 0xc, |
|
1791 |
}; |
|
1778 | 1792 |
|
1793 |
kvm_inject_x86_mce_on(env, &mce, ABORT_ON_ERROR); |
|
1779 | 1794 |
kvm_mce_broadcast_rest(env); |
1780 | 1795 |
} |
1781 | 1796 |
|
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