Archipelago » qemu

/*

 *  CRIS emulation for qemu: main translation routines.

 *

 *  Copyright (c) 2008 AXIS Communications AB

 *  Written by Edgar E. Iglesias.

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

/*

 * FIXME:

 * The condition code translation is in need of attention.

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include <assert.h>

#include "cpu.h"

#include "exec-all.h"

#include "disas.h"

#include "tcg-op.h"

#include "helper.h"

#include "crisv32-decode.h"

#include "qemu-common.h"

#define DISAS_CRIS 0

#if DISAS_CRIS

#define DIS(x) x

#else

#define DIS(x)

#endif

#define D(x)

#define BUG() (gen_BUG(dc, __FILE__, __LINE__))

#define BUG_ON(x) ({if (x) BUG();})

#define DISAS_SWI 5

/* Used by the decoder.  */

#define EXTRACT_FIELD(src, start, end) \

            (((src) >> start) & ((1 << (end - start + 1)) - 1))

#define CC_MASK_NZ 0xc

#define CC_MASK_NZV 0xe

#define CC_MASK_NZVC 0xf

#define CC_MASK_RNZV 0x10e

TCGv cpu_env;

TCGv cpu_T[2];

TCGv cpu_R[16];

TCGv cpu_PR[16];

TCGv cc_x;

TCGv cc_src;

TCGv cc_dest;

TCGv cc_result;

TCGv cc_op;

TCGv cc_size;

TCGv cc_mask;

TCGv env_btaken;

TCGv env_btarget;

TCGv env_pc;

#include "gen-icount.h"

/* This is the state at translation time.  */

typedef struct DisasContext {

        CPUState *env;

        target_ulong pc, ppc;

        /* Decoder.  */

        uint32_t ir;

        uint32_t opcode;

        unsigned int op1;

        unsigned int op2;

        unsigned int zsize, zzsize;

        unsigned int mode;

        unsigned int postinc;

        int update_cc;

        int cc_op;

        int cc_size;

        uint32_t cc_mask;

        int cc_size_uptodate; /* -1 invalid or last written value.  */

        int cc_x_uptodate;  /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate.  */

        int flags_uptodate; /* Wether or not $ccs is uptodate.  */

        int flagx_known; /* Wether or not flags_x has the x flag known at

                            translation time.  */

        int flags_x;

        int clear_x; /* Clear x after this insn?  */

        int cpustate_changed;

        unsigned int tb_flags; /* tb dependent flags.  */

        int is_jmp;

#define JMP_NOJMP    0

#define JMP_DIRECT   1

#define JMP_INDIRECT 2

        int jmp; /* 0=nojmp, 1=direct, 2=indirect.  */ 

        uint32_t jmp_pc;

        int delayed_branch;

        struct TranslationBlock *tb;

        int singlestep_enabled;

} DisasContext;

static void gen_BUG(DisasContext *dc, const char *file, int line)

{

        printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);

        fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);

        cpu_abort(dc->env, "%s:%d\n", file, line);

}

const char *regnames[] =

{

        "$r0", "$r1", "$r2", "$r3",

        "$r4", "$r5", "$r6", "$r7",

        "$r8", "$r9", "$r10", "$r11",

        "$r12", "$r13", "$sp", "$acr",

};

const char *pregnames[] =

{

        "$bz", "$vr", "$pid", "$srs",

        "$wz", "$exs", "$eda", "$mof",

        "$dz", "$ebp", "$erp", "$srp",

        "$nrp", "$ccs", "$usp", "$spc",

};

/* We need this table to handle preg-moves with implicit width.  */

int preg_sizes[] = {

        1, /* bz.  */

        1, /* vr.  */

        4, /* pid.  */

        1, /* srs.  */

        2, /* wz.  */

        4, 4, 4,

        4, 4, 4, 4,

        4, 4, 4, 4,

};

#define t_gen_mov_TN_env(tn, member) \

 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))

#define t_gen_mov_env_TN(member, tn) \

 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))

static inline void t_gen_mov_TN_reg(TCGv tn, int r)

{

        if (r < 0 || r > 15)

                fprintf(stderr, "wrong register read $r%d\n", r);

        tcg_gen_mov_tl(tn, cpu_R[r]);

}

static inline void t_gen_mov_reg_TN(int r, TCGv tn)

{

        if (r < 0 || r > 15)

                fprintf(stderr, "wrong register write $r%d\n", r);

        tcg_gen_mov_tl(cpu_R[r], tn);

}

static inline void _t_gen_mov_TN_env(TCGv tn, int offset)

{

        if (offset > sizeof (CPUState))

                fprintf(stderr, "wrong load from env from off=%d\n", offset);

        tcg_gen_ld_tl(tn, cpu_env, offset);

}

static inline void _t_gen_mov_env_TN(int offset, TCGv tn)

{

        if (offset > sizeof (CPUState))

                fprintf(stderr, "wrong store to env at off=%d\n", offset);

        tcg_gen_st_tl(tn, cpu_env, offset);

}

static inline void t_gen_mov_TN_preg(TCGv tn, int r)

{

        if (r < 0 || r > 15)

                fprintf(stderr, "wrong register read $p%d\n", r);

        if (r == PR_BZ || r == PR_WZ || r == PR_DZ)

                tcg_gen_mov_tl(tn, tcg_const_tl(0));

        else if (r == PR_VR)

                tcg_gen_mov_tl(tn, tcg_const_tl(32));

        else if (r == PR_EXS) {

                printf("read from EXS!\n");

                tcg_gen_mov_tl(tn, cpu_PR[r]);

        }

        else if (r == PR_EDA) {

                printf("read from EDA!\n");

                tcg_gen_mov_tl(tn, cpu_PR[r]);

        }

        else

                tcg_gen_mov_tl(tn, cpu_PR[r]);

}

static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)

{

        if (r < 0 || r > 15)

                fprintf(stderr, "wrong register write $p%d\n", r);

        if (r == PR_BZ || r == PR_WZ || r == PR_DZ)

                return;

        else if (r == PR_SRS)

                tcg_gen_andi_tl(cpu_PR[r], tn, 3);

        else {

                tcg_gen_mov_tl(cpu_PR[r], tn);

                if (r == PR_PID) 

                        tcg_gen_helper_0_1(helper_tlb_flush_pid, tn);

                else if (r == PR_CCS)

                        dc->cpustate_changed = 1;

        }

}

static inline void t_gen_raise_exception(uint32_t index)

{

        tcg_gen_helper_0_1(helper_raise_exception, tcg_const_tl(index));

}

static void t_gen_lsl(TCGv d, TCGv a, TCGv b)

{

        int l1;

        l1 = gen_new_label();

        /* Speculative shift. */

        tcg_gen_shl_tl(d, a, b);

        tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);

        /* Clear dst if shift operands were to large.  */

        tcg_gen_movi_tl(d, 0);

        gen_set_label(l1);

}

static void t_gen_lsr(TCGv d, TCGv a, TCGv b)

{

        int l1;

        l1 = gen_new_label();

        /* Speculative shift. */

        tcg_gen_shr_tl(d, a, b);

        tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);

        /* Clear dst if shift operands were to large.  */

        tcg_gen_movi_tl(d, 0);

        gen_set_label(l1);

}

static void t_gen_asr(TCGv d, TCGv a, TCGv b)

{

        int l1;

        l1 = gen_new_label();

        /* Speculative shift. */

        tcg_gen_sar_tl(d, a, b);

        tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);

        /* Clear dst if shift operands were to large.  */

        tcg_gen_sar_tl(d, a, tcg_const_tl(30));

        gen_set_label(l1);

}

/* 64-bit signed mul, lower result in d and upper in d2.  */

static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)

{

        TCGv t0, t1;

        t0 = tcg_temp_new(TCG_TYPE_I64);

        t1 = tcg_temp_new(TCG_TYPE_I64);

        tcg_gen_ext32s_i64(t0, a);

        tcg_gen_ext32s_i64(t1, b);

        tcg_gen_mul_i64(t0, t0, t1);

        tcg_gen_trunc_i64_i32(d, t0);

        tcg_gen_shri_i64(t0, t0, 32);

        tcg_gen_trunc_i64_i32(d2, t0);

        tcg_temp_free(t0);

        tcg_temp_free(t1);

}

/* 64-bit unsigned muls, lower result in d and upper in d2.  */

static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)

{

        TCGv t0, t1;

        t0 = tcg_temp_new(TCG_TYPE_I64);

        t1 = tcg_temp_new(TCG_TYPE_I64);

        tcg_gen_extu_i32_i64(t0, a);

        tcg_gen_extu_i32_i64(t1, b);

        tcg_gen_mul_i64(t0, t0, t1);

        tcg_gen_trunc_i64_i32(d, t0);

        tcg_gen_shri_i64(t0, t0, 32);

        tcg_gen_trunc_i64_i32(d2, t0);

        tcg_temp_free(t0);

        tcg_temp_free(t1);

}

/* 32bit branch-free binary search for counting leading zeros.  */

static void t_gen_lz_i32(TCGv d, TCGv x)

{

        TCGv y, m, n;

        y = tcg_temp_new(TCG_TYPE_I32);

        m = tcg_temp_new(TCG_TYPE_I32);

        n = tcg_temp_new(TCG_TYPE_I32);

        /* y = -(x >> 16)  */

        tcg_gen_shri_i32(y, x, 16);

        tcg_gen_neg_i32(y, y);

        /* m = (y >> 16) & 16  */

        tcg_gen_sari_i32(m, y, 16);

        tcg_gen_andi_i32(m, m, 16);

        /* n = 16 - m  */

        tcg_gen_sub_i32(n, tcg_const_i32(16), m);

        /* x = x >> m  */

        tcg_gen_shr_i32(x, x, m);

        /* y = x - 0x100  */

        tcg_gen_subi_i32(y, x, 0x100);

        /* m = (y >> 16) & 8  */

        tcg_gen_sari_i32(m, y, 16);

        tcg_gen_andi_i32(m, m, 8);

        /* n = n + m  */

        tcg_gen_add_i32(n, n, m);

        /* x = x << m  */

        tcg_gen_shl_i32(x, x, m);

        /* y = x - 0x1000  */

        tcg_gen_subi_i32(y, x, 0x1000);

        /* m = (y >> 16) & 4  */

        tcg_gen_sari_i32(m, y, 16);

        tcg_gen_andi_i32(m, m, 4);

        /* n = n + m  */

        tcg_gen_add_i32(n, n, m);

        /* x = x << m  */

        tcg_gen_shl_i32(x, x, m);

        /* y = x - 0x4000  */

        tcg_gen_subi_i32(y, x, 0x4000);

        /* m = (y >> 16) & 2  */

        tcg_gen_sari_i32(m, y, 16);

        tcg_gen_andi_i32(m, m, 2);

        /* n = n + m  */

        tcg_gen_add_i32(n, n, m);

        /* x = x << m  */

        tcg_gen_shl_i32(x, x, m);

        /* y = x >> 14  */

        tcg_gen_shri_i32(y, x, 14);

        /* m = y & ~(y >> 1)  */

        tcg_gen_sari_i32(m, y, 1);

        tcg_gen_not_i32(m, m);

        tcg_gen_and_i32(m, m, y);

        /* d = n + 2 - m  */

        tcg_gen_addi_i32(d, n, 2);

        tcg_gen_sub_i32(d, d, m);

        tcg_temp_free(y);

        tcg_temp_free(m);

        tcg_temp_free(n);

}

static void t_gen_btst(TCGv d, TCGv a, TCGv b)

{

        TCGv sbit;

        TCGv bset;

        TCGv t0;

        int l1;

        /* des ref:

           The N flag is set according to the selected bit in the dest reg.

           The Z flag is set if the selected bit and all bits to the right are

           zero.

           The X flag is cleared.

           Other flags are left untouched.

           The destination reg is not affected.

        unsigned int fz, sbit, bset, mask, masked_t0;

        sbit = T1 & 31;

        bset = !!(T0 & (1 << sbit));

        mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;

        masked_t0 = T0 & mask;

        fz = !(masked_t0 | bset);

        // Clear the X, N and Z flags.

        T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);

        // Set the N and Z flags accordingly.

        T0 |= (bset << 3) | (fz << 2);

        */

        l1 = gen_new_label();

        sbit = tcg_temp_new(TCG_TYPE_TL);

        bset = tcg_temp_new(TCG_TYPE_TL);

        t0 = tcg_temp_new(TCG_TYPE_TL);

        /* Compute bset and sbit.  */

        tcg_gen_andi_tl(sbit, b, 31);

        tcg_gen_shl_tl(t0, tcg_const_tl(1), sbit);

        tcg_gen_and_tl(bset, a, t0);

        tcg_gen_shr_tl(bset, bset, sbit);

        /* Displace to N_FLAG.  */

        tcg_gen_shli_tl(bset, bset, 3);

        tcg_gen_shl_tl(sbit, tcg_const_tl(2), sbit);

        tcg_gen_subi_tl(sbit, sbit, 1);

        tcg_gen_and_tl(sbit, a, sbit);

        tcg_gen_andi_tl(d, cpu_PR[PR_CCS], ~(X_FLAG | N_FLAG | Z_FLAG));

        /* or in the N_FLAG.  */

        tcg_gen_or_tl(d, d, bset);

        tcg_gen_brcondi_tl(TCG_COND_NE, sbit, 0, l1);

        /* or in the Z_FLAG.  */

        tcg_gen_ori_tl(d, d, Z_FLAG);

        gen_set_label(l1);

        tcg_temp_free(sbit);

        tcg_temp_free(bset);

}

static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)

{

        int l1;

        l1 = gen_new_label();

        /* 

         * d <<= 1

         * if (d >= s)

         *    d -= s;

         */

        tcg_gen_shli_tl(d, a, 1);

        tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);

        tcg_gen_sub_tl(d, d, b);

        gen_set_label(l1);

}

/* Extended arithmetics on CRIS.  */

static inline void t_gen_add_flag(TCGv d, int flag)

{

        TCGv c;

        c = tcg_temp_new(TCG_TYPE_TL);

        t_gen_mov_TN_preg(c, PR_CCS);

        /* Propagate carry into d.  */

        tcg_gen_andi_tl(c, c, 1 << flag);

        if (flag)

                tcg_gen_shri_tl(c, c, flag);

        tcg_gen_add_tl(d, d, c);

        tcg_temp_free(c);

}

static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)

{

        if (dc->flagx_known) {

                if (dc->flags_x) {

                        TCGv c;

                        c = tcg_temp_new(TCG_TYPE_TL);

                        t_gen_mov_TN_preg(c, PR_CCS);

                        /* C flag is already at bit 0.  */

                        tcg_gen_andi_tl(c, c, C_FLAG);

                        tcg_gen_add_tl(d, d, c);

                        tcg_temp_free(c);

                }

        } else {

                TCGv x, c;

                x = tcg_temp_new(TCG_TYPE_TL);

                c = tcg_temp_new(TCG_TYPE_TL);

                t_gen_mov_TN_preg(x, PR_CCS);

                tcg_gen_mov_tl(c, x);

                /* Propagate carry into d if X is set. Branch free.  */

                tcg_gen_andi_tl(c, c, C_FLAG);

                tcg_gen_andi_tl(x, x, X_FLAG);

                tcg_gen_shri_tl(x, x, 4);

                tcg_gen_and_tl(x, x, c);

                tcg_gen_add_tl(d, d, x);        

                tcg_temp_free(x);

                tcg_temp_free(c);

        }

}

static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)

{

        if (dc->flagx_known) {

                if (dc->flags_x) {

                        TCGv c;

                        c = tcg_temp_new(TCG_TYPE_TL);

                        t_gen_mov_TN_preg(c, PR_CCS);

                        /* C flag is already at bit 0.  */

                        tcg_gen_andi_tl(c, c, C_FLAG);

                        tcg_gen_sub_tl(d, d, c);

                        tcg_temp_free(c);

                }

        } else {

                TCGv x, c;

                x = tcg_temp_new(TCG_TYPE_TL);

                c = tcg_temp_new(TCG_TYPE_TL);

                t_gen_mov_TN_preg(x, PR_CCS);

                tcg_gen_mov_tl(c, x);

                /* Propagate carry into d if X is set. Branch free.  */

                tcg_gen_andi_tl(c, c, C_FLAG);

                tcg_gen_andi_tl(x, x, X_FLAG);

                tcg_gen_shri_tl(x, x, 4);

                tcg_gen_and_tl(x, x, c);

                tcg_gen_sub_tl(d, d, x);

                tcg_temp_free(x);

                tcg_temp_free(c);

        }

}

/* Swap the two bytes within each half word of the s operand.

   T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff)  */

static inline void t_gen_swapb(TCGv d, TCGv s)

{

        TCGv t, org_s;

        t = tcg_temp_new(TCG_TYPE_TL);

        org_s = tcg_temp_new(TCG_TYPE_TL);

        /* d and s may refer to the same object.  */

        tcg_gen_mov_tl(org_s, s);

        tcg_gen_shli_tl(t, org_s, 8);

        tcg_gen_andi_tl(d, t, 0xff00ff00);

        tcg_gen_shri_tl(t, org_s, 8);

        tcg_gen_andi_tl(t, t, 0x00ff00ff);

        tcg_gen_or_tl(d, d, t);

        tcg_temp_free(t);

        tcg_temp_free(org_s);

}

/* Swap the halfwords of the s operand.  */

static inline void t_gen_swapw(TCGv d, TCGv s)

{

        TCGv t;

        /* d and s refer the same object.  */

        t = tcg_temp_new(TCG_TYPE_TL);

        tcg_gen_mov_tl(t, s);

        tcg_gen_shli_tl(d, t, 16);

        tcg_gen_shri_tl(t, t, 16);

        tcg_gen_or_tl(d, d, t);

        tcg_temp_free(t);

}

/* Reverse the within each byte.

   T0 = (((T0 << 7) & 0x80808080) |

   ((T0 << 5) & 0x40404040) |

   ((T0 << 3) & 0x20202020) |

   ((T0 << 1) & 0x10101010) |

   ((T0 >> 1) & 0x08080808) |

   ((T0 >> 3) & 0x04040404) |

   ((T0 >> 5) & 0x02020202) |

   ((T0 >> 7) & 0x01010101));

 */

static inline void t_gen_swapr(TCGv d, TCGv s)

{

        struct {

                int shift; /* LSL when positive, LSR when negative.  */

                uint32_t mask;

        } bitrev [] = {

                {7, 0x80808080},

                {5, 0x40404040},

                {3, 0x20202020},

                {1, 0x10101010},

                {-1, 0x08080808},

                {-3, 0x04040404},

                {-5, 0x02020202},

                {-7, 0x01010101}

        };

        int i;

        TCGv t, org_s;

        /* d and s refer the same object.  */

        t = tcg_temp_new(TCG_TYPE_TL);

        org_s = tcg_temp_new(TCG_TYPE_TL);

        tcg_gen_mov_tl(org_s, s);

        tcg_gen_shli_tl(t, org_s,  bitrev[0].shift);

        tcg_gen_andi_tl(d, t,  bitrev[0].mask);

        for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {

                if (bitrev[i].shift >= 0) {

                        tcg_gen_shli_tl(t, org_s,  bitrev[i].shift);

                } else {

                        tcg_gen_shri_tl(t, org_s,  -bitrev[i].shift);

                }

                tcg_gen_andi_tl(t, t,  bitrev[i].mask);

                tcg_gen_or_tl(d, d, t);

        }

        tcg_temp_free(t);

        tcg_temp_free(org_s);

}

static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)

{

        TCGv btaken;

        int l1;

        l1 = gen_new_label();

        btaken = tcg_temp_new(TCG_TYPE_TL);

        /* Conditional jmp.  */

        tcg_gen_mov_tl(btaken, env_btaken);

        tcg_gen_mov_tl(env_pc, pc_false);

        tcg_gen_brcondi_tl(TCG_COND_EQ, btaken, 0, l1);

        tcg_gen_mov_tl(env_pc, pc_true);

        gen_set_label(l1);

        tcg_temp_free(btaken);

}

static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)

{

        TranslationBlock *tb;

        tb = dc->tb;

        if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {

                tcg_gen_goto_tb(n);

                tcg_gen_movi_tl(env_pc, dest);

                tcg_gen_exit_tb((long)tb + n);

        } else {

                tcg_gen_movi_tl(env_pc, dest);

                tcg_gen_exit_tb(0);

        }

}

/* Sign extend at translation time.  */

static int sign_extend(unsigned int val, unsigned int width)

{

        int sval;

        /* LSL.  */

        val <<= 31 - width;

        sval = val;

        /* ASR.  */

        sval >>= 31 - width;

        return sval;

}

static inline void cris_clear_x_flag(DisasContext *dc)

{

        if (dc->flagx_known && dc->flags_x)

                dc->flags_uptodate = 0;

        dc->flagx_known = 1;

        dc->flags_x = 0;

}

static void cris_flush_cc_state(DisasContext *dc)

{

        if (dc->cc_size_uptodate != dc->cc_size) {

                tcg_gen_movi_tl(cc_size, dc->cc_size);

                dc->cc_size_uptodate = dc->cc_size;

        }

        tcg_gen_movi_tl(cc_op, dc->cc_op);

        tcg_gen_movi_tl(cc_mask, dc->cc_mask);

}

static void cris_evaluate_flags(DisasContext *dc)

{

        if (!dc->flags_uptodate) {

                cris_flush_cc_state(dc);

                switch (dc->cc_op)

                {

                        case CC_OP_MCP:

                                tcg_gen_helper_0_0(helper_evaluate_flags_mcp);

                                break;

                        case CC_OP_MULS:

                                tcg_gen_helper_0_0(helper_evaluate_flags_muls);

                                break;

                        case CC_OP_MULU:

                                tcg_gen_helper_0_0(helper_evaluate_flags_mulu);

                                break;

                        case CC_OP_MOVE:

                        case CC_OP_AND:

                        case CC_OP_OR:

                        case CC_OP_XOR:

                        case CC_OP_ASR:

                        case CC_OP_LSR:

                        case CC_OP_LSL:

                                switch (dc->cc_size)

                                {

                                        case 4:

                                                tcg_gen_helper_0_0(helper_evaluate_flags_move_4);

                                                break;

                                        case 2:

                                                tcg_gen_helper_0_0(helper_evaluate_flags_move_2);

                                                break;

                                        default:

                                                tcg_gen_helper_0_0(helper_evaluate_flags);

                                                break;

                                }

                                break;

                        case CC_OP_FLAGS:

                                /* live.  */

                                break;

                        default:

                        {

                                switch (dc->cc_size)

                                {

                                        case 4:

                                                tcg_gen_helper_0_0(helper_evaluate_flags_alu_4);

                                                break;

                                        default:

                                                tcg_gen_helper_0_0(helper_evaluate_flags);

                                                break;

                                }

                        }

                        break;

                }

                if (dc->flagx_known) {

                        if (dc->flags_x)

                                tcg_gen_ori_tl(cpu_PR[PR_CCS], 

                                               cpu_PR[PR_CCS], X_FLAG);

                        else

                                tcg_gen_andi_tl(cpu_PR[PR_CCS], 

                                                cpu_PR[PR_CCS], ~X_FLAG);

                }

                dc->flags_uptodate = 1;

        }

}

static void cris_cc_mask(DisasContext *dc, unsigned int mask)

{

        uint32_t ovl;

        if (!mask) {

                dc->update_cc = 0;

                return;

        }        

        /* Check if we need to evaluate the condition codes due to 

           CC overlaying.  */

        ovl = (dc->cc_mask ^ mask) & ~mask;

        if (ovl) {

                /* TODO: optimize this case. It trigs all the time.  */

                cris_evaluate_flags (dc);

        }

        dc->cc_mask = mask;

        dc->update_cc = 1;

}

static void cris_update_cc_op(DisasContext *dc, int op, int size)

{

        dc->cc_op = op;

        dc->cc_size = size;

        dc->flags_uptodate = 0;

}

static inline void cris_update_cc_x(DisasContext *dc)

{

        /* Save the x flag state at the time of the cc snapshot.  */

        if (dc->flagx_known) {

                if (dc->cc_x_uptodate == (2 | dc->flags_x))

                        return;

                tcg_gen_movi_tl(cc_x, dc->flags_x);

                dc->cc_x_uptodate = 2 | dc->flags_x;

        }

        else {

                tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);

                dc->cc_x_uptodate = 1;

        }

}

/* Update cc prior to executing ALU op. Needs source operands untouched.  */

static void cris_pre_alu_update_cc(DisasContext *dc, int op, 

                                   TCGv dst, TCGv src, int size)

{

        if (dc->update_cc) {

                cris_update_cc_op(dc, op, size);

                tcg_gen_mov_tl(cc_src, src);

                if (op != CC_OP_MOVE

                    && op != CC_OP_AND

                    && op != CC_OP_OR

                    && op != CC_OP_XOR

                    && op != CC_OP_ASR

                    && op != CC_OP_LSR

                    && op != CC_OP_LSL)

                        tcg_gen_mov_tl(cc_dest, dst);

                cris_update_cc_x(dc);

        }

}

/* Update cc after executing ALU op. needs the result.  */

static inline void cris_update_result(DisasContext *dc, TCGv res)

{

        if (dc->update_cc) {

                if (dc->cc_size == 4 && 

                    (dc->cc_op == CC_OP_SUB

                     || dc->cc_op == CC_OP_ADD))

                        return;

                tcg_gen_mov_tl(cc_result, res);

        }

}

/* Returns one if the write back stage should execute.  */

static void cris_alu_op_exec(DisasContext *dc, int op, 

                               TCGv dst, TCGv a, TCGv b, int size)

{

        /* Emit the ALU insns.  */

        switch (op)

        {

                case CC_OP_ADD:

                        tcg_gen_add_tl(dst, a, b);

                        /* Extended arithmetics.  */

                        t_gen_addx_carry(dc, dst);

                        break;

                case CC_OP_ADDC:

                        tcg_gen_add_tl(dst, a, b);

                        t_gen_add_flag(dst, 0); /* C_FLAG.  */

                        break;

                case CC_OP_MCP:

                        tcg_gen_add_tl(dst, a, b);

                        t_gen_add_flag(dst, 8); /* R_FLAG.  */

                        break;

                case CC_OP_SUB:

                        tcg_gen_sub_tl(dst, a, b);

                        /* Extended arithmetics.  */

                        t_gen_subx_carry(dc, dst);

                        break;

                case CC_OP_MOVE:

                        tcg_gen_mov_tl(dst, b);

                        break;

                case CC_OP_OR:

                        tcg_gen_or_tl(dst, a, b);

                        break;

                case CC_OP_AND:

                        tcg_gen_and_tl(dst, a, b);

                        break;

                case CC_OP_XOR:

                        tcg_gen_xor_tl(dst, a, b);

                        break;

                case CC_OP_LSL:

                        t_gen_lsl(dst, a, b);

                        break;

                case CC_OP_LSR:

                        t_gen_lsr(dst, a, b);

                        break;

                case CC_OP_ASR:

                        t_gen_asr(dst, a, b);

                        break;

                case CC_OP_NEG:

                        tcg_gen_neg_tl(dst, b);

                        /* Extended arithmetics.  */

                        t_gen_subx_carry(dc, dst);

                        break;

                case CC_OP_LZ:

                        t_gen_lz_i32(dst, b);

                        break;

                case CC_OP_BTST:

                        t_gen_btst(dst, a, b);

                        break;

                case CC_OP_MULS:

                        t_gen_muls(dst, cpu_PR[PR_MOF], a, b);

                        break;

                case CC_OP_MULU:

                        t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);

                        break;

                case CC_OP_DSTEP:

                        t_gen_cris_dstep(dst, a, b);

                        break;

                case CC_OP_BOUND:

                {

                        int l1;

                        l1 = gen_new_label();

                        tcg_gen_mov_tl(dst, a);

                        tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);

                        tcg_gen_mov_tl(dst, b);

                        gen_set_label(l1);

                }

                break;

                case CC_OP_CMP:

                        tcg_gen_sub_tl(dst, a, b);

                        /* Extended arithmetics.  */

                        t_gen_subx_carry(dc, dst);

                        break;

                default:

                        fprintf (logfile, "illegal ALU op.\n");

                        BUG();

                        break;

        }

        if (size == 1)

                tcg_gen_andi_tl(dst, dst, 0xff);

        else if (size == 2)

                tcg_gen_andi_tl(dst, dst, 0xffff);

}

static void cris_alu(DisasContext *dc, int op,

                               TCGv d, TCGv op_a, TCGv op_b, int size)

{

        TCGv tmp;

        int writeback;

        writeback = 1;

        tmp = cpu_T[0];

        if (op == CC_OP_CMP)

                writeback = 0;

        else if (size == 4) {

                tmp = d;

                writeback = 0;

        }

        cris_pre_alu_update_cc(dc, op, op_a, op_b, size);

        cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);

        cris_update_result(dc, tmp);

        /* Writeback.  */

        if (writeback) {

                if (size == 1)

                        tcg_gen_andi_tl(d, d, ~0xff);

                else

                        tcg_gen_andi_tl(d, d, ~0xffff);

                tcg_gen_or_tl(d, d, tmp);

        }

}

static int arith_cc(DisasContext *dc)

{

        if (dc->update_cc) {

                switch (dc->cc_op) {

                        case CC_OP_ADDC: return 1;

                        case CC_OP_ADD: return 1;

                        case CC_OP_SUB: return 1;

                        case CC_OP_DSTEP: return 1;

                        case CC_OP_LSL: return 1;

                        case CC_OP_LSR: return 1;

                        case CC_OP_ASR: return 1;

                        case CC_OP_CMP: return 1;

                        case CC_OP_NEG: return 1;

                        case CC_OP_OR: return 1;

                        case CC_OP_XOR: return 1;

                        case CC_OP_MULU: return 1;

                        case CC_OP_MULS: return 1;

                        default:

                                return 0;

                }

        }

        return 0;

}

static void gen_tst_cc (DisasContext *dc, int cond)

{

        int arith_opt, move_opt;

        /* TODO: optimize more condition codes.  */

        /*

         * If the flags are live, we've gotta look into the bits of CCS.

         * Otherwise, if we just did an arithmetic operation we try to

         * evaluate the condition code faster.

         *

         * When this function is done, T0 should be non-zero if the condition

         * code is true.

         */

        arith_opt = arith_cc(dc) && !dc->flags_uptodate;

        move_opt = (dc->cc_op == CC_OP_MOVE) && dc->flags_uptodate;

        switch (cond) {

                case CC_EQ:

                        if (arith_opt || move_opt) {

                                /* If cc_result is zero, T0 should be 

                                   non-zero otherwise T0 should be zero.  */

                                int l1;

                                l1 = gen_new_label();

                                tcg_gen_movi_tl(cpu_T[0], 0);

                                tcg_gen_brcondi_tl(TCG_COND_NE, cc_result, 

                                                   0, l1);

                                tcg_gen_movi_tl(cpu_T[0], 1);

                                gen_set_label(l1);

                        }

                        else {

                                cris_evaluate_flags(dc);

                                tcg_gen_andi_tl(cpu_T[0], 

                                                cpu_PR[PR_CCS], Z_FLAG);

                        }

                        break;

                case CC_NE:

                        if (arith_opt || move_opt)

                                tcg_gen_mov_tl(cpu_T[0], cc_result);

                        else {

                                cris_evaluate_flags(dc);

                                tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],

                                                Z_FLAG);

                                tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);

                        }

                        break;

                case CC_CS:

                        cris_evaluate_flags(dc);

                        tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);

                        break;

                case CC_CC:

                        cris_evaluate_flags(dc);

                        tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);

                        tcg_gen_andi_tl(cpu_T[0], cpu_T[0], C_FLAG);

                        break;

                case CC_VS:

                        cris_evaluate_flags(dc);

                        tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], V_FLAG);

                        break;

                case CC_VC:

                        cris_evaluate_flags(dc);

                        tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],

                                        V_FLAG);

                        tcg_gen_andi_tl(cpu_T[0], cpu_T[0], V_FLAG);

                        break;

                case CC_PL:

                        if (arith_opt || move_opt) {

                                int bits = 31;

                                if (dc->cc_size == 1)

                                        bits = 7;

                                else if (dc->cc_size == 2)

                                        bits = 15;        

                                tcg_gen_shri_tl(cpu_T[0], cc_result, bits);

                                tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);

                        } else {

                                cris_evaluate_flags(dc);

                                tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],

                                                N_FLAG);

                                tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);

                        }

                        break;

                case CC_MI:

                        if (arith_opt || move_opt) {

                                int bits = 31;

                                if (dc->cc_size == 1)

                                        bits = 7;

                                else if (dc->cc_size == 2)

                                        bits = 15;        

                                tcg_gen_shri_tl(cpu_T[0], cc_result, 31);

                        }

                        else {

                                cris_evaluate_flags(dc);

                                tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],

                                                N_FLAG);

                        }

                        break;

                case CC_LS:

                        cris_evaluate_flags(dc);

                        tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],

                                        C_FLAG | Z_FLAG);

                        break;

                case CC_HI:

                        cris_evaluate_flags(dc);

                        {

                                TCGv tmp;

                                tmp = tcg_temp_new(TCG_TYPE_TL);

                                tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],

                                                C_FLAG | Z_FLAG);

                                /* Overlay the C flag on top of the Z.  */

                                tcg_gen_shli_tl(cpu_T[0], tmp, 2);

                                tcg_gen_and_tl(cpu_T[0], tmp, cpu_T[0]);

                                tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);

                                tcg_temp_free(tmp);

                        }

                        break;

                case CC_GE:

                        cris_evaluate_flags(dc);

                        /* Overlay the V flag on top of the N.  */

                        tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);

                        tcg_gen_xor_tl(cpu_T[0],

                                       cpu_PR[PR_CCS], cpu_T[0]);

                        tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);

                        tcg_gen_xori_tl(cpu_T[0], cpu_T[0], N_FLAG);

                        break;

                case CC_LT:

                        cris_evaluate_flags(dc);

                        /* Overlay the V flag on top of the N.  */

                        tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);

                        tcg_gen_xor_tl(cpu_T[0],

                                       cpu_PR[PR_CCS], cpu_T[0]);

                        tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);

                        break;

                case CC_GT:

                        cris_evaluate_flags(dc);

                        {

                                TCGv n, z;

                                n = tcg_temp_new(TCG_TYPE_TL);

                                z = tcg_temp_new(TCG_TYPE_TL);

                                /* To avoid a shift we overlay everything on

                                   the V flag.  */

                                tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);

                                tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);

                                /* invert Z.  */

                                tcg_gen_xori_tl(z, z, 2);

                                tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);

                                tcg_gen_xori_tl(n, n, 2);

                                tcg_gen_and_tl(cpu_T[0], z, n);

                                tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);

                                tcg_temp_free(n);

                                tcg_temp_free(z);

                        }

                        break;

                case CC_LE:

                        cris_evaluate_flags(dc);

                        {

                                TCGv n, z;

                                n = tcg_temp_new(TCG_TYPE_TL);

                                z = tcg_temp_new(TCG_TYPE_TL);

                                /* To avoid a shift we overlay everything on

                                   the V flag.  */

                                tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);

                                tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);

                                tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);

                                tcg_gen_or_tl(cpu_T[0], z, n);

                                tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);

                                tcg_temp_free(n);

                                tcg_temp_free(z);

                        }

                        break;

                case CC_P:

                        cris_evaluate_flags(dc);

                        tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], P_FLAG);

                        break;

                case CC_A:

                        tcg_gen_movi_tl(cpu_T[0], 1);

                        break;

                default:

                        BUG();

                        break;

        };

}

static void cris_store_direct_jmp(DisasContext *dc)

{

        /* Store the direct jmp state into the cpu-state.  */

        if (dc->jmp == JMP_DIRECT) {

                tcg_gen_movi_tl(env_btarget, dc->jmp_pc);

                tcg_gen_movi_tl(env_btaken, 1);

        }

}

static void cris_prepare_cc_branch (DisasContext *dc, 

                                    int offset, int cond)

{

        /* This helps us re-schedule the micro-code to insns in delay-slots

           before the actual jump.  */

        dc->delayed_branch = 2;

        dc->jmp_pc = dc->pc + offset;

        if (cond != CC_A)

        {

                dc->jmp = JMP_INDIRECT;

                gen_tst_cc (dc, cond);

                tcg_gen_mov_tl(env_btaken, cpu_T[0]);

                tcg_gen_movi_tl(env_btarget, dc->jmp_pc);

        } else {

                /* Allow chaining.  */

                dc->jmp = JMP_DIRECT;

        }

}

/* jumps, when the dest is in a live reg for example. Direct should be set

   when the dest addr is constant to allow tb chaining.  */

static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)

{

        /* This helps us re-schedule the micro-code to insns in delay-slots

           before the actual jump.  */

        dc->delayed_branch = 2;

        dc->jmp = type;

        if (type == JMP_INDIRECT)

                tcg_gen_movi_tl(env_btaken, 1);

}

void gen_load(DisasContext *dc, TCGv dst, TCGv addr, 

              unsigned int size, int sign)

{

        int mem_index = cpu_mmu_index(dc->env);

        /* If we get a fault on a delayslot we must keep the jmp state in

           the cpu-state to be able to re-execute the jmp.  */

        if (dc->delayed_branch == 1)

                cris_store_direct_jmp(dc);

        if (size == 1) {

                if (sign)

                        tcg_gen_qemu_ld8s(dst, addr, mem_index);

                else

                        tcg_gen_qemu_ld8u(dst, addr, mem_index);

        }

        else if (size == 2) {

                if (sign)

                        tcg_gen_qemu_ld16s(dst, addr, mem_index);

                else

                        tcg_gen_qemu_ld16u(dst, addr, mem_index);

        }

        else {

                tcg_gen_qemu_ld32u(dst, addr, mem_index);

        }

}

void gen_store (DisasContext *dc, TCGv addr, TCGv val,

                unsigned int size)

{

        int mem_index = cpu_mmu_index(dc->env);

        /* If we get a fault on a delayslot we must keep the jmp state in

           the cpu-state to be able to re-execute the jmp.  */

        if (dc->delayed_branch == 1)

                 cris_store_direct_jmp(dc);

        /* Conditional writes. We only support the kind were X and P are known

           at translation time.  */

        if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {

                dc->postinc = 0;

                cris_evaluate_flags(dc);

                tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);

                return;

        }

        /* Remember, operands are flipped. CRIS has reversed order.  */

        if (size == 1)

                tcg_gen_qemu_st8(val, addr, mem_index);

        else if (size == 2)

                tcg_gen_qemu_st16(val, addr, mem_index);

        else

                tcg_gen_qemu_st32(val, addr, mem_index);

        if (dc->flagx_known && dc->flags_x) {

                cris_evaluate_flags(dc);

                tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);

        }

}

static inline void t_gen_sext(TCGv d, TCGv s, int size)

{

        if (size == 1)

                tcg_gen_ext8s_i32(d, s);

        else if (size == 2)

                tcg_gen_ext16s_i32(d, s);

        else if(GET_TCGV(d) != GET_TCGV(s))

                tcg_gen_mov_tl(d, s);

}

static inline void t_gen_zext(TCGv d, TCGv s, int size)

{

        if (size == 1)

                tcg_gen_ext8u_i32(d, s);

        else if (size == 2)

                tcg_gen_ext16u_i32(d, s);

        else if (GET_TCGV(d) != GET_TCGV(s))

                tcg_gen_mov_tl(d, s);

}

#if DISAS_CRIS

static char memsize_char(int size)

{

        switch (size)

        {

                case 1: return 'b';  break;

                case 2: return 'w';  break;

                case 4: return 'd';  break;

                default:

                        return 'x';

                        break;

        }

}

#endif

static inline unsigned int memsize_z(DisasContext *dc)

{

        return dc->zsize + 1;

}

static inline unsigned int memsize_zz(DisasContext *dc)

{

        switch (dc->zzsize)

        {

                case 0: return 1;

                case 1: return 2;

                default:

                        return 4;

        }

}

static inline void do_postinc (DisasContext *dc, int size)

{

        if (dc->postinc)

                tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);

}

static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,

                            int size, int s_ext, TCGv dst)

{

        if (s_ext)

                t_gen_sext(dst, cpu_R[rs], size);

        else

                t_gen_zext(dst, cpu_R[rs], size);

}

/* Prepare T0 and T1 for a register alu operation.

   s_ext decides if the operand1 should be sign-extended or zero-extended when

   needed.  */

static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,

                          int size, int s_ext)

{

        dec_prep_move_r(dc, rs, rd, size, s_ext, cpu_T[1]);

        if (s_ext)

                t_gen_sext(cpu_T[0], cpu_R[rd], size);

        else

                t_gen_zext(cpu_T[0], cpu_R[rd], size);

}

static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,

                           TCGv dst)

{

        unsigned int rs, rd;

        uint32_t imm;