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root / target-ppc @ 7d08d856

Name Size
Makefile.objs 379 Bytes
STATUS 10.6 kB
cpu-models.c 64.1 kB
cpu-models.h 29.4 kB
cpu-qom.h 2.7 kB
cpu.h 87.3 kB
excp_helper.c 34.2 kB
fpu_helper.c 48.5 kB
helper.h 15.9 kB
helper_regs.h 3.4 kB
int_helper.c 52.8 kB
kvm.c 48.2 kB
kvm_ppc.c 1.1 kB
kvm_ppc.h 3.9 kB
machine.c 5.6 kB
mem_helper.c 8.1 kB
mfrom_table.c 3.3 kB
mfrom_table_gen.c 653 Bytes
misc_helper.c 3.5 kB
mmu-hash32.c 16 kB
mmu-hash32.h 3.2 kB
mmu-hash64.c 15.3 kB
mmu-hash64.h 4.5 kB
mmu_helper.c 84.6 kB
timebase_helper.c 4.3 kB
translate.c 364.2 kB
translate_init.c 293 kB
user_only_helper.c 1.4 kB

Latest revisions

# Date Author Comment
199f830d 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate lfiwax instruction

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
[agraf: fix tcg debug error]
Signed-off-by: Alexander Graf <>

05050ee8 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate load doubleword pair instructions

Needed for Power ISA version 2.05 compliance. The check for odd register
pairs is done using the invalid bits.

Signed-off-by: Aurelien Jarno <>
Signed-off-by: Alexander Graf <>

44bc0c4d 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate store doubleword pair instructions

Needed for Power ISA version 2.05 compliance. The check for odd register
pairs is done using the invalid bits.

Signed-off-by: Aurelien Jarno <>
Signed-off-by: Alexander Graf <>

7d08d856 04/27/2013 12:02 am Aurelien Jarno

target-ppc: add support for extended mtfsf/mtfsfi forms

Power ISA 2.05 adds support for extended mtfsf/mtfsfi form, with a new
W field to select the upper part of the FPCSR register.

For that the helper is changed to handle 64-bit input values and mask with...

414f5d14 04/27/2013 12:02 am Alexander Graf

PPC: Fix dcbz for linux-user on 970

The default with linux-user for dcbz on 970 is to emulate 32 byte clears.
However, redoing the dcbzl support we added a check to not honor the bit
in HID5 that sets this.

Remove the #ifdef check on linux user, so that we get 32 byte clears again....

bf45a2e6 04/27/2013 12:02 am Aurelien Jarno

target-ppc: optimize fabs, fnabs, fneg

fabs, fnabs and fneg are just flipping the bit sign of an FP register,
this can be implemented in TCG instead of using softfloat.

Signed-off-by: Aurelien Jarno <>
Signed-off-by: Alexander Graf <>

9c2627b0 04/27/2013 12:02 am Aurelien Jarno

target-ppc: add instruction flags for Book I 2.05

.. and enable it on POWER7 CPU.

Reviewed-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
Signed-off-by: Alexander Graf <>

fcfda20f 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate cmpb instruction

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
Signed-off-by: Alexander Graf <>

725bcec2 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate prtyw and prtyd instructions

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
[agraf: fix 32-bit host compile, simplify code]
Signed-off-by: Alexander Graf <>

f0332888 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate fcpsgn instruction

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
Signed-off-by: Alexander Graf <>

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