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1 | 0ecfa993 | bellard | /* NOTE: this header is included in op-i386.c where global register
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2 | 0ecfa993 | bellard | variable are used. Care must be used when including glibc headers.
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3 | 0ecfa993 | bellard | */
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4 | 367e86e8 | bellard | #ifndef CPU_I386_H
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5 | 367e86e8 | bellard | #define CPU_I386_H
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6 | 367e86e8 | bellard | |
7 | 0ecfa993 | bellard | #include <setjmp.h> |
8 | 0ecfa993 | bellard | |
9 | 367e86e8 | bellard | #define R_EAX 0 |
10 | 367e86e8 | bellard | #define R_ECX 1 |
11 | 367e86e8 | bellard | #define R_EDX 2 |
12 | 367e86e8 | bellard | #define R_EBX 3 |
13 | 367e86e8 | bellard | #define R_ESP 4 |
14 | 367e86e8 | bellard | #define R_EBP 5 |
15 | 367e86e8 | bellard | #define R_ESI 6 |
16 | 367e86e8 | bellard | #define R_EDI 7 |
17 | 367e86e8 | bellard | |
18 | 367e86e8 | bellard | #define R_AL 0 |
19 | 367e86e8 | bellard | #define R_CL 1 |
20 | 367e86e8 | bellard | #define R_DL 2 |
21 | 367e86e8 | bellard | #define R_BL 3 |
22 | 367e86e8 | bellard | #define R_AH 4 |
23 | 367e86e8 | bellard | #define R_CH 5 |
24 | 367e86e8 | bellard | #define R_DH 6 |
25 | 367e86e8 | bellard | #define R_BH 7 |
26 | 367e86e8 | bellard | |
27 | 367e86e8 | bellard | #define R_ES 0 |
28 | 367e86e8 | bellard | #define R_CS 1 |
29 | 367e86e8 | bellard | #define R_SS 2 |
30 | 367e86e8 | bellard | #define R_DS 3 |
31 | 367e86e8 | bellard | #define R_FS 4 |
32 | 367e86e8 | bellard | #define R_GS 5 |
33 | 367e86e8 | bellard | |
34 | 367e86e8 | bellard | #define CC_C 0x0001 |
35 | 367e86e8 | bellard | #define CC_P 0x0004 |
36 | 367e86e8 | bellard | #define CC_A 0x0010 |
37 | 367e86e8 | bellard | #define CC_Z 0x0040 |
38 | 367e86e8 | bellard | #define CC_S 0x0080 |
39 | 367e86e8 | bellard | #define CC_O 0x0800 |
40 | 367e86e8 | bellard | |
41 | 367e86e8 | bellard | #define TRAP_FLAG 0x0100 |
42 | 367e86e8 | bellard | #define INTERRUPT_FLAG 0x0200 |
43 | 367e86e8 | bellard | #define DIRECTION_FLAG 0x0400 |
44 | 367e86e8 | bellard | #define IOPL_FLAG_MASK 0x3000 |
45 | 367e86e8 | bellard | #define NESTED_FLAG 0x4000 |
46 | 367e86e8 | bellard | #define BYTE_FL 0x8000 /* Intel reserved! */ |
47 | 367e86e8 | bellard | #define RF_FLAG 0x10000 |
48 | 367e86e8 | bellard | #define VM_FLAG 0x20000 |
49 | 367e86e8 | bellard | /* AC 0x40000 */
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50 | 367e86e8 | bellard | |
51 | 0ecfa993 | bellard | #define EXCP00_DIVZ 1 |
52 | 0ecfa993 | bellard | #define EXCP01_SSTP 2 |
53 | 0ecfa993 | bellard | #define EXCP02_NMI 3 |
54 | 0ecfa993 | bellard | #define EXCP03_INT3 4 |
55 | 0ecfa993 | bellard | #define EXCP04_INTO 5 |
56 | 0ecfa993 | bellard | #define EXCP05_BOUND 6 |
57 | 0ecfa993 | bellard | #define EXCP06_ILLOP 7 |
58 | 0ecfa993 | bellard | #define EXCP07_PREX 8 |
59 | 0ecfa993 | bellard | #define EXCP08_DBLE 9 |
60 | 0ecfa993 | bellard | #define EXCP09_XERR 10 |
61 | 0ecfa993 | bellard | #define EXCP0A_TSS 11 |
62 | 0ecfa993 | bellard | #define EXCP0B_NOSEG 12 |
63 | 0ecfa993 | bellard | #define EXCP0C_STACK 13 |
64 | 0ecfa993 | bellard | #define EXCP0D_GPF 14 |
65 | 0ecfa993 | bellard | #define EXCP0E_PAGE 15 |
66 | 0ecfa993 | bellard | #define EXCP10_COPR 17 |
67 | 0ecfa993 | bellard | #define EXCP11_ALGN 18 |
68 | 0ecfa993 | bellard | #define EXCP12_MCHK 19 |
69 | 0ecfa993 | bellard | |
70 | 0ecfa993 | bellard | #define EXCP_SIGNAL 256 /* async signal */ |
71 | 0ecfa993 | bellard | |
72 | 367e86e8 | bellard | enum {
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73 | 367e86e8 | bellard | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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74 | 367e86e8 | bellard | CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
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75 | 367e86e8 | bellard | CC_OP_MUL, /* modify all flags, C, O = (CC_SRC != 0) */
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76 | 367e86e8 | bellard | |
77 | 367e86e8 | bellard | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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78 | 367e86e8 | bellard | CC_OP_ADDW, |
79 | 367e86e8 | bellard | CC_OP_ADDL, |
80 | 367e86e8 | bellard | |
81 | 4b74fe1f | bellard | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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82 | 4b74fe1f | bellard | CC_OP_ADCW, |
83 | 4b74fe1f | bellard | CC_OP_ADCL, |
84 | 4b74fe1f | bellard | |
85 | 367e86e8 | bellard | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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86 | 367e86e8 | bellard | CC_OP_SUBW, |
87 | 367e86e8 | bellard | CC_OP_SUBL, |
88 | 367e86e8 | bellard | |
89 | 4b74fe1f | bellard | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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90 | 4b74fe1f | bellard | CC_OP_SBBW, |
91 | 4b74fe1f | bellard | CC_OP_SBBL, |
92 | 4b74fe1f | bellard | |
93 | 367e86e8 | bellard | CC_OP_LOGICB, /* modify all flags, CC_DST = res */
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94 | 367e86e8 | bellard | CC_OP_LOGICW, |
95 | 367e86e8 | bellard | CC_OP_LOGICL, |
96 | 367e86e8 | bellard | |
97 | 4b74fe1f | bellard | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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98 | 367e86e8 | bellard | CC_OP_INCW, |
99 | 367e86e8 | bellard | CC_OP_INCL, |
100 | 367e86e8 | bellard | |
101 | 4b74fe1f | bellard | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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102 | 367e86e8 | bellard | CC_OP_DECW, |
103 | 367e86e8 | bellard | CC_OP_DECL, |
104 | 367e86e8 | bellard | |
105 | 367e86e8 | bellard | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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106 | 367e86e8 | bellard | CC_OP_SHLW, |
107 | 367e86e8 | bellard | CC_OP_SHLL, |
108 | 367e86e8 | bellard | |
109 | 4b74fe1f | bellard | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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110 | 4b74fe1f | bellard | CC_OP_SARW, |
111 | 4b74fe1f | bellard | CC_OP_SARL, |
112 | 4b74fe1f | bellard | |
113 | 367e86e8 | bellard | CC_OP_NB, |
114 | 367e86e8 | bellard | }; |
115 | 367e86e8 | bellard | |
116 | 927f621e | bellard | #ifdef __i386__
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117 | 77f8dd5a | bellard | //#define USE_X86LDOUBLE
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118 | 927f621e | bellard | #endif
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119 | 927f621e | bellard | |
120 | 927f621e | bellard | #ifdef USE_X86LDOUBLE
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121 | 927f621e | bellard | typedef long double CPU86_LDouble; |
122 | 927f621e | bellard | #else
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123 | 927f621e | bellard | typedef double CPU86_LDouble; |
124 | 927f621e | bellard | #endif
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125 | 927f621e | bellard | |
126 | ba1c6e37 | bellard | typedef struct CPUX86State { |
127 | 367e86e8 | bellard | /* standard registers */
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128 | 367e86e8 | bellard | uint32_t regs[8];
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129 | 367e86e8 | bellard | uint32_t pc; /* cs_case + eip value */
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130 | 367e86e8 | bellard | uint32_t eflags; |
131 | 0ecfa993 | bellard | |
132 | 0ecfa993 | bellard | /* emulator internal eflags handling */
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133 | 367e86e8 | bellard | uint32_t cc_src; |
134 | 367e86e8 | bellard | uint32_t cc_dst; |
135 | 367e86e8 | bellard | uint32_t cc_op; |
136 | 367e86e8 | bellard | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
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137 | 0ecfa993 | bellard | |
138 | 367e86e8 | bellard | /* segments */
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139 | 367e86e8 | bellard | uint8_t *segs_base[6];
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140 | 367e86e8 | bellard | |
141 | 927f621e | bellard | /* FPU state */
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142 | 927f621e | bellard | unsigned int fpstt; /* top of stack index */ |
143 | 927f621e | bellard | unsigned int fpus; |
144 | 927f621e | bellard | unsigned int fpuc; |
145 | 0ecfa993 | bellard | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
146 | 0ecfa993 | bellard | CPU86_LDouble fpregs[8];
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147 | 0ecfa993 | bellard | |
148 | 0ecfa993 | bellard | /* segments */
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149 | 0ecfa993 | bellard | uint32_t segs[6];
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150 | 927f621e | bellard | |
151 | 367e86e8 | bellard | /* emulator internal variables */
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152 | 927f621e | bellard | CPU86_LDouble ft0; |
153 | d57c4e01 | bellard | |
154 | 0ecfa993 | bellard | /* exception handling */
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155 | 0ecfa993 | bellard | jmp_buf jmp_env; |
156 | 0ecfa993 | bellard | int exception_index;
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157 | ba1c6e37 | bellard | } CPUX86State; |
158 | 367e86e8 | bellard | |
159 | 367e86e8 | bellard | static inline int ldub(void *ptr) |
160 | 367e86e8 | bellard | { |
161 | 367e86e8 | bellard | return *(uint8_t *)ptr;
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162 | 367e86e8 | bellard | } |
163 | 367e86e8 | bellard | |
164 | 367e86e8 | bellard | static inline int ldsb(void *ptr) |
165 | 367e86e8 | bellard | { |
166 | 367e86e8 | bellard | return *(int8_t *)ptr;
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167 | 367e86e8 | bellard | } |
168 | 367e86e8 | bellard | |
169 | 367e86e8 | bellard | static inline int lduw(void *ptr) |
170 | 367e86e8 | bellard | { |
171 | 367e86e8 | bellard | return *(uint16_t *)ptr;
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172 | 367e86e8 | bellard | } |
173 | 367e86e8 | bellard | |
174 | 367e86e8 | bellard | static inline int ldsw(void *ptr) |
175 | 367e86e8 | bellard | { |
176 | 367e86e8 | bellard | return *(int16_t *)ptr;
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177 | 367e86e8 | bellard | } |
178 | 367e86e8 | bellard | |
179 | 367e86e8 | bellard | static inline int ldl(void *ptr) |
180 | 367e86e8 | bellard | { |
181 | 367e86e8 | bellard | return *(uint32_t *)ptr;
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182 | 367e86e8 | bellard | } |
183 | 367e86e8 | bellard | |
184 | 927f621e | bellard | static inline uint64_t ldq(void *ptr) |
185 | 927f621e | bellard | { |
186 | 927f621e | bellard | return *(uint64_t *)ptr;
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187 | 927f621e | bellard | } |
188 | 367e86e8 | bellard | |
189 | 367e86e8 | bellard | static inline void stb(void *ptr, int v) |
190 | 367e86e8 | bellard | { |
191 | 367e86e8 | bellard | *(uint8_t *)ptr = v; |
192 | 367e86e8 | bellard | } |
193 | 367e86e8 | bellard | |
194 | 367e86e8 | bellard | static inline void stw(void *ptr, int v) |
195 | 367e86e8 | bellard | { |
196 | 367e86e8 | bellard | *(uint16_t *)ptr = v; |
197 | 367e86e8 | bellard | } |
198 | 367e86e8 | bellard | |
199 | 367e86e8 | bellard | static inline void stl(void *ptr, int v) |
200 | 367e86e8 | bellard | { |
201 | 367e86e8 | bellard | *(uint32_t *)ptr = v; |
202 | 367e86e8 | bellard | } |
203 | 367e86e8 | bellard | |
204 | 77f8dd5a | bellard | static inline void stq(void *ptr, uint64_t v) |
205 | 927f621e | bellard | { |
206 | 927f621e | bellard | *(uint64_t *)ptr = v; |
207 | 927f621e | bellard | } |
208 | 927f621e | bellard | |
209 | 927f621e | bellard | /* float access */
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210 | 927f621e | bellard | |
211 | 927f621e | bellard | static inline float ldfl(void *ptr) |
212 | 927f621e | bellard | { |
213 | 927f621e | bellard | return *(float *)ptr; |
214 | 927f621e | bellard | } |
215 | 927f621e | bellard | |
216 | 927f621e | bellard | static inline double ldfq(void *ptr) |
217 | 927f621e | bellard | { |
218 | 927f621e | bellard | return *(double *)ptr; |
219 | 927f621e | bellard | } |
220 | 927f621e | bellard | |
221 | 927f621e | bellard | static inline void stfl(void *ptr, float v) |
222 | 927f621e | bellard | { |
223 | 927f621e | bellard | *(float *)ptr = v;
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224 | 927f621e | bellard | } |
225 | 927f621e | bellard | |
226 | 927f621e | bellard | static inline void stfq(void *ptr, double v) |
227 | 927f621e | bellard | { |
228 | 927f621e | bellard | *(double *)ptr = v;
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229 | 927f621e | bellard | } |
230 | 927f621e | bellard | |
231 | 927f621e | bellard | #ifndef IN_OP_I386
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232 | ba1c6e37 | bellard | void cpu_x86_outb(int addr, int val); |
233 | ba1c6e37 | bellard | void cpu_x86_outw(int addr, int val); |
234 | ba1c6e37 | bellard | void cpu_x86_outl(int addr, int val); |
235 | ba1c6e37 | bellard | int cpu_x86_inb(int addr); |
236 | ba1c6e37 | bellard | int cpu_x86_inw(int addr); |
237 | ba1c6e37 | bellard | int cpu_x86_inl(int addr); |
238 | 927f621e | bellard | #endif
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239 | 367e86e8 | bellard | |
240 | ba1c6e37 | bellard | CPUX86State *cpu_x86_init(void);
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241 | ba1c6e37 | bellard | int cpu_x86_exec(CPUX86State *s);
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242 | ba1c6e37 | bellard | void cpu_x86_close(CPUX86State *s);
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243 | ba1c6e37 | bellard | |
244 | ba1c6e37 | bellard | /* internal functions */
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245 | 1017ebe9 | bellard | int cpu_x86_gen_code(uint8_t *gen_code_buf, int max_code_size, |
246 | 1017ebe9 | bellard | int *gen_code_size_ptr, uint8_t *pc_start);
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247 | 7d13299d | bellard | void cpu_x86_tblocks_init(void); |
248 | ba1c6e37 | bellard | |
249 | 367e86e8 | bellard | #endif /* CPU_I386_H */ |