Revision 7d85892b target-sparc/op_helper.c

b/target-sparc/op_helper.c
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            break;
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        }
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        break;
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    case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
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    case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
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    case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
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        switch(size) {
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        case 1:
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            ret = ldub_phys((target_phys_addr_t)T0
......
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    case 0x39: /* data cache diagnostic register */
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        ret = 0;
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        break;
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    case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
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    default:
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        do_unassigned_access(T0, 0, 0, asi);
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        ret = 0;

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