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/*
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* QEMU Sun4m & Sun4d System Emulator
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "qemu-timer.h" |
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#include "sun4m.h" |
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#include "nvram.h" |
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#include "sparc32_dma.h" |
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#include "fdc.h" |
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#include "sysemu.h" |
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#include "net.h" |
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#include "boards.h" |
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#include "firmware_abi.h" |
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//#define DEBUG_IRQ
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/*
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* Sun4m architecture was used in the following machines:
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*
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* SPARCserver 6xxMP/xx
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* SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10)
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* SPARCstation LX/ZX (4/30)
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* SPARCstation Voyager
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* SPARCstation 10/xx, SPARCserver 10/xx
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* SPARCstation 5, SPARCserver 5
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* SPARCstation 20/xx, SPARCserver 20
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* SPARCstation 4
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*
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* Sun4d architecture was used in the following machines:
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*
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* SPARCcenter 2000
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* SPARCserver 1000
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*
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* See for example: http://www.sunhelp.org/faq/sunref1.html
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*/
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#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, args...) \
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do { printf("CPUIRQ: " fmt , ##args); } while (0) |
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#else
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#define DPRINTF(fmt, args...)
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#endif
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#define KERNEL_LOAD_ADDR 0x00004000 |
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#define CMDLINE_ADDR 0x007ff000 |
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#define INITRD_LOAD_ADDR 0x00800000 |
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#define PROM_SIZE_MAX (512 * 1024) |
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#define PROM_VADDR 0xffd00000 |
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#define PROM_FILENAME "openbios-sparc32" |
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#define MAX_CPUS 16 |
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#define MAX_PILS 16 |
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struct hwdef {
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target_phys_addr_t iommu_base, slavio_base; |
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target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
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target_phys_addr_t serial_base, fd_base; |
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target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
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target_phys_addr_t tcx_base, cs_base, power_base; |
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target_phys_addr_t ecc_base; |
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uint32_t ecc_version; |
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long vram_size, nvram_size;
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// IRQ numbers are not PIL ones, but master interrupt controller register
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// bit numbers
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int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
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int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
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int machine_id; // For NVRAM |
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uint32_t iommu_version; |
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uint32_t intbit_to_level[32];
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uint64_t max_mem; |
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const char * const default_cpu_model; |
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}; |
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#define MAX_IOUNITS 5 |
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struct sun4d_hwdef {
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target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; |
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target_phys_addr_t counter_base, nvram_base, ms_kb_base; |
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target_phys_addr_t serial_base; |
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target_phys_addr_t espdma_base, esp_base; |
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target_phys_addr_t ledma_base, le_base; |
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target_phys_addr_t tcx_base; |
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target_phys_addr_t sbi_base; |
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unsigned long vram_size, nvram_size; |
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// IRQ numbers are not PIL ones, but SBI register bit numbers
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int esp_irq, le_irq, clock_irq, clock1_irq;
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int ser_irq, ms_kb_irq, me_irq;
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int machine_id; // For NVRAM |
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uint32_t iounit_version; |
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uint64_t max_mem; |
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const char * const default_cpu_model; |
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}; |
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/* TSC handling */
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uint64_t cpu_get_tsc() |
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{ |
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return qemu_get_clock(vm_clock);
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} |
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int DMA_get_channel_mode (int nchan) |
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{ |
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return 0; |
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} |
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int DMA_read_memory (int nchan, void *buf, int pos, int size) |
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{ |
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return 0; |
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} |
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int DMA_write_memory (int nchan, void *buf, int pos, int size) |
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{ |
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return 0; |
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} |
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void DMA_hold_DREQ (int nchan) {} |
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void DMA_release_DREQ (int nchan) {} |
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void DMA_schedule(int nchan) {} |
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void DMA_run (void) {} |
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void DMA_init (int high_page_enable) {} |
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void DMA_register_channel (int nchan, |
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DMA_transfer_handler transfer_handler, |
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void *opaque)
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{ |
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} |
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extern int nographic; |
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static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
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const char *boot_devices, uint32_t RAM_size, |
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uint32_t kernel_size, |
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int width, int height, int depth, |
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int machine_id, const char *arch) |
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{ |
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unsigned int i; |
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uint32_t start, end; |
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uint8_t image[0x1ff0];
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ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ |
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struct sparc_arch_cfg *sparc_header;
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struct OpenBIOS_nvpart_v1 *part_header;
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memset(image, '\0', sizeof(image)); |
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// Try to match PPC NVRAM
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strcpy(header->struct_ident, "QEMU_BIOS");
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header->struct_version = cpu_to_be32(3); /* structure v3 */ |
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header->nvram_size = cpu_to_be16(0x2000);
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header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
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header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg)); |
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strcpy(header->arch, arch); |
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header->nb_cpus = smp_cpus & 0xff;
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header->RAM0_base = 0;
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header->RAM0_size = cpu_to_be64((uint64_t)RAM_size); |
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strcpy(header->boot_devices, boot_devices); |
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header->nboot_devices = strlen(boot_devices) & 0xff;
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header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR); |
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header->kernel_size = cpu_to_be64((uint64_t)kernel_size); |
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if (cmdline) {
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strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
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header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR); |
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header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline)); |
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} |
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// XXX add initrd_image, initrd_size
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header->width = cpu_to_be16(width); |
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header->height = cpu_to_be16(height); |
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header->depth = cpu_to_be16(depth); |
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if (nographic)
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header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS); |
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header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
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// Architecture specific header
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start = sizeof(ohwcfg_v3_t);
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sparc_header = (struct sparc_arch_cfg *)&image[start];
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sparc_header->valid = 0;
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start += sizeof(struct sparc_arch_cfg); |
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// OpenBIOS nvram variables
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// Variable partition
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_SYSTEM; |
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strcpy(part_header->name, "system");
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end = start + sizeof(struct OpenBIOS_nvpart_v1); |
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for (i = 0; i < nb_prom_envs; i++) |
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end = OpenBIOS_set_var(image, end, prom_envs[i]); |
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// End marker
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image[end++] = '\0';
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end = start + ((end - start + 15) & ~15); |
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OpenBIOS_finish_partition(part_header, end - start); |
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// free partition
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start = end; |
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_FREE; |
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strcpy(part_header->name, "free");
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end = 0x1fd0;
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OpenBIOS_finish_partition(part_header, end - start); |
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Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id); |
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for (i = 0; i < sizeof(image); i++) |
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m48t59_write(nvram, i, image[i]); |
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} |
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static void *slavio_intctl; |
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void pic_info()
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{ |
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if (slavio_intctl)
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slavio_pic_info(slavio_intctl); |
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} |
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void irq_info()
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{ |
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if (slavio_intctl)
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slavio_irq_info(slavio_intctl); |
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} |
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void cpu_check_irqs(CPUState *env)
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{ |
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if (env->pil_in && (env->interrupt_index == 0 || |
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(env->interrupt_index & ~15) == TT_EXTINT)) {
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unsigned int i; |
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for (i = 15; i > 0; i--) { |
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if (env->pil_in & (1 << i)) { |
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int old_interrupt = env->interrupt_index;
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env->interrupt_index = TT_EXTINT | i; |
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if (old_interrupt != env->interrupt_index)
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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break;
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} |
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} |
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} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
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env->interrupt_index = 0;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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} |
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static void cpu_set_irq(void *opaque, int irq, int level) |
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{ |
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CPUState *env = opaque; |
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if (level) {
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DPRINTF("Raise CPU IRQ %d\n", irq);
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env->halted = 0;
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env->pil_in |= 1 << irq;
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cpu_check_irqs(env); |
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} else {
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DPRINTF("Lower CPU IRQ %d\n", irq);
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env->pil_in &= ~(1 << irq);
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cpu_check_irqs(env); |
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} |
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} |
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static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
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{ |
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} |
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static void *slavio_misc; |
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void qemu_system_powerdown(void) |
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{ |
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slavio_set_power_fail(slavio_misc, 1);
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} |
289 |
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static void main_cpu_reset(void *opaque) |
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{ |
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CPUState *env = opaque; |
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cpu_reset(env); |
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env->halted = 0;
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} |
297 |
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static void secondary_cpu_reset(void *opaque) |
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{ |
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CPUState *env = opaque; |
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cpu_reset(env); |
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env->halted = 1;
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} |
305 |
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static unsigned long sun4m_load_kernel(const char *kernel_filename, |
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const char *kernel_cmdline, |
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const char *initrd_filename) |
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{ |
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int linux_boot;
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unsigned int i; |
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long initrd_size, kernel_size;
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linux_boot = (kernel_filename != NULL);
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kernel_size = 0;
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if (linux_boot) {
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kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, |
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NULL);
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if (kernel_size < 0) |
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kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
322 |
if (kernel_size < 0) |
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kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
324 |
if (kernel_size < 0) { |
325 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename); |
327 |
exit(1);
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328 |
} |
329 |
|
330 |
/* load initrd */
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initrd_size = 0;
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if (initrd_filename) {
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initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); |
334 |
if (initrd_size < 0) { |
335 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename); |
337 |
exit(1);
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} |
339 |
} |
340 |
if (initrd_size > 0) { |
341 |
for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
342 |
if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
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== 0x48647253) { // HdrS |
344 |
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
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stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
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346 |
break;
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} |
348 |
} |
349 |
} |
350 |
} |
351 |
return kernel_size;
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} |
353 |
|
354 |
static void sun4m_hw_init(const struct hwdef *hwdef, int RAM_size, |
355 |
const char *boot_device, |
356 |
DisplayState *ds, const char *kernel_filename, |
357 |
const char *kernel_cmdline, |
358 |
const char *initrd_filename, const char *cpu_model) |
359 |
|
360 |
{ |
361 |
CPUState *env, *envs[MAX_CPUS]; |
362 |
unsigned int i; |
363 |
void *iommu, *espdma, *ledma, *main_esp, *nvram;
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364 |
qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq, |
365 |
*espdma_irq, *ledma_irq; |
366 |
qemu_irq *esp_reset, *le_reset; |
367 |
unsigned long prom_offset, kernel_size; |
368 |
int ret;
|
369 |
char buf[1024]; |
370 |
BlockDriverState *fd[MAX_FD]; |
371 |
int index;
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372 |
|
373 |
/* init CPUs */
|
374 |
if (!cpu_model)
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375 |
cpu_model = hwdef->default_cpu_model; |
376 |
|
377 |
for(i = 0; i < smp_cpus; i++) { |
378 |
env = cpu_init(cpu_model); |
379 |
if (!env) {
|
380 |
fprintf(stderr, "Unable to find Sparc CPU definition\n");
|
381 |
exit(1);
|
382 |
} |
383 |
cpu_sparc_set_id(env, i); |
384 |
envs[i] = env; |
385 |
if (i == 0) { |
386 |
qemu_register_reset(main_cpu_reset, env); |
387 |
} else {
|
388 |
qemu_register_reset(secondary_cpu_reset, env); |
389 |
env->halted = 1;
|
390 |
} |
391 |
register_savevm("cpu", i, 3, cpu_save, cpu_load, env); |
392 |
cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
393 |
env->prom_addr = hwdef->slavio_base; |
394 |
} |
395 |
|
396 |
for (i = smp_cpus; i < MAX_CPUS; i++)
|
397 |
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
398 |
|
399 |
|
400 |
/* allocate RAM */
|
401 |
if ((uint64_t)RAM_size > hwdef->max_mem) {
|
402 |
fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
|
403 |
(unsigned int)RAM_size / (1024 * 1024), |
404 |
(unsigned int)(hwdef->max_mem / (1024 * 1024))); |
405 |
exit(1);
|
406 |
} |
407 |
cpu_register_physical_memory(0, RAM_size, 0); |
408 |
|
409 |
/* load boot prom */
|
410 |
prom_offset = RAM_size + hwdef->vram_size; |
411 |
cpu_register_physical_memory(hwdef->slavio_base, |
412 |
(PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
413 |
TARGET_PAGE_MASK, |
414 |
prom_offset | IO_MEM_ROM); |
415 |
|
416 |
if (bios_name == NULL) |
417 |
bios_name = PROM_FILENAME; |
418 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
419 |
ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
420 |
if (ret < 0 || ret > PROM_SIZE_MAX) |
421 |
ret = load_image(buf, phys_ram_base + prom_offset); |
422 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
423 |
fprintf(stderr, "qemu: could not load prom '%s'\n",
|
424 |
buf); |
425 |
exit(1);
|
426 |
} |
427 |
prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
|
428 |
|
429 |
/* set up devices */
|
430 |
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version); |
431 |
slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
432 |
hwdef->intctl_base + 0x10000ULL,
|
433 |
&hwdef->intbit_to_level[0],
|
434 |
&slavio_irq, &slavio_cpu_irq, |
435 |
cpu_irqs, |
436 |
hwdef->clock_irq); |
437 |
|
438 |
if (hwdef->idreg_base != (target_phys_addr_t)-1) { |
439 |
stl_raw(phys_ram_base + prom_offset, 0xfe810103);
|
440 |
|
441 |
cpu_register_physical_memory(hwdef->idreg_base, sizeof(uint32_t),
|
442 |
prom_offset | IO_MEM_ROM); |
443 |
} |
444 |
|
445 |
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], |
446 |
iommu, &espdma_irq, &esp_reset); |
447 |
|
448 |
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
449 |
slavio_irq[hwdef->le_irq], iommu, &ledma_irq, |
450 |
&le_reset); |
451 |
|
452 |
if (graphic_depth != 8 && graphic_depth != 24) { |
453 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
454 |
exit (1);
|
455 |
} |
456 |
tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
457 |
hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
458 |
|
459 |
if (nd_table[0].model == NULL |
460 |
|| strcmp(nd_table[0].model, "lance") == 0) { |
461 |
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
462 |
} else if (strcmp(nd_table[0].model, "?") == 0) { |
463 |
fprintf(stderr, "qemu: Supported NICs: lance\n");
|
464 |
exit (1);
|
465 |
} else {
|
466 |
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
467 |
exit (1);
|
468 |
} |
469 |
|
470 |
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
471 |
hwdef->nvram_size, 8);
|
472 |
|
473 |
slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq], |
474 |
slavio_cpu_irq, smp_cpus); |
475 |
|
476 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], |
477 |
nographic); |
478 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
479 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
480 |
slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], |
481 |
serial_hds[1], serial_hds[0]); |
482 |
|
483 |
if (hwdef->fd_base != (target_phys_addr_t)-1) { |
484 |
/* there is zero or one floppy drive */
|
485 |
fd[1] = fd[0] = NULL; |
486 |
index = drive_get_index(IF_FLOPPY, 0, 0); |
487 |
if (index != -1) |
488 |
fd[0] = drives_table[index].bdrv;
|
489 |
|
490 |
sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd); |
491 |
} |
492 |
|
493 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
494 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
495 |
exit(1);
|
496 |
} |
497 |
|
498 |
main_esp = esp_init(hwdef->esp_base, espdma, *espdma_irq, |
499 |
esp_reset); |
500 |
|
501 |
for (i = 0; i < ESP_MAX_DEVS; i++) { |
502 |
index = drive_get_index(IF_SCSI, 0, i);
|
503 |
if (index == -1) |
504 |
continue;
|
505 |
esp_scsi_attach(main_esp, drives_table[index].bdrv, i); |
506 |
} |
507 |
|
508 |
slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->power_base, |
509 |
slavio_irq[hwdef->me_irq]); |
510 |
if (hwdef->cs_base != (target_phys_addr_t)-1) |
511 |
cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl); |
512 |
|
513 |
kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline, |
514 |
initrd_filename); |
515 |
|
516 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
517 |
boot_device, RAM_size, kernel_size, graphic_width, |
518 |
graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
|
519 |
|
520 |
if (hwdef->ecc_base != (target_phys_addr_t)-1) |
521 |
ecc_init(hwdef->ecc_base, hwdef->ecc_version); |
522 |
} |
523 |
|
524 |
static const struct hwdef hwdefs[] = { |
525 |
/* SS-5 */
|
526 |
{ |
527 |
.iommu_base = 0x10000000,
|
528 |
.tcx_base = 0x50000000,
|
529 |
.cs_base = 0x6c000000,
|
530 |
.slavio_base = 0x70000000,
|
531 |
.ms_kb_base = 0x71000000,
|
532 |
.serial_base = 0x71100000,
|
533 |
.nvram_base = 0x71200000,
|
534 |
.fd_base = 0x71400000,
|
535 |
.counter_base = 0x71d00000,
|
536 |
.intctl_base = 0x71e00000,
|
537 |
.idreg_base = 0x78000000,
|
538 |
.dma_base = 0x78400000,
|
539 |
.esp_base = 0x78800000,
|
540 |
.le_base = 0x78c00000,
|
541 |
.power_base = 0x7a000000,
|
542 |
.ecc_base = -1,
|
543 |
.vram_size = 0x00100000,
|
544 |
.nvram_size = 0x2000,
|
545 |
.esp_irq = 18,
|
546 |
.le_irq = 16,
|
547 |
.clock_irq = 7,
|
548 |
.clock1_irq = 19,
|
549 |
.ms_kb_irq = 14,
|
550 |
.ser_irq = 15,
|
551 |
.fd_irq = 22,
|
552 |
.me_irq = 30,
|
553 |
.cs_irq = 5,
|
554 |
.machine_id = 0x80,
|
555 |
.iommu_version = 0x04000000,
|
556 |
.intbit_to_level = { |
557 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
558 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
559 |
}, |
560 |
.max_mem = 0x10000000,
|
561 |
.default_cpu_model = "Fujitsu MB86904",
|
562 |
}, |
563 |
/* SS-10 */
|
564 |
{ |
565 |
.iommu_base = 0xfe0000000ULL,
|
566 |
.tcx_base = 0xe20000000ULL,
|
567 |
.cs_base = -1,
|
568 |
.slavio_base = 0xff0000000ULL,
|
569 |
.ms_kb_base = 0xff1000000ULL,
|
570 |
.serial_base = 0xff1100000ULL,
|
571 |
.nvram_base = 0xff1200000ULL,
|
572 |
.fd_base = 0xff1700000ULL,
|
573 |
.counter_base = 0xff1300000ULL,
|
574 |
.intctl_base = 0xff1400000ULL,
|
575 |
.idreg_base = 0xef0000000ULL,
|
576 |
.dma_base = 0xef0400000ULL,
|
577 |
.esp_base = 0xef0800000ULL,
|
578 |
.le_base = 0xef0c00000ULL,
|
579 |
.power_base = 0xefa000000ULL,
|
580 |
.ecc_base = 0xf00000000ULL,
|
581 |
.ecc_version = 0x10000000, // version 0, implementation 1 |
582 |
.vram_size = 0x00100000,
|
583 |
.nvram_size = 0x2000,
|
584 |
.esp_irq = 18,
|
585 |
.le_irq = 16,
|
586 |
.clock_irq = 7,
|
587 |
.clock1_irq = 19,
|
588 |
.ms_kb_irq = 14,
|
589 |
.ser_irq = 15,
|
590 |
.fd_irq = 22,
|
591 |
.me_irq = 30,
|
592 |
.cs_irq = -1,
|
593 |
.machine_id = 0x72,
|
594 |
.iommu_version = 0x03000000,
|
595 |
.intbit_to_level = { |
596 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
597 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
598 |
}, |
599 |
.max_mem = 0xffffffff, // XXX actually first 62GB ok |
600 |
.default_cpu_model = "TI SuperSparc II",
|
601 |
}, |
602 |
/* SS-600MP */
|
603 |
{ |
604 |
.iommu_base = 0xfe0000000ULL,
|
605 |
.tcx_base = 0xe20000000ULL,
|
606 |
.cs_base = -1,
|
607 |
.slavio_base = 0xff0000000ULL,
|
608 |
.ms_kb_base = 0xff1000000ULL,
|
609 |
.serial_base = 0xff1100000ULL,
|
610 |
.nvram_base = 0xff1200000ULL,
|
611 |
.fd_base = -1,
|
612 |
.counter_base = 0xff1300000ULL,
|
613 |
.intctl_base = 0xff1400000ULL,
|
614 |
.idreg_base = -1,
|
615 |
.dma_base = 0xef0081000ULL,
|
616 |
.esp_base = 0xef0080000ULL,
|
617 |
.le_base = 0xef0060000ULL,
|
618 |
.power_base = 0xefa000000ULL,
|
619 |
.ecc_base = 0xf00000000ULL,
|
620 |
.ecc_version = 0x00000000, // version 0, implementation 0 |
621 |
.vram_size = 0x00100000,
|
622 |
.nvram_size = 0x2000,
|
623 |
.esp_irq = 18,
|
624 |
.le_irq = 16,
|
625 |
.clock_irq = 7,
|
626 |
.clock1_irq = 19,
|
627 |
.ms_kb_irq = 14,
|
628 |
.ser_irq = 15,
|
629 |
.fd_irq = 22,
|
630 |
.me_irq = 30,
|
631 |
.cs_irq = -1,
|
632 |
.machine_id = 0x71,
|
633 |
.iommu_version = 0x01000000,
|
634 |
.intbit_to_level = { |
635 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
636 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
637 |
}, |
638 |
.max_mem = 0xffffffff, // XXX actually first 62GB ok |
639 |
.default_cpu_model = "TI SuperSparc II",
|
640 |
}, |
641 |
/* SS-20 */
|
642 |
{ |
643 |
.iommu_base = 0xfe0000000ULL,
|
644 |
.tcx_base = 0xe20000000ULL,
|
645 |
.cs_base = -1,
|
646 |
.slavio_base = 0xff0000000ULL,
|
647 |
.ms_kb_base = 0xff1000000ULL,
|
648 |
.serial_base = 0xff1100000ULL,
|
649 |
.nvram_base = 0xff1200000ULL,
|
650 |
.fd_base = 0xff1700000ULL,
|
651 |
.counter_base = 0xff1300000ULL,
|
652 |
.intctl_base = 0xff1400000ULL,
|
653 |
.idreg_base = 0xef0000000ULL,
|
654 |
.dma_base = 0xef0400000ULL,
|
655 |
.esp_base = 0xef0800000ULL,
|
656 |
.le_base = 0xef0c00000ULL,
|
657 |
.power_base = 0xefa000000ULL,
|
658 |
.ecc_base = 0xf00000000ULL,
|
659 |
.ecc_version = 0x20000000, // version 0, implementation 2 |
660 |
.vram_size = 0x00100000,
|
661 |
.nvram_size = 0x2000,
|
662 |
.esp_irq = 18,
|
663 |
.le_irq = 16,
|
664 |
.clock_irq = 7,
|
665 |
.clock1_irq = 19,
|
666 |
.ms_kb_irq = 14,
|
667 |
.ser_irq = 15,
|
668 |
.fd_irq = 22,
|
669 |
.me_irq = 30,
|
670 |
.cs_irq = -1,
|
671 |
.machine_id = 0x72,
|
672 |
.iommu_version = 0x13000000,
|
673 |
.intbit_to_level = { |
674 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
675 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
676 |
}, |
677 |
.max_mem = 0xffffffff, // XXX actually first 62GB ok |
678 |
.default_cpu_model = "TI SuperSparc II",
|
679 |
}, |
680 |
}; |
681 |
|
682 |
/* SPARCstation 5 hardware initialisation */
|
683 |
static void ss5_init(int RAM_size, int vga_ram_size, |
684 |
const char *boot_device, DisplayState *ds, |
685 |
const char *kernel_filename, const char *kernel_cmdline, |
686 |
const char *initrd_filename, const char *cpu_model) |
687 |
{ |
688 |
sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
|
689 |
kernel_cmdline, initrd_filename, cpu_model); |
690 |
} |
691 |
|
692 |
/* SPARCstation 10 hardware initialisation */
|
693 |
static void ss10_init(int RAM_size, int vga_ram_size, |
694 |
const char *boot_device, DisplayState *ds, |
695 |
const char *kernel_filename, const char *kernel_cmdline, |
696 |
const char *initrd_filename, const char *cpu_model) |
697 |
{ |
698 |
sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
|
699 |
kernel_cmdline, initrd_filename, cpu_model); |
700 |
} |
701 |
|
702 |
/* SPARCserver 600MP hardware initialisation */
|
703 |
static void ss600mp_init(int RAM_size, int vga_ram_size, |
704 |
const char *boot_device, DisplayState *ds, |
705 |
const char *kernel_filename, const char *kernel_cmdline, |
706 |
const char *initrd_filename, const char *cpu_model) |
707 |
{ |
708 |
sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
|
709 |
kernel_cmdline, initrd_filename, cpu_model); |
710 |
} |
711 |
|
712 |
/* SPARCstation 20 hardware initialisation */
|
713 |
static void ss20_init(int RAM_size, int vga_ram_size, |
714 |
const char *boot_device, DisplayState *ds, |
715 |
const char *kernel_filename, const char *kernel_cmdline, |
716 |
const char *initrd_filename, const char *cpu_model) |
717 |
{ |
718 |
sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
|
719 |
kernel_cmdline, initrd_filename, cpu_model); |
720 |
} |
721 |
|
722 |
QEMUMachine ss5_machine = { |
723 |
"SS-5",
|
724 |
"Sun4m platform, SPARCstation 5",
|
725 |
ss5_init, |
726 |
}; |
727 |
|
728 |
QEMUMachine ss10_machine = { |
729 |
"SS-10",
|
730 |
"Sun4m platform, SPARCstation 10",
|
731 |
ss10_init, |
732 |
}; |
733 |
|
734 |
QEMUMachine ss600mp_machine = { |
735 |
"SS-600MP",
|
736 |
"Sun4m platform, SPARCserver 600MP",
|
737 |
ss600mp_init, |
738 |
}; |
739 |
|
740 |
QEMUMachine ss20_machine = { |
741 |
"SS-20",
|
742 |
"Sun4m platform, SPARCstation 20",
|
743 |
ss20_init, |
744 |
}; |
745 |
|
746 |
|
747 |
static const struct sun4d_hwdef sun4d_hwdefs[] = { |
748 |
/* SS-1000 */
|
749 |
{ |
750 |
.iounit_bases = { |
751 |
0xfe0200000ULL,
|
752 |
0xfe1200000ULL,
|
753 |
0xfe2200000ULL,
|
754 |
0xfe3200000ULL,
|
755 |
-1,
|
756 |
}, |
757 |
.tcx_base = 0x820000000ULL,
|
758 |
.slavio_base = 0xf00000000ULL,
|
759 |
.ms_kb_base = 0xf00240000ULL,
|
760 |
.serial_base = 0xf00200000ULL,
|
761 |
.nvram_base = 0xf00280000ULL,
|
762 |
.counter_base = 0xf00300000ULL,
|
763 |
.espdma_base = 0x800081000ULL,
|
764 |
.esp_base = 0x800080000ULL,
|
765 |
.ledma_base = 0x800040000ULL,
|
766 |
.le_base = 0x800060000ULL,
|
767 |
.sbi_base = 0xf02800000ULL,
|
768 |
.vram_size = 0x00100000,
|
769 |
.nvram_size = 0x2000,
|
770 |
.esp_irq = 3,
|
771 |
.le_irq = 4,
|
772 |
.clock_irq = 14,
|
773 |
.clock1_irq = 10,
|
774 |
.ms_kb_irq = 12,
|
775 |
.ser_irq = 12,
|
776 |
.machine_id = 0x80,
|
777 |
.iounit_version = 0x03000000,
|
778 |
.max_mem = 0xffffffff, // XXX actually first 62GB ok |
779 |
.default_cpu_model = "TI SuperSparc II",
|
780 |
}, |
781 |
/* SS-2000 */
|
782 |
{ |
783 |
.iounit_bases = { |
784 |
0xfe0200000ULL,
|
785 |
0xfe1200000ULL,
|
786 |
0xfe2200000ULL,
|
787 |
0xfe3200000ULL,
|
788 |
0xfe4200000ULL,
|
789 |
}, |
790 |
.tcx_base = 0x820000000ULL,
|
791 |
.slavio_base = 0xf00000000ULL,
|
792 |
.ms_kb_base = 0xf00240000ULL,
|
793 |
.serial_base = 0xf00200000ULL,
|
794 |
.nvram_base = 0xf00280000ULL,
|
795 |
.counter_base = 0xf00300000ULL,
|
796 |
.espdma_base = 0x800081000ULL,
|
797 |
.esp_base = 0x800080000ULL,
|
798 |
.ledma_base = 0x800040000ULL,
|
799 |
.le_base = 0x800060000ULL,
|
800 |
.sbi_base = 0xf02800000ULL,
|
801 |
.vram_size = 0x00100000,
|
802 |
.nvram_size = 0x2000,
|
803 |
.esp_irq = 3,
|
804 |
.le_irq = 4,
|
805 |
.clock_irq = 14,
|
806 |
.clock1_irq = 10,
|
807 |
.ms_kb_irq = 12,
|
808 |
.ser_irq = 12,
|
809 |
.machine_id = 0x80,
|
810 |
.iounit_version = 0x03000000,
|
811 |
.max_mem = 0xffffffff, // XXX actually first 62GB ok |
812 |
.default_cpu_model = "TI SuperSparc II",
|
813 |
}, |
814 |
}; |
815 |
|
816 |
static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, int RAM_size, |
817 |
const char *boot_device, |
818 |
DisplayState *ds, const char *kernel_filename, |
819 |
const char *kernel_cmdline, |
820 |
const char *initrd_filename, const char *cpu_model) |
821 |
{ |
822 |
CPUState *env, *envs[MAX_CPUS]; |
823 |
unsigned int i; |
824 |
void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
|
825 |
qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq, |
826 |
*espdma_irq, *ledma_irq; |
827 |
qemu_irq *esp_reset, *le_reset; |
828 |
unsigned long prom_offset, kernel_size; |
829 |
int ret;
|
830 |
char buf[1024]; |
831 |
int index;
|
832 |
|
833 |
/* init CPUs */
|
834 |
if (!cpu_model)
|
835 |
cpu_model = hwdef->default_cpu_model; |
836 |
|
837 |
for (i = 0; i < smp_cpus; i++) { |
838 |
env = cpu_init(cpu_model); |
839 |
if (!env) {
|
840 |
fprintf(stderr, "Unable to find Sparc CPU definition\n");
|
841 |
exit(1);
|
842 |
} |
843 |
cpu_sparc_set_id(env, i); |
844 |
envs[i] = env; |
845 |
if (i == 0) { |
846 |
qemu_register_reset(main_cpu_reset, env); |
847 |
} else {
|
848 |
qemu_register_reset(secondary_cpu_reset, env); |
849 |
env->halted = 1;
|
850 |
} |
851 |
register_savevm("cpu", i, 3, cpu_save, cpu_load, env); |
852 |
cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
853 |
env->prom_addr = hwdef->slavio_base; |
854 |
} |
855 |
|
856 |
for (i = smp_cpus; i < MAX_CPUS; i++)
|
857 |
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
858 |
|
859 |
/* allocate RAM */
|
860 |
if ((uint64_t)RAM_size > hwdef->max_mem) {
|
861 |
fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
|
862 |
(unsigned int)RAM_size / (1024 * 1024), |
863 |
(unsigned int)(hwdef->max_mem / (1024 * 1024))); |
864 |
exit(1);
|
865 |
} |
866 |
cpu_register_physical_memory(0, RAM_size, 0); |
867 |
|
868 |
/* load boot prom */
|
869 |
prom_offset = RAM_size + hwdef->vram_size; |
870 |
cpu_register_physical_memory(hwdef->slavio_base, |
871 |
(PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
872 |
TARGET_PAGE_MASK, |
873 |
prom_offset | IO_MEM_ROM); |
874 |
|
875 |
if (bios_name == NULL) |
876 |
bios_name = PROM_FILENAME; |
877 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
878 |
ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
879 |
if (ret < 0 || ret > PROM_SIZE_MAX) |
880 |
ret = load_image(buf, phys_ram_base + prom_offset); |
881 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
882 |
fprintf(stderr, "qemu: could not load prom '%s'\n",
|
883 |
buf); |
884 |
exit(1);
|
885 |
} |
886 |
|
887 |
/* set up devices */
|
888 |
sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs); |
889 |
|
890 |
for (i = 0; i < MAX_IOUNITS; i++) |
891 |
if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) |
892 |
iounits[i] = iommu_init(hwdef->iounit_bases[i], hwdef->iounit_version); |
893 |
|
894 |
espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq], |
895 |
iounits[0], &espdma_irq, &esp_reset);
|
896 |
|
897 |
ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq], |
898 |
iounits[0], &ledma_irq, &le_reset);
|
899 |
|
900 |
if (graphic_depth != 8 && graphic_depth != 24) { |
901 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
902 |
exit (1);
|
903 |
} |
904 |
tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
905 |
hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
906 |
|
907 |
if (nd_table[0].model == NULL |
908 |
|| strcmp(nd_table[0].model, "lance") == 0) { |
909 |
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
910 |
} else if (strcmp(nd_table[0].model, "?") == 0) { |
911 |
fprintf(stderr, "qemu: Supported NICs: lance\n");
|
912 |
exit (1);
|
913 |
} else {
|
914 |
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
915 |
exit (1);
|
916 |
} |
917 |
|
918 |
nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, |
919 |
hwdef->nvram_size, 8);
|
920 |
|
921 |
slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq], |
922 |
sbi_cpu_irq, smp_cpus); |
923 |
|
924 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq], |
925 |
nographic); |
926 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
927 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
928 |
slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], |
929 |
serial_hds[1], serial_hds[0]); |
930 |
|
931 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
932 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
933 |
exit(1);
|
934 |
} |
935 |
|
936 |
main_esp = esp_init(hwdef->esp_base, espdma, *espdma_irq, |
937 |
esp_reset); |
938 |
|
939 |
for (i = 0; i < ESP_MAX_DEVS; i++) { |
940 |
index = drive_get_index(IF_SCSI, 0, i);
|
941 |
if (index == -1) |
942 |
continue;
|
943 |
esp_scsi_attach(main_esp, drives_table[index].bdrv, i); |
944 |
} |
945 |
|
946 |
kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline, |
947 |
initrd_filename); |
948 |
|
949 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
950 |
boot_device, RAM_size, kernel_size, graphic_width, |
951 |
graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
|
952 |
} |
953 |
|
954 |
/* SPARCserver 1000 hardware initialisation */
|
955 |
static void ss1000_init(int RAM_size, int vga_ram_size, |
956 |
const char *boot_device, DisplayState *ds, |
957 |
const char *kernel_filename, const char *kernel_cmdline, |
958 |
const char *initrd_filename, const char *cpu_model) |
959 |
{ |
960 |
sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
|
961 |
kernel_cmdline, initrd_filename, cpu_model); |
962 |
} |
963 |
|
964 |
/* SPARCcenter 2000 hardware initialisation */
|
965 |
static void ss2000_init(int RAM_size, int vga_ram_size, |
966 |
const char *boot_device, DisplayState *ds, |
967 |
const char *kernel_filename, const char *kernel_cmdline, |
968 |
const char *initrd_filename, const char *cpu_model) |
969 |
{ |
970 |
sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
|
971 |
kernel_cmdline, initrd_filename, cpu_model); |
972 |
} |
973 |
|
974 |
QEMUMachine ss1000_machine = { |
975 |
"SS-1000",
|
976 |
"Sun4d platform, SPARCserver 1000",
|
977 |
ss1000_init, |
978 |
}; |
979 |
|
980 |
QEMUMachine ss2000_machine = { |
981 |
"SS-2000",
|
982 |
"Sun4d platform, SPARCcenter 2000",
|
983 |
ss2000_init, |
984 |
}; |