Revision 7d932dfd hw/hpet.c

b/hw/hpet.c
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#include "qemu-timer.h"
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#include "hpet_emul.h"
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#include "sysbus.h"
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#include "mc146818rtc.h"
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//#define HPET_DEBUG
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#ifdef HPET_DEBUG
......
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    SysBusDevice busdev;
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    uint64_t hpet_offset;
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    qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
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    uint8_t rtc_irq_level;
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    HPETTimer timer[HPET_NUM_TIMERS];
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    /* Memory-mapped, software visible registers */
......
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static HPETState *hpet_statep;
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uint32_t hpet_in_legacy_mode(void)
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static uint32_t hpet_in_legacy_mode(HPETState *s)
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{
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    if (!hpet_statep) {
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        return 0;
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    }
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    return hpet_statep->config & HPET_CFG_LEGACY;
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    return s->config & HPET_CFG_LEGACY;
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}
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static uint32_t timer_int_route(struct HPETTimer *timer)
......
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{
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    int route;
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    if (timer->tn <= 1 && hpet_in_legacy_mode()) {
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    if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) {
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        /* if LegacyReplacementRoute bit is set, HPET specification requires
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         * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
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         * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
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         */
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        route = (timer->tn == 0) ? 0 : 8;
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        route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ;
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    } else {
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        route = timer_int_route(timer);
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    }
......
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            /* i8254 and RTC are disabled when HPET is in legacy mode */
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            if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
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                hpet_pit_disable();
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                qemu_irq_lower(s->irqs[RTC_ISA_IRQ]);
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            } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
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                hpet_pit_enable();
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                qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level);
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            }
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            break;
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        case HPET_CFG + 4:
......
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    count = 1;
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}
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static void hpet_handle_rtc_irq(void *opaque, int n, int level)
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{
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    HPETState *s = FROM_SYSBUS(HPETState, opaque);
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    s->rtc_irq_level = level;
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    if (!hpet_in_legacy_mode(s)) {
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        qemu_set_irq(s->irqs[RTC_ISA_IRQ], level);
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    }
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}
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static int hpet_init(SysBusDevice *dev)
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{
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    HPETState *s = FROM_SYSBUS(HPETState, dev);
......
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        timer->state = s;
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    }
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    isa_reserve_irq(RTC_ISA_IRQ);
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    qdev_init_gpio_in(&dev->qdev, hpet_handle_rtc_irq, 1);
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    /* HPET Area */
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    iomemtype = cpu_register_io_memory(hpet_ram_read,
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                                       hpet_ram_write, s);

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