Revision 7efbe241 target-sh4/translate.c
| b/target-sh4/translate.c | ||
|---|---|---|
| 366 | 366 |
#define B15_12 ((ctx->opcode >> 12) & 0xf) |
| 367 | 367 |
|
| 368 | 368 |
#define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \ |
| 369 |
(x) + 16 : (x))
|
|
| 369 |
(cpu_gregs[x + 16]) : (cpu_gregs[x]))
|
|
| 370 | 370 |
|
| 371 | 371 |
#define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \ |
| 372 |
? (x) + 16 : (x))
|
|
| 372 |
? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
|
|
| 373 | 373 |
|
| 374 | 374 |
#define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x)) |
| 375 | 375 |
#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) |
| ... | ... | |
| 448 | 448 |
|
| 449 | 449 |
switch (ctx->opcode & 0xf000) {
|
| 450 | 450 |
case 0x1000: /* mov.l Rm,@(disp,Rn) */ |
| 451 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 452 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 453 |
tcg_gen_addi_i32(cpu_T[1], cpu_T[1], B3_0 * 4); |
|
| 454 |
tcg_gen_qemu_st32(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 451 |
tcg_gen_addi_i32(cpu_T[0], REG(B11_8), B3_0 * 4); |
|
| 452 |
tcg_gen_qemu_st32(REG(B7_4), cpu_T[0], ctx->memidx); |
|
| 455 | 453 |
return; |
| 456 | 454 |
case 0x5000: /* mov.l @(disp,Rm),Rn */ |
| 457 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 458 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B3_0 * 4); |
|
| 459 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 460 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 455 |
tcg_gen_addi_i32(cpu_T[0], REG(B7_4), B3_0 * 4); |
|
| 456 |
tcg_gen_qemu_ld32s(REG(B11_8), cpu_T[0], ctx->memidx); |
|
| 461 | 457 |
return; |
| 462 | 458 |
case 0xe000: /* mov #imm,Rn */ |
| 463 |
tcg_gen_movi_i32(cpu_gregs[REG(B11_8)], B7_0s);
|
|
| 459 |
tcg_gen_movi_i32(REG(B11_8), B7_0s);
|
|
| 464 | 460 |
return; |
| 465 | 461 |
case 0x9000: /* mov.w @(disp,PC),Rn */ |
| 466 | 462 |
tcg_gen_movi_i32(cpu_T[0], ctx->pc + 4 + B7_0 * 2); |
| 467 |
tcg_gen_qemu_ld16s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 468 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 463 |
tcg_gen_qemu_ld16s(REG(B11_8), cpu_T[0], ctx->memidx); |
|
| 469 | 464 |
return; |
| 470 | 465 |
case 0xd000: /* mov.l @(disp,PC),Rn */ |
| 471 | 466 |
tcg_gen_movi_i32(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3); |
| 472 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 473 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 467 |
tcg_gen_qemu_ld32s(REG(B11_8), cpu_T[0], ctx->memidx); |
|
| 474 | 468 |
return; |
| 475 | 469 |
case 0x7000: /* add #imm,Rn */ |
| 476 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], B7_0s);
|
|
| 470 |
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s);
|
|
| 477 | 471 |
return; |
| 478 | 472 |
case 0xa000: /* bra disp */ |
| 479 | 473 |
CHECK_NOT_DELAY_SLOT |
| ... | ... | |
| 492 | 486 |
|
| 493 | 487 |
switch (ctx->opcode & 0xf00f) {
|
| 494 | 488 |
case 0x6003: /* mov Rm,Rn */ |
| 495 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 496 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 489 |
tcg_gen_mov_i32(REG(B11_8), REG(B7_4)); |
|
| 497 | 490 |
return; |
| 498 | 491 |
case 0x2000: /* mov.b Rm,@Rn */ |
| 499 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 500 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 501 |
tcg_gen_qemu_st8(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 492 |
tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx); |
|
| 502 | 493 |
return; |
| 503 | 494 |
case 0x2001: /* mov.w Rm,@Rn */ |
| 504 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 505 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 506 |
tcg_gen_qemu_st16(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 495 |
tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx); |
|
| 507 | 496 |
return; |
| 508 | 497 |
case 0x2002: /* mov.l Rm,@Rn */ |
| 509 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 510 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 511 |
tcg_gen_qemu_st32(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 498 |
tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx); |
|
| 512 | 499 |
return; |
| 513 | 500 |
case 0x6000: /* mov.b @Rm,Rn */ |
| 514 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 515 |
tcg_gen_qemu_ld8s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 516 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 501 |
tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx); |
|
| 517 | 502 |
return; |
| 518 | 503 |
case 0x6001: /* mov.w @Rm,Rn */ |
| 519 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 520 |
tcg_gen_qemu_ld16s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 521 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 504 |
tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx); |
|
| 522 | 505 |
return; |
| 523 | 506 |
case 0x6002: /* mov.l @Rm,Rn */ |
| 524 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 525 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 526 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 507 |
tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx); |
|
| 527 | 508 |
return; |
| 528 | 509 |
case 0x2004: /* mov.b Rm,@-Rn */ |
| 529 |
tcg_gen_subi_i32(cpu_T[1], cpu_gregs[REG(B11_8)], 1); |
|
| 530 |
tcg_gen_qemu_st8(cpu_gregs[REG(B7_4)], cpu_T[1], ctx->memidx); /* might cause re-execution */ |
|
| 531 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], |
|
| 532 |
cpu_gregs[REG(B11_8)], 1); /* modify register status */ |
|
| 510 |
tcg_gen_subi_i32(cpu_T[0], REG(B11_8), 1); |
|
| 511 |
tcg_gen_qemu_st8(REG(B7_4), cpu_T[0], ctx->memidx); /* might cause re-execution */ |
|
| 512 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); /* modify register status */ |
|
| 533 | 513 |
return; |
| 534 | 514 |
case 0x2005: /* mov.w Rm,@-Rn */ |
| 535 |
tcg_gen_subi_i32(cpu_T[1], cpu_gregs[REG(B11_8)], 2); |
|
| 536 |
tcg_gen_qemu_st16(cpu_gregs[REG(B7_4)], cpu_T[1], ctx->memidx); |
|
| 537 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], |
|
| 538 |
cpu_gregs[REG(B11_8)], 2); |
|
| 515 |
tcg_gen_subi_i32(cpu_T[0], REG(B11_8), 2); |
|
| 516 |
tcg_gen_qemu_st16(REG(B7_4), cpu_T[0], ctx->memidx); |
|
| 517 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2); |
|
| 539 | 518 |
return; |
| 540 | 519 |
case 0x2006: /* mov.l Rm,@-Rn */ |
| 541 |
tcg_gen_subi_i32(cpu_T[1], cpu_gregs[REG(B11_8)], 4); |
|
| 542 |
tcg_gen_qemu_st32(cpu_gregs[REG(B7_4)], cpu_T[1], ctx->memidx); |
|
| 543 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], |
|
| 544 |
cpu_gregs[REG(B11_8)], 4); |
|
| 520 |
tcg_gen_subi_i32(cpu_T[0], REG(B11_8), 4); |
|
| 521 |
tcg_gen_qemu_st32(REG(B7_4), cpu_T[0], ctx->memidx); |
|
| 522 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); |
|
| 545 | 523 |
return; |
| 546 | 524 |
case 0x6004: /* mov.b @Rm+,Rn */ |
| 547 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 548 |
tcg_gen_qemu_ld8s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 549 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 525 |
tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx); |
|
| 550 | 526 |
if ( B11_8 != B7_4 ) |
| 551 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], |
|
| 552 |
cpu_gregs[REG(B7_4)], 1); |
|
| 527 |
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1); |
|
| 553 | 528 |
return; |
| 554 | 529 |
case 0x6005: /* mov.w @Rm+,Rn */ |
| 555 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 556 |
tcg_gen_qemu_ld16s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 557 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 530 |
tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx); |
|
| 558 | 531 |
if ( B11_8 != B7_4 ) |
| 559 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], |
|
| 560 |
cpu_gregs[REG(B7_4)], 2); |
|
| 532 |
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); |
|
| 561 | 533 |
return; |
| 562 | 534 |
case 0x6006: /* mov.l @Rm+,Rn */ |
| 563 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 564 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 565 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 535 |
tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx); |
|
| 566 | 536 |
if ( B11_8 != B7_4 ) |
| 567 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], |
|
| 568 |
cpu_gregs[REG(B7_4)], 4); |
|
| 537 |
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); |
|
| 569 | 538 |
return; |
| 570 | 539 |
case 0x0004: /* mov.b Rm,@(R0,Rn) */ |
| 571 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 572 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 573 |
tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]); |
|
| 574 |
tcg_gen_qemu_st8(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 540 |
tcg_gen_add_i32(cpu_T[0], REG(B11_8), REG(0)); |
|
| 541 |
tcg_gen_qemu_st8(REG(B7_4), cpu_T[0], ctx->memidx); |
|
| 575 | 542 |
return; |
| 576 | 543 |
case 0x0005: /* mov.w Rm,@(R0,Rn) */ |
| 577 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 578 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 579 |
tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]); |
|
| 580 |
tcg_gen_qemu_st16(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 544 |
tcg_gen_add_i32(cpu_T[0], REG(B11_8), REG(0)); |
|
| 545 |
tcg_gen_qemu_st16(REG(B7_4), cpu_T[0], ctx->memidx); |
|
| 581 | 546 |
return; |
| 582 | 547 |
case 0x0006: /* mov.l Rm,@(R0,Rn) */ |
| 583 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 584 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 585 |
tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]); |
|
| 586 |
tcg_gen_qemu_st32(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 548 |
tcg_gen_add_i32(cpu_T[0], REG(B11_8), REG(0)); |
|
| 549 |
tcg_gen_qemu_st32(REG(B7_4), cpu_T[0], ctx->memidx); |
|
| 587 | 550 |
return; |
| 588 | 551 |
case 0x000c: /* mov.b @(R0,Rm),Rn */ |
| 589 |
tcg_gen_add_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(0)]); |
|
| 590 |
tcg_gen_qemu_ld8s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 591 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 552 |
tcg_gen_add_i32(cpu_T[0], REG(B7_4), REG(0)); |
|
| 553 |
tcg_gen_qemu_ld8s(REG(B11_8), cpu_T[0], ctx->memidx); |
|
| 592 | 554 |
return; |
| 593 | 555 |
case 0x000d: /* mov.w @(R0,Rm),Rn */ |
| 594 |
tcg_gen_add_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(0)]); |
|
| 595 |
tcg_gen_qemu_ld16s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 596 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 556 |
tcg_gen_add_i32(cpu_T[0], REG(B7_4), REG(0)); |
|
| 557 |
tcg_gen_qemu_ld16s(REG(B11_8), cpu_T[0], ctx->memidx); |
|
| 597 | 558 |
return; |
| 598 | 559 |
case 0x000e: /* mov.l @(R0,Rm),Rn */ |
| 599 |
tcg_gen_add_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(0)]); |
|
| 600 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 601 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 560 |
tcg_gen_add_i32(cpu_T[0], REG(B7_4), REG(0)); |
|
| 561 |
tcg_gen_qemu_ld32s(REG(B11_8), cpu_T[0], ctx->memidx); |
|
| 602 | 562 |
return; |
| 603 | 563 |
case 0x6008: /* swap.b Rm,Rn */ |
| 604 |
tcg_gen_andi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)], 0xffff0000); |
|
| 605 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0xff); |
|
| 564 |
tcg_gen_ext8u_i32(cpu_T[0], REG(B7_4)); |
|
| 606 | 565 |
tcg_gen_shli_i32(cpu_T[0], cpu_T[0], 8); |
| 607 |
tcg_gen_or_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 608 |
tcg_gen_shri_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 8); |
|
| 609 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff); |
|
| 610 |
tcg_gen_or_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 566 |
tcg_gen_shri_i32(cpu_T[1], REG(B7_4), 8); |
|
| 567 |
tcg_gen_ext8u_i32(cpu_T[1], cpu_T[1]); |
|
| 568 |
tcg_gen_or_i32(REG(B11_8), cpu_T[0], cpu_T[1]); |
|
| 611 | 569 |
return; |
| 612 | 570 |
case 0x6009: /* swap.w Rm,Rn */ |
| 613 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0xffff);
|
|
| 571 |
tcg_gen_ext16u_i32(cpu_T[0], REG(B7_4));
|
|
| 614 | 572 |
tcg_gen_shli_i32(cpu_T[0], cpu_T[0], 16); |
| 615 |
tcg_gen_shri_i32(cpu_T[1], cpu_gregs[REG(B7_4)], 16);
|
|
| 616 |
tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff);
|
|
| 617 |
tcg_gen_or_i32(cpu_gregs[REG(B11_8)], cpu_T[0], cpu_T[1]);
|
|
| 573 |
tcg_gen_shri_i32(cpu_T[1], REG(B7_4), 16);
|
|
| 574 |
tcg_gen_ext16u_i32(cpu_T[1], cpu_T[1]);
|
|
| 575 |
tcg_gen_or_i32(REG(B11_8), cpu_T[0], cpu_T[1]);
|
|
| 618 | 576 |
return; |
| 619 | 577 |
case 0x200d: /* xtrct Rm,Rn */ |
| 620 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0xffff);
|
|
| 578 |
tcg_gen_ext16u_i32(cpu_T[0], REG(B7_4));
|
|
| 621 | 579 |
tcg_gen_shli_i32(cpu_T[0], cpu_T[0], 16); |
| 622 |
tcg_gen_shri_i32(cpu_T[1], cpu_gregs[REG(B11_8)], 16);
|
|
| 623 |
tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff);
|
|
| 624 |
tcg_gen_or_i32(cpu_gregs[REG(B11_8)], cpu_T[0], cpu_T[1]);
|
|
| 580 |
tcg_gen_shri_i32(cpu_T[1], REG(B11_8), 16);
|
|
| 581 |
tcg_gen_ext16u_i32(cpu_T[1], cpu_T[1]);
|
|
| 582 |
tcg_gen_or_i32(REG(B11_8), cpu_T[0], cpu_T[1]);
|
|
| 625 | 583 |
return; |
| 626 | 584 |
case 0x300c: /* add Rm,Rn */ |
| 627 |
tcg_gen_add_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]);
|
|
| 585 |
tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
|
|
| 628 | 586 |
return; |
| 629 | 587 |
case 0x300e: /* addc Rm,Rn */ |
| 630 |
tcg_gen_helper_1_2(helper_addc, cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)], cpu_gregs[REG(B11_8)]);
|
|
| 588 |
tcg_gen_helper_1_2(helper_addc, REG(B11_8), REG(B7_4), REG(B11_8));
|
|
| 631 | 589 |
return; |
| 632 | 590 |
case 0x300f: /* addv Rm,Rn */ |
| 633 |
tcg_gen_helper_1_2(helper_addv, cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)], cpu_gregs[REG(B11_8)]);
|
|
| 591 |
tcg_gen_helper_1_2(helper_addv, REG(B11_8), REG(B7_4), REG(B11_8));
|
|
| 634 | 592 |
return; |
| 635 | 593 |
case 0x2009: /* and Rm,Rn */ |
| 636 |
tcg_gen_and_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]);
|
|
| 594 |
tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4));
|
|
| 637 | 595 |
return; |
| 638 | 596 |
case 0x3000: /* cmp/eq Rm,Rn */ |
| 639 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 640 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 641 |
gen_cmp(TCG_COND_EQ, cpu_T[0], cpu_T[1]); |
|
| 597 |
gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8)); |
|
| 642 | 598 |
return; |
| 643 | 599 |
case 0x3003: /* cmp/ge Rm,Rn */ |
| 644 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 645 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 646 |
gen_cmp(TCG_COND_GE, cpu_T[0], cpu_T[1]); |
|
| 600 |
gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8)); |
|
| 647 | 601 |
return; |
| 648 | 602 |
case 0x3007: /* cmp/gt Rm,Rn */ |
| 649 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 650 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 651 |
gen_cmp(TCG_COND_GT, cpu_T[0], cpu_T[1]); |
|
| 603 |
gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8)); |
|
| 652 | 604 |
return; |
| 653 | 605 |
case 0x3006: /* cmp/hi Rm,Rn */ |
| 654 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 655 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 656 |
gen_cmp(TCG_COND_GTU, cpu_T[0], cpu_T[1]); |
|
| 606 |
gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8)); |
|
| 657 | 607 |
return; |
| 658 | 608 |
case 0x3002: /* cmp/hs Rm,Rn */ |
| 659 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 660 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 661 |
gen_cmp(TCG_COND_GEU, cpu_T[0], cpu_T[1]); |
|
| 609 |
gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8)); |
|
| 662 | 610 |
return; |
| 663 | 611 |
case 0x200c: /* cmp/str Rm,Rn */ |
| 664 | 612 |
{
|
| 665 | 613 |
int label1 = gen_new_label(); |
| 666 | 614 |
int label2 = gen_new_label(); |
| 667 |
tcg_gen_xor_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(B11_8)]);
|
|
| 615 |
tcg_gen_xor_i32(cpu_T[0], REG(B7_4), REG(B11_8));
|
|
| 668 | 616 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff000000); |
| 669 | 617 |
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_T[0], 0, label1); |
| 670 | 618 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0x00ff0000); |
| ... | ... | |
| 681 | 629 |
} |
| 682 | 630 |
return; |
| 683 | 631 |
case 0x2007: /* div0s Rm,Rn */ |
| 684 |
gen_copy_bit_i32(cpu_sr, 8, cpu_gregs[REG(B11_8)], 31); /* SR_Q */
|
|
| 685 |
gen_copy_bit_i32(cpu_sr, 9, cpu_gregs[REG(B7_4)], 31); /* SR_M */
|
|
| 686 |
tcg_gen_xor_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(B11_8)]);
|
|
| 687 |
gen_copy_bit_i32(cpu_sr, 0, cpu_T[0], 31); /* SR_T */
|
|
| 632 |
gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31); /* SR_Q */
|
|
| 633 |
gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31); /* SR_M */
|
|
| 634 |
tcg_gen_xor_i32(cpu_T[0], REG(B7_4), REG(B11_8));
|
|
| 635 |
gen_copy_bit_i32(cpu_sr, 0, cpu_T[0], 31); /* SR_T */ |
|
| 688 | 636 |
return; |
| 689 | 637 |
case 0x3004: /* div1 Rm,Rn */ |
| 690 |
tcg_gen_helper_1_2(helper_div1, cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)], cpu_gregs[REG(B11_8)]);
|
|
| 638 |
tcg_gen_helper_1_2(helper_div1, REG(B11_8), REG(B7_4), REG(B11_8));
|
|
| 691 | 639 |
return; |
| 692 | 640 |
case 0x300d: /* dmuls.l Rm,Rn */ |
| 693 | 641 |
{
|
| 694 | 642 |
TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64); |
| 695 | 643 |
TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64); |
| 696 | 644 |
|
| 697 |
tcg_gen_ext_i32_i64(tmp1, cpu_gregs[REG(B7_4)]);
|
|
| 698 |
tcg_gen_ext_i32_i64(tmp2, cpu_gregs[REG(B11_8)]);
|
|
| 645 |
tcg_gen_ext_i32_i64(tmp1, REG(B7_4));
|
|
| 646 |
tcg_gen_ext_i32_i64(tmp2, REG(B11_8));
|
|
| 699 | 647 |
tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
| 700 | 648 |
tcg_gen_trunc_i64_i32(cpu_macl, tmp1); |
| 701 | 649 |
tcg_gen_shri_i64(tmp1, tmp1, 32); |
| ... | ... | |
| 710 | 658 |
TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64); |
| 711 | 659 |
TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64); |
| 712 | 660 |
|
| 713 |
tcg_gen_extu_i32_i64(tmp1, cpu_gregs[REG(B7_4)]);
|
|
| 714 |
tcg_gen_extu_i32_i64(tmp2, cpu_gregs[REG(B11_8)]);
|
|
| 661 |
tcg_gen_extu_i32_i64(tmp1, REG(B7_4));
|
|
| 662 |
tcg_gen_extu_i32_i64(tmp2, REG(B11_8));
|
|
| 715 | 663 |
tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
| 716 | 664 |
tcg_gen_trunc_i64_i32(cpu_macl, tmp1); |
| 717 | 665 |
tcg_gen_shri_i64(tmp1, tmp1, 32); |
| ... | ... | |
| 722 | 670 |
} |
| 723 | 671 |
return; |
| 724 | 672 |
case 0x600e: /* exts.b Rm,Rn */ |
| 725 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 726 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff); |
|
| 727 |
tcg_gen_ext8s_i32(cpu_T[0], cpu_T[0]); |
|
| 728 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 673 |
tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4)); |
|
| 729 | 674 |
return; |
| 730 | 675 |
case 0x600f: /* exts.w Rm,Rn */ |
| 731 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 732 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff); |
|
| 733 |
tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]); |
|
| 734 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 676 |
tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4)); |
|
| 735 | 677 |
return; |
| 736 | 678 |
case 0x600c: /* extu.b Rm,Rn */ |
| 737 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 738 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff); |
|
| 739 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 679 |
tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4)); |
|
| 740 | 680 |
return; |
| 741 | 681 |
case 0x600d: /* extu.w Rm,Rn */ |
| 742 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 743 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff); |
|
| 744 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 682 |
tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4)); |
|
| 745 | 683 |
return; |
| 746 | 684 |
case 0x000f: /* mac.l @Rm+,@Rn+ */ |
| 747 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); |
|
| 748 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 749 |
tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); |
|
| 750 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 751 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 685 |
tcg_gen_qemu_ld32s(cpu_T[0], REG(B7_4), ctx->memidx); |
|
| 686 |
tcg_gen_qemu_ld32s(cpu_T[1], REG(B11_8), ctx->memidx); |
|
| 752 | 687 |
tcg_gen_helper_0_2(helper_macl, cpu_T[0], cpu_T[1]); |
| 753 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], cpu_gregs[REG(B7_4)], 4);
|
|
| 754 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
|
| 688 |
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
|
|
| 689 |
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
|
| 755 | 690 |
return; |
| 756 | 691 |
case 0x400f: /* mac.w @Rm+,@Rn+ */ |
| 757 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); |
|
| 758 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 759 |
tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); |
|
| 760 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 761 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 692 |
tcg_gen_qemu_ld32s(cpu_T[0], REG(B7_4), ctx->memidx); |
|
| 693 |
tcg_gen_qemu_ld32s(cpu_T[1], REG(B11_8), ctx->memidx); |
|
| 762 | 694 |
tcg_gen_helper_0_2(helper_macw, cpu_T[0], cpu_T[1]); |
| 763 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 2);
|
|
| 764 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], cpu_gregs[REG(B7_4)], 2);
|
|
| 695 |
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);
|
|
| 696 |
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
|
|
| 765 | 697 |
return; |
| 766 | 698 |
case 0x0007: /* mul.l Rm,Rn */ |
| 767 |
tcg_gen_mul_i32(cpu_macl, cpu_gregs[REG(B7_4)], cpu_gregs[REG(B11_8)]);
|
|
| 699 |
tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8));
|
|
| 768 | 700 |
return; |
| 769 | 701 |
case 0x200f: /* muls.w Rm,Rn */ |
| 770 |
tcg_gen_ext16s_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
|
| 771 |
tcg_gen_ext16s_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
|
| 702 |
tcg_gen_ext16s_i32(cpu_T[0], REG(B7_4));
|
|
| 703 |
tcg_gen_ext16s_i32(cpu_T[1], REG(B11_8));
|
|
| 772 | 704 |
tcg_gen_mul_i32(cpu_macl, cpu_T[0], cpu_T[1]); |
| 773 | 705 |
return; |
| 774 | 706 |
case 0x200e: /* mulu.w Rm,Rn */ |
| 775 |
tcg_gen_ext16u_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
|
| 776 |
tcg_gen_ext16u_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
|
| 707 |
tcg_gen_ext16u_i32(cpu_T[0], REG(B7_4));
|
|
| 708 |
tcg_gen_ext16u_i32(cpu_T[1], REG(B11_8));
|
|
| 777 | 709 |
tcg_gen_mul_i32(cpu_macl, cpu_T[0], cpu_T[1]); |
| 778 | 710 |
return; |
| 779 | 711 |
case 0x600b: /* neg Rm,Rn */ |
| 780 |
tcg_gen_neg_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]);
|
|
| 712 |
tcg_gen_neg_i32(REG(B11_8), REG(B7_4));
|
|
| 781 | 713 |
return; |
| 782 | 714 |
case 0x600a: /* negc Rm,Rn */ |
| 783 |
tcg_gen_helper_1_1(helper_negc, cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]);
|
|
| 715 |
tcg_gen_helper_1_1(helper_negc, REG(B11_8), REG(B7_4));
|
|
| 784 | 716 |
return; |
| 785 | 717 |
case 0x6007: /* not Rm,Rn */ |
| 786 |
tcg_gen_not_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]);
|
|
| 718 |
tcg_gen_not_i32(REG(B11_8), REG(B7_4));
|
|
| 787 | 719 |
return; |
| 788 | 720 |
case 0x200b: /* or Rm,Rn */ |
| 789 |
tcg_gen_or_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]);
|
|
| 721 |
tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4));
|
|
| 790 | 722 |
return; |
| 791 | 723 |
case 0x400c: /* shad Rm,Rn */ |
| 792 | 724 |
{
|
| ... | ... | |
| 794 | 726 |
int label2 = gen_new_label(); |
| 795 | 727 |
int label3 = gen_new_label(); |
| 796 | 728 |
int label4 = gen_new_label(); |
| 797 |
tcg_gen_brcondi_i32(TCG_COND_LT, cpu_gregs[REG(B7_4)], 0, label1);
|
|
| 729 |
tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
|
|
| 798 | 730 |
/* Rm positive, shift to the left */ |
| 799 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0x1f);
|
|
| 800 |
tcg_gen_shl_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]);
|
|
| 731 |
tcg_gen_andi_i32(cpu_T[0], REG(B7_4), 0x1f);
|
|
| 732 |
tcg_gen_shl_i32(REG(B11_8), REG(B11_8), cpu_T[0]);
|
|
| 801 | 733 |
tcg_gen_br(label4); |
| 802 | 734 |
/* Rm negative, shift to the right */ |
| 803 | 735 |
gen_set_label(label1); |
| 804 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0x1f);
|
|
| 736 |
tcg_gen_andi_i32(cpu_T[0], REG(B7_4), 0x1f);
|
|
| 805 | 737 |
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_T[0], 0, label2); |
| 806 |
tcg_gen_not_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
|
| 738 |
tcg_gen_not_i32(cpu_T[0], REG(B7_4));
|
|
| 807 | 739 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0x1f); |
| 808 | 740 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], 1); |
| 809 |
tcg_gen_sar_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]);
|
|
| 741 |
tcg_gen_sar_i32(REG(B11_8), REG(B11_8), cpu_T[0]);
|
|
| 810 | 742 |
tcg_gen_br(label4); |
| 811 | 743 |
/* Rm = -32 */ |
| 812 | 744 |
gen_set_label(label2); |
| 813 |
tcg_gen_brcondi_i32(TCG_COND_LT, cpu_gregs[REG(B11_8)], 0, label3);
|
|
| 814 |
tcg_gen_movi_i32(cpu_gregs[REG(B11_8)], 0);
|
|
| 745 |
tcg_gen_brcondi_i32(TCG_COND_LT, REG(B11_8), 0, label3);
|
|
| 746 |
tcg_gen_movi_i32(REG(B11_8), 0);
|
|
| 815 | 747 |
tcg_gen_br(label4); |
| 816 | 748 |
gen_set_label(label3); |
| 817 |
tcg_gen_movi_i32(cpu_gregs[REG(B11_8)], 0xffffffff);
|
|
| 749 |
tcg_gen_movi_i32(REG(B11_8), 0xffffffff);
|
|
| 818 | 750 |
gen_set_label(label4); |
| 819 | 751 |
} |
| 820 | 752 |
return; |
| ... | ... | |
| 823 | 755 |
int label1 = gen_new_label(); |
| 824 | 756 |
int label2 = gen_new_label(); |
| 825 | 757 |
int label3 = gen_new_label(); |
| 826 |
tcg_gen_brcondi_i32(TCG_COND_LT, cpu_gregs[REG(B7_4)], 0, label1);
|
|
| 758 |
tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
|
|
| 827 | 759 |
/* Rm positive, shift to the left */ |
| 828 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0x1f);
|
|
| 829 |
tcg_gen_shl_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]);
|
|
| 760 |
tcg_gen_andi_i32(cpu_T[0], REG(B7_4), 0x1f);
|
|
| 761 |
tcg_gen_shl_i32(REG(B11_8), REG(B11_8), cpu_T[0]);
|
|
| 830 | 762 |
tcg_gen_br(label3); |
| 831 | 763 |
/* Rm negative, shift to the right */ |
| 832 | 764 |
gen_set_label(label1); |
| 833 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0x1f);
|
|
| 765 |
tcg_gen_andi_i32(cpu_T[0], REG(B7_4), 0x1f);
|
|
| 834 | 766 |
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_T[0], 0, label2); |
| 835 |
tcg_gen_not_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
|
| 767 |
tcg_gen_not_i32(cpu_T[0], REG(B7_4));
|
|
| 836 | 768 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0x1f); |
| 837 | 769 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], 1); |
| 838 |
tcg_gen_shr_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]);
|
|
| 770 |
tcg_gen_shr_i32(REG(B11_8), REG(B11_8), cpu_T[0]);
|
|
| 839 | 771 |
tcg_gen_br(label3); |
| 840 | 772 |
/* Rm = -32 */ |
| 841 | 773 |
gen_set_label(label2); |
| 842 |
tcg_gen_movi_i32(cpu_gregs[REG(B11_8)], 0);
|
|
| 774 |
tcg_gen_movi_i32(REG(B11_8), 0);
|
|
| 843 | 775 |
gen_set_label(label3); |
| 844 | 776 |
} |
| 845 | 777 |
return; |
| 846 | 778 |
case 0x3008: /* sub Rm,Rn */ |
| 847 |
tcg_gen_sub_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]);
|
|
| 779 |
tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4));
|
|
| 848 | 780 |
return; |
| 849 | 781 |
case 0x300a: /* subc Rm,Rn */ |
| 850 |
tcg_gen_helper_1_2(helper_subc, cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)], cpu_gregs[REG(B11_8)]);
|
|
| 782 |
tcg_gen_helper_1_2(helper_subc, REG(B11_8), REG(B7_4), REG(B11_8));
|
|
| 851 | 783 |
return; |
| 852 | 784 |
case 0x300b: /* subv Rm,Rn */ |
| 853 |
tcg_gen_helper_1_2(helper_subv, cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)], cpu_gregs[REG(B11_8)]);
|
|
| 785 |
tcg_gen_helper_1_2(helper_subv, REG(B11_8), REG(B7_4), REG(B11_8));
|
|
| 854 | 786 |
return; |
| 855 | 787 |
case 0x2008: /* tst Rm,Rn */ |
| 856 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 857 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 858 |
tcg_gen_and_i32(cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 788 |
tcg_gen_and_i32(cpu_T[0], REG(B7_4), REG(B11_8)); |
|
| 859 | 789 |
gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0); |
| 860 | 790 |
return; |
| 861 | 791 |
case 0x200a: /* xor Rm,Rn */ |
| 862 |
tcg_gen_xor_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]);
|
|
| 792 |
tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4));
|
|
| 863 | 793 |
return; |
| 864 | 794 |
case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
|
| 865 | 795 |
if (ctx->fpscr & FPSCR_SZ) {
|
| ... | ... | |
| 873 | 803 |
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
|
| 874 | 804 |
if (ctx->fpscr & FPSCR_SZ) {
|
| 875 | 805 |
gen_op_fmov_drN_DT0(XREG(B7_4)); |
| 876 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
|
| 806 |
tcg_gen_mov_i32(cpu_T[1], REG(B11_8));
|
|
| 877 | 807 |
gen_op_stfq_DT0_T1(ctx); |
| 878 | 808 |
} else {
|
| 879 | 809 |
gen_op_fmov_frN_FT0(FREG(B7_4)); |
| 880 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
|
| 810 |
tcg_gen_mov_i32(cpu_T[1], REG(B11_8));
|
|
| 881 | 811 |
gen_op_stfl_FT0_T1(ctx); |
| 882 | 812 |
} |
| 883 | 813 |
return; |
| 884 | 814 |
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
|
| 885 | 815 |
if (ctx->fpscr & FPSCR_SZ) {
|
| 886 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
|
| 816 |
tcg_gen_mov_i32(cpu_T[0], REG(B7_4));
|
|
| 887 | 817 |
gen_op_ldfq_T0_DT0(ctx); |
| 888 | 818 |
gen_op_fmov_DT0_drN(XREG(B11_8)); |
| 889 | 819 |
} else {
|
| 890 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
|
| 820 |
tcg_gen_mov_i32(cpu_T[0], REG(B7_4));
|
|
| 891 | 821 |
gen_op_ldfl_T0_FT0(ctx); |
| 892 | 822 |
gen_op_fmov_FT0_frN(FREG(B11_8)); |
| 893 | 823 |
} |
| 894 | 824 |
return; |
| 895 | 825 |
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
|
| 896 | 826 |
if (ctx->fpscr & FPSCR_SZ) {
|
| 897 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
|
| 827 |
tcg_gen_mov_i32(cpu_T[0], REG(B7_4));
|
|
| 898 | 828 |
gen_op_ldfq_T0_DT0(ctx); |
| 899 | 829 |
gen_op_fmov_DT0_drN(XREG(B11_8)); |
| 900 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)],
|
|
| 901 |
cpu_gregs[REG(B7_4)], 8);
|
|
| 830 |
tcg_gen_addi_i32(REG(B7_4),
|
|
| 831 |
REG(B7_4), 8);
|
|
| 902 | 832 |
} else {
|
| 903 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
|
| 833 |
tcg_gen_mov_i32(cpu_T[0], REG(B7_4));
|
|
| 904 | 834 |
gen_op_ldfl_T0_FT0(ctx); |
| 905 | 835 |
gen_op_fmov_FT0_frN(FREG(B11_8)); |
| 906 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)],
|
|
| 907 |
cpu_gregs[REG(B7_4)], 4);
|
|
| 836 |
tcg_gen_addi_i32(REG(B7_4),
|
|
| 837 |
REG(B7_4), 4);
|
|
| 908 | 838 |
} |
| 909 | 839 |
return; |
| 910 | 840 |
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
|
| 911 | 841 |
if (ctx->fpscr & FPSCR_SZ) {
|
| 912 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 8);
|
|
| 842 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
|
|
| 913 | 843 |
gen_op_fmov_drN_DT0(XREG(B7_4)); |
| 914 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
|
| 915 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 8);
|
|
| 844 |
tcg_gen_mov_i32(cpu_T[1], REG(B11_8));
|
|
| 845 |
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 8);
|
|
| 916 | 846 |
gen_op_stfq_DT0_T1(ctx); |
| 917 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 8);
|
|
| 847 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
|
|
| 918 | 848 |
} else {
|
| 919 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
|
| 849 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
|
|
| 920 | 850 |
gen_op_fmov_frN_FT0(FREG(B7_4)); |
| 921 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
|
| 922 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
|
| 851 |
tcg_gen_mov_i32(cpu_T[1], REG(B11_8));
|
|
| 852 |
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
|
| 923 | 853 |
gen_op_stfl_FT0_T1(ctx); |
| 924 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
|
| 854 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
|
|
| 925 | 855 |
} |
| 926 | 856 |
return; |
| 927 | 857 |
case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
|
| 928 |
tcg_gen_add_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(0)]);
|
|
| 858 |
tcg_gen_add_i32(cpu_T[0], REG(B7_4), REG(0));
|
|
| 929 | 859 |
if (ctx->fpscr & FPSCR_SZ) {
|
| 930 | 860 |
gen_op_ldfq_T0_DT0(ctx); |
| 931 | 861 |
gen_op_fmov_DT0_drN(XREG(B11_8)); |
| ... | ... | |
| 937 | 867 |
case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
|
| 938 | 868 |
if (ctx->fpscr & FPSCR_SZ) {
|
| 939 | 869 |
gen_op_fmov_drN_DT0(XREG(B7_4)); |
| 940 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
|
| 941 |
tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]);
|
|
| 870 |
tcg_gen_mov_i32(cpu_T[1], REG(B11_8));
|
|
| 871 |
tcg_gen_add_i32(cpu_T[1], cpu_T[1], REG(0));
|
|
| 942 | 872 |
gen_op_stfq_DT0_T1(ctx); |
| 943 | 873 |
} else {
|
| 944 | 874 |
gen_op_fmov_frN_FT0(FREG(B7_4)); |
| 945 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
|
| 946 |
tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]);
|
|
| 875 |
tcg_gen_mov_i32(cpu_T[1], REG(B11_8));
|
|
| 876 |
tcg_gen_add_i32(cpu_T[1], cpu_T[1], REG(0));
|
|
| 947 | 877 |
gen_op_stfl_FT0_T1(ctx); |
| 948 | 878 |
} |
| 949 | 879 |
return; |
| ... | ... | |
| 996 | 926 |
|
| 997 | 927 |
switch (ctx->opcode & 0xff00) {
|
| 998 | 928 |
case 0xc900: /* and #imm,R0 */ |
| 999 |
tcg_gen_andi_i32(cpu_gregs[REG(0)], cpu_gregs[REG(0)], B7_0);
|
|
| 929 |
tcg_gen_andi_i32(REG(0), REG(0), B7_0);
|
|
| 1000 | 930 |
return; |
| 1001 | 931 |
case 0xcd00: /* and.b #imm,@(R0,GBR) */ |
| 1002 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
|
| 1003 |
tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr); |
|
| 1004 |
tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); |
|
| 1005 |
tcg_gen_qemu_ld8u(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 932 |
tcg_gen_add_i32(cpu_T[1], REG(0), cpu_gbr); |
|
| 933 |
tcg_gen_qemu_ld8u(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 1006 | 934 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], B7_0); |
| 1007 | 935 |
tcg_gen_qemu_st8(cpu_T[0], cpu_T[1], ctx->memidx); |
| 1008 | 936 |
return; |
| ... | ... | |
| 1029 | 957 |
ctx->flags |= DELAY_SLOT_CONDITIONAL; |
| 1030 | 958 |
return; |
| 1031 | 959 |
case 0x8800: /* cmp/eq #imm,R0 */ |
| 1032 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
|
| 1033 |
gen_cmp_imm(TCG_COND_EQ, cpu_T[0], B7_0s); |
|
| 960 |
gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s); |
|
| 1034 | 961 |
return; |
| 1035 | 962 |
case 0xc400: /* mov.b @(disp,GBR),R0 */ |
| 1036 | 963 |
tcg_gen_addi_i32(cpu_T[0], cpu_gbr, B7_0); |
| 1037 |
tcg_gen_qemu_ld8s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 1038 |
tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]); |
|
| 964 |
tcg_gen_qemu_ld8s(REG(0), cpu_T[0], ctx->memidx); |
|
| 1039 | 965 |
return; |
| 1040 | 966 |
case 0xc500: /* mov.w @(disp,GBR),R0 */ |
| 1041 | 967 |
tcg_gen_addi_i32(cpu_T[0], cpu_gbr, B7_0 * 2); |
| 1042 |
tcg_gen_qemu_ld16s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 1043 |
tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]); |
|
| 968 |
tcg_gen_qemu_ld16s(REG(0), cpu_T[0], ctx->memidx); |
|
| 1044 | 969 |
return; |
| 1045 | 970 |
case 0xc600: /* mov.l @(disp,GBR),R0 */ |
| 1046 | 971 |
tcg_gen_addi_i32(cpu_T[0], cpu_gbr, B7_0 * 4); |
| 1047 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 1048 |
tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]); |
|
| 972 |
tcg_gen_qemu_ld32s(REG(0), cpu_T[0], ctx->memidx); |
|
| 1049 | 973 |
return; |
| 1050 | 974 |
case 0xc000: /* mov.b R0,@(disp,GBR) */ |
| 1051 | 975 |
tcg_gen_addi_i32(cpu_T[0], cpu_gbr, B7_0); |
| 1052 |
tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); |
|
| 1053 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
|
| 1054 |
tcg_gen_qemu_st8(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 976 |
tcg_gen_qemu_st8(REG(0), cpu_T[0], ctx->memidx); |
|
| 1055 | 977 |
return; |
| 1056 | 978 |
case 0xc100: /* mov.w R0,@(disp,GBR) */ |
| 1057 | 979 |
tcg_gen_addi_i32(cpu_T[0], cpu_gbr, B7_0 * 2); |
| 1058 |
tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); |
|
| 1059 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
|
| 1060 |
tcg_gen_qemu_st16(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 980 |
tcg_gen_qemu_st16(REG(0), cpu_T[0], ctx->memidx); |
|
| 1061 | 981 |
return; |
| 1062 | 982 |
case 0xc200: /* mov.l R0,@(disp,GBR) */ |
| 1063 | 983 |
tcg_gen_addi_i32(cpu_T[0], cpu_gbr, B7_0 * 4); |
| 1064 |
tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); |
|
| 1065 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
|
| 1066 |
tcg_gen_qemu_st32(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 984 |
tcg_gen_qemu_st32(REG(0), cpu_T[0], ctx->memidx); |
|
| 1067 | 985 |
return; |
| 1068 | 986 |
case 0x8000: /* mov.b R0,@(disp,Rn) */ |
| 1069 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
|
| 1070 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B7_4)]); |
|
| 1071 |
tcg_gen_addi_i32(cpu_T[1], cpu_T[1], B3_0); |
|
| 1072 |
tcg_gen_qemu_st8(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 987 |
tcg_gen_addi_i32(cpu_T[0], REG(B7_4), B3_0); |
|
| 988 |
tcg_gen_qemu_st8(REG(0), cpu_T[0], ctx->memidx); |
|
| 1073 | 989 |
return; |
| 1074 | 990 |
case 0x8100: /* mov.w R0,@(disp,Rn) */ |
| 1075 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
|
| 1076 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B7_4)]); |
|
| 1077 |
tcg_gen_addi_i32(cpu_T[1], cpu_T[1], B3_0 * 2); |
|
| 1078 |
tcg_gen_qemu_st16(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 991 |
tcg_gen_addi_i32(cpu_T[0], REG(B7_4), B3_0 * 2); |
|
| 992 |
tcg_gen_qemu_st16(REG(0), cpu_T[0], ctx->memidx); |
|
| 1079 | 993 |
return; |
| 1080 | 994 |
case 0x8400: /* mov.b @(disp,Rn),R0 */ |
| 1081 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 1082 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B3_0); |
|
| 1083 |
tcg_gen_qemu_ld8s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 1084 |
tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]); |
|
| 995 |
tcg_gen_addi_i32(cpu_T[0], REG(B7_4), B3_0); |
|
| 996 |
tcg_gen_qemu_ld8s(REG(0), cpu_T[0], ctx->memidx); |
|
| 1085 | 997 |
return; |
| 1086 | 998 |
case 0x8500: /* mov.w @(disp,Rn),R0 */ |
| 1087 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 1088 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B3_0 * 2); |
|
| 1089 |
tcg_gen_qemu_ld16s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 1090 |
tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]); |
|
| 999 |
tcg_gen_addi_i32(cpu_T[0], REG(B7_4), B3_0 * 2); |
|
| 1000 |
tcg_gen_qemu_ld16s(REG(0), cpu_T[0], ctx->memidx); |
|
| 1091 | 1001 |
return; |
| 1092 | 1002 |
case 0xc700: /* mova @(disp,PC),R0 */ |
| 1093 |
tcg_gen_movi_i32(cpu_gregs[REG(0)], |
|
| 1094 |
((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3); |
|
| 1003 |
tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3); |
|
| 1095 | 1004 |
return; |
| 1096 | 1005 |
case 0xcb00: /* or #imm,R0 */ |
| 1097 |
tcg_gen_ori_i32(cpu_gregs[REG(0)], cpu_gregs[REG(0)], B7_0);
|
|
| 1006 |
tcg_gen_ori_i32(REG(0), REG(0), B7_0);
|
|
| 1098 | 1007 |
return; |
| 1099 | 1008 |
case 0xcf00: /* or.b #imm,@(R0,GBR) */ |
| 1100 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
|
| 1101 |
tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr); |
|
| 1102 |
tcg_gen_mov_i32(cpu_T[0], cpu_T[1]); |
|
| 1103 |
tcg_gen_qemu_ld8u(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 1009 |
tcg_gen_add_i32(cpu_T[1], REG(0), cpu_gbr); |
|
| 1010 |
tcg_gen_qemu_ld8u(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 1104 | 1011 |
tcg_gen_ori_i32(cpu_T[0], cpu_T[0], B7_0); |
| 1105 | 1012 |
tcg_gen_qemu_st8(cpu_T[0], cpu_T[1], ctx->memidx); |
| 1106 | 1013 |
return; |
| ... | ... | |
| 1112 | 1019 |
ctx->bstate = BS_BRANCH; |
| 1113 | 1020 |
return; |
| 1114 | 1021 |
case 0xc800: /* tst #imm,R0 */ |
| 1115 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(0)], B7_0);
|
|
| 1022 |
tcg_gen_andi_i32(cpu_T[0], REG(0), B7_0);
|
|
| 1116 | 1023 |
gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0); |
| 1117 | 1024 |
return; |
| 1118 | 1025 |
case 0xcc00: /* tst.b #imm,@(R0,GBR) */ |
| 1119 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
|
| 1120 |
tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr); |
|
| 1026 |
tcg_gen_add_i32(cpu_T[0], REG(0), cpu_gbr); |
|
| 1121 | 1027 |
tcg_gen_qemu_ld8u(cpu_T[0], cpu_T[0], ctx->memidx); |
| 1122 | 1028 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], B7_0); |
| 1123 | 1029 |
gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0); |
| 1124 | 1030 |
return; |
| 1125 | 1031 |
case 0xca00: /* xor #imm,R0 */ |
| 1126 |
tcg_gen_xori_i32(cpu_gregs[REG(0)], cpu_gregs[REG(0)], B7_0);
|
|
| 1032 |
tcg_gen_xori_i32(REG(0), REG(0), B7_0);
|
|
| 1127 | 1033 |
return; |
| 1128 | 1034 |
case 0xce00: /* xor.b #imm,@(R0,GBR) */ |
| 1129 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
|
| 1130 |
tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr); |
|
| 1131 |
tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); |
|
| 1132 |
tcg_gen_qemu_ld8u(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 1035 |
tcg_gen_add_i32(cpu_T[1], REG(0), cpu_gbr); |
|
| 1036 |
tcg_gen_qemu_ld8u(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 1133 | 1037 |
tcg_gen_xori_i32(cpu_T[0], cpu_T[0], B7_0); |
| 1134 | 1038 |
tcg_gen_qemu_st8(cpu_T[0], cpu_T[1], ctx->memidx); |
| 1135 | 1039 |
return; |
| ... | ... | |
| 1137 | 1041 |
|
| 1138 | 1042 |
switch (ctx->opcode & 0xf08f) {
|
| 1139 | 1043 |
case 0x408e: /* ldc Rm,Rn_BANK */ |
| 1140 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); |
|
| 1141 |
tcg_gen_mov_i32(cpu_gregs[ALTREG(B6_4)], cpu_T[0]); |
|
| 1044 |
tcg_gen_mov_i32(ALTREG(B6_4), REG(B11_8)); |
|
| 1142 | 1045 |
return; |
| 1143 | 1046 |
case 0x4087: /* ldc.l @Rm+,Rn_BANK */ |
| 1144 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); |
|
| 1145 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 1146 |
tcg_gen_mov_i32(cpu_gregs[ALTREG(B6_4)], cpu_T[0]); |
|
| 1147 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4); |
|
| 1047 |
tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx); |
|
| 1048 |
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); |
|
| 1148 | 1049 |
return; |
| 1149 | 1050 |
case 0x0082: /* stc Rm_BANK,Rn */ |
| 1150 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[ALTREG(B6_4)]); |
|
| 1151 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 1051 |
tcg_gen_mov_i32(REG(B11_8), ALTREG(B6_4)); |
|
| 1152 | 1052 |
return; |
| 1153 | 1053 |
case 0x4083: /* stc.l Rm_BANK,@-Rn */ |
| 1154 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4); |
|
| 1155 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 1156 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[ALTREG(B6_4)]); |
|
| 1157 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4); |
|
| 1158 |
tcg_gen_qemu_st32(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 1159 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4); |
|
| 1054 |
tcg_gen_subi_i32(cpu_T[0], REG(B11_8), 4); |
|
| 1055 |
tcg_gen_qemu_st32(ALTREG(B6_4), cpu_T[0], ctx->memidx); |
|
| 1056 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); |
|
| 1160 | 1057 |
return; |
| 1161 | 1058 |
} |
| 1162 | 1059 |
|
| 1163 | 1060 |
switch (ctx->opcode & 0xf0ff) {
|
| 1164 | 1061 |
case 0x0023: /* braf Rn */ |
| 1165 |
CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
|
| 1166 |
tcg_gen_addi_i32(cpu_delayed_pc, cpu_T[0], ctx->pc + 4);
|
|
| 1062 |
CHECK_NOT_DELAY_SLOT |
|
| 1063 |
tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4);
|
|
| 1167 | 1064 |
ctx->flags |= DELAY_SLOT; |
| 1168 | 1065 |
ctx->delayed_pc = (uint32_t) - 1; |
| 1169 | 1066 |
return; |
| 1170 | 1067 |
case 0x0003: /* bsrf Rn */ |
| 1171 |
CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
|
| 1068 |
CHECK_NOT_DELAY_SLOT |
|
| 1172 | 1069 |
tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); |
| 1173 |
tcg_gen_add_i32(cpu_delayed_pc, cpu_T[0], cpu_pr);
|
|
| 1070 |
tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr);
|
|
| 1174 | 1071 |
ctx->flags |= DELAY_SLOT; |
| 1175 | 1072 |
ctx->delayed_pc = (uint32_t) - 1; |
| 1176 | 1073 |
return; |
| 1177 | 1074 |
case 0x4015: /* cmp/pl Rn */ |
| 1178 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); |
|
| 1179 |
gen_cmp_imm(TCG_COND_GT, cpu_T[0], 0); |
|
| 1075 |
gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0); |
|
| 1180 | 1076 |
return; |
| 1181 | 1077 |
case 0x4011: /* cmp/pz Rn */ |
| 1182 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); |
|
| 1183 |
gen_cmp_imm(TCG_COND_GE, cpu_T[0], 0); |
|
| 1078 |
gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0); |
|
| 1184 | 1079 |
return; |
| 1185 | 1080 |
case 0x4010: /* dt Rn */ |
| 1186 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1);
|
|
| 1187 |
gen_cmp_imm(TCG_COND_EQ, cpu_gregs[REG(B11_8)], 0);
|
|
| 1081 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);
|
|
| 1082 |
gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0);
|
|
| 1188 | 1083 |
return; |
| 1189 | 1084 |
case 0x402b: /* jmp @Rn */ |
| 1190 |
CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
|
| 1191 |
tcg_gen_mov_i32(cpu_delayed_pc, cpu_T[0]);
|
|
| 1085 |
CHECK_NOT_DELAY_SLOT |
|
| 1086 |
tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
|
|
| 1192 | 1087 |
ctx->flags |= DELAY_SLOT; |
| 1193 | 1088 |
ctx->delayed_pc = (uint32_t) - 1; |
| 1194 | 1089 |
return; |
| 1195 | 1090 |
case 0x400b: /* jsr @Rn */ |
| 1196 |
CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
|
| 1091 |
CHECK_NOT_DELAY_SLOT |
|
| 1197 | 1092 |
tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); |
| 1198 |
tcg_gen_mov_i32(cpu_delayed_pc, cpu_T[0]);
|
|
| 1093 |
tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
|
|
| 1199 | 1094 |
ctx->flags |= DELAY_SLOT; |
| 1200 | 1095 |
ctx->delayed_pc = (uint32_t) - 1; |
| 1201 | 1096 |
return; |
| 1202 | 1097 |
case 0x400e: /* lds Rm,SR */ |
| 1203 |
tcg_gen_andi_i32(cpu_sr, cpu_gregs[REG(B11_8)], 0x700083f3);
|
|
| 1098 |
tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3);
|
|
| 1204 | 1099 |
ctx->bstate = BS_STOP; |
| 1205 | 1100 |
return; |
| 1206 | 1101 |
case 0x4007: /* lds.l @Rm+,SR */ |
| 1207 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_gregs[REG(B11_8)], ctx->memidx);
|
|
| 1208 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
|
| 1102 |
tcg_gen_qemu_ld32s(cpu_T[0], REG(B11_8), ctx->memidx);
|
|
| 1103 |
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
|
| 1209 | 1104 |
tcg_gen_andi_i32(cpu_sr, cpu_T[0], 0x700083f3); |
| 1210 | 1105 |
ctx->bstate = BS_STOP; |
| 1211 | 1106 |
return; |
| 1212 | 1107 |
case 0x0002: /* sts SR,Rn */ |
| 1213 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_sr);
|
|
| 1108 |
tcg_gen_mov_i32(REG(B11_8), cpu_sr);
|
|
| 1214 | 1109 |
return; |
| 1215 | 1110 |
case 0x4003: /* sts SR,@-Rn */ |
| 1216 |
tcg_gen_subi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 4);
|
|
| 1111 |
tcg_gen_subi_i32(cpu_T[0], REG(B11_8), 4);
|
|
| 1217 | 1112 |
tcg_gen_qemu_st32(cpu_sr, cpu_T[0], ctx->memidx); |
| 1218 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
|
| 1113 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
|
|
| 1219 | 1114 |
return; |
| 1220 | 1115 |
#define LDST(reg,ldnum,ldpnum,stnum,stpnum) \ |
| 1221 | 1116 |
case ldnum: \ |
| 1222 |
tcg_gen_mov_i32 (cpu_##reg, cpu_gregs[REG(B11_8)]); \
|
|
| 1117 |
tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \
|
|
| 1223 | 1118 |
return; \ |
| 1224 | 1119 |
case ldpnum: \ |
| 1225 |
tcg_gen_qemu_ld32s (cpu_##reg, cpu_gregs[REG(B11_8)], ctx->memidx); \ |
|
| 1226 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], \ |
|
| 1227 |
cpu_gregs[REG(B11_8)], 4); \ |
|
| 1120 |
tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \ |
|
| 1121 |
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \ |
|
| 1228 | 1122 |
return; \ |
| 1229 | 1123 |
case stnum: \ |
| 1230 |
tcg_gen_mov_i32 (cpu_gregs[REG(B11_8)], cpu_##reg); \
|
|
| 1124 |
tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \
|
|
| 1231 | 1125 |
return; \ |
| 1232 | 1126 |
case stpnum: \ |
| 1233 |
tcg_gen_subi_i32(cpu_T[1], cpu_gregs[REG(B11_8)], 4); \ |
|
| 1234 |
tcg_gen_qemu_st32 (cpu_##reg, cpu_T[1], ctx->memidx); \ |
|
| 1235 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], \ |
|
| 1236 |
cpu_gregs[REG(B11_8)], 4); \ |
|
| 1127 |
tcg_gen_subi_i32(cpu_T[0], REG(B11_8), 4); \ |
|
| 1128 |
tcg_gen_qemu_st32 (cpu_##reg, cpu_T[0], ctx->memidx); \ |
|
| 1129 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); \ |
|
| 1237 | 1130 |
return; |
| 1238 | 1131 |
LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013) |
| 1239 | 1132 |
LDST(vbr, 0x402e, 0x4027, 0x0022, 0x4023) |
| ... | ... | |
| 1245 | 1138 |
LDST(pr, 0x402a, 0x4026, 0x002a, 0x4022) |
| 1246 | 1139 |
LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052) |
| 1247 | 1140 |
case 0x406a: /* lds Rm,FPSCR */ |
| 1248 |
tcg_gen_helper_0_1(helper_ld_fpscr, cpu_gregs[REG(B11_8)]);
|
|
| 1141 |
tcg_gen_helper_0_1(helper_ld_fpscr, REG(B11_8));
|
|
| 1249 | 1142 |
ctx->bstate = BS_STOP; |
| 1250 | 1143 |
return; |
| 1251 | 1144 |
case 0x4066: /* lds.l @Rm+,FPSCR */ |
| 1252 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_gregs[REG(B11_8)], ctx->memidx);
|
|
| 1253 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
|
| 1145 |
tcg_gen_qemu_ld32s(cpu_T[0], REG(B11_8), ctx->memidx);
|
|
| 1146 |
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
|
| 1254 | 1147 |
tcg_gen_helper_0_1(helper_ld_fpscr, cpu_T[0]); |
| 1255 | 1148 |
ctx->bstate = BS_STOP; |
| 1256 | 1149 |
return; |
| 1257 | 1150 |
case 0x006a: /* sts FPSCR,Rn */ |
| 1258 | 1151 |
tcg_gen_andi_i32(cpu_T[0], cpu_fpscr, 0x003fffff); |
| 1259 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
|
| 1152 |
tcg_gen_mov_i32(REG(B11_8), cpu_T[0]);
|
|
| 1260 | 1153 |
return; |
| 1261 | 1154 |
case 0x4062: /* sts FPSCR,@-Rn */ |
| 1262 | 1155 |
tcg_gen_andi_i32(cpu_T[0], cpu_fpscr, 0x003fffff); |
| 1263 |
tcg_gen_subi_i32(cpu_T[1], cpu_gregs[REG(B11_8)], 4);
|
|
| 1156 |
tcg_gen_subi_i32(cpu_T[1], REG(B11_8), 4);
|
|
| 1264 | 1157 |
tcg_gen_qemu_st32(cpu_T[0], cpu_T[1], ctx->memidx); |
| 1265 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
|
| 1158 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
|
|
| 1266 | 1159 |
return; |
| 1267 | 1160 |
case 0x00c3: /* movca.l R0,@Rm */ |
| 1268 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
|
| 1269 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 1270 |
tcg_gen_qemu_st32(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 1161 |
tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx); |
|
| 1271 | 1162 |
return; |
| 1272 | 1163 |
case 0x0029: /* movt Rn */ |
| 1273 |
tcg_gen_andi_i32(cpu_gregs[REG(B11_8)], cpu_sr, SR_T);
|
|
| 1164 |
tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T);
|
|
| 1274 | 1165 |
return; |
| 1275 | 1166 |
case 0x0093: /* ocbi @Rn */ |
| 1276 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); |
|
| 1277 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 1167 |
tcg_gen_qemu_ld32s(cpu_T[0], REG(B11_8), ctx->memidx); |
|
| 1278 | 1168 |
return; |
| 1279 | 1169 |
case 0x00a3: /* ocbp @Rn */ |
| 1280 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); |
|
| 1281 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 1170 |
tcg_gen_qemu_ld32s(cpu_T[0], REG(B11_8), ctx->memidx); |
|
| 1282 | 1171 |
return; |
| 1283 | 1172 |
case 0x00b3: /* ocbwb @Rn */ |
| 1284 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); |
|
| 1285 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 1173 |
tcg_gen_qemu_ld32s(cpu_T[0], REG(B11_8), ctx->memidx); |
|
| 1286 | 1174 |
return; |
| 1287 | 1175 |
case 0x0083: /* pref @Rn */ |
| 1288 | 1176 |
return; |
| 1289 | 1177 |
case 0x4024: /* rotcl Rn */ |
| 1290 | 1178 |
tcg_gen_mov_i32(cpu_T[0], cpu_sr); |
| 1291 |
gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 31);
|
|
| 1292 |
tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1);
|
|
| 1293 |
gen_copy_bit_i32(cpu_gregs[REG(B11_8)], 0, cpu_T[0], 0);
|
|
| 1179 |
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
|
|
| 1180 |
tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
|
|
| 1181 |
gen_copy_bit_i32(REG(B11_8), 0, cpu_T[0], 0);
|
|
| 1294 | 1182 |
return; |
| 1295 | 1183 |
case 0x4025: /* rotcr Rn */ |
| 1296 | 1184 |
tcg_gen_mov_i32(cpu_T[0], cpu_sr); |
| 1297 |
gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 0);
|
|
| 1298 |
tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1);
|
|
| 1299 |
gen_copy_bit_i32(cpu_gregs[REG(B11_8)], 31, cpu_T[0], 0);
|
|
| 1185 |
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
|
|
| 1186 |
tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
|
|
| 1187 |
gen_copy_bit_i32(REG(B11_8), 31, cpu_T[0], 0);
|
|
| 1300 | 1188 |
return; |
| 1301 | 1189 |
case 0x4004: /* rotl Rn */ |
| 1302 |
gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 31);
|
|
| 1303 |
tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1);
|
|
| 1304 |
gen_copy_bit_i32(cpu_gregs[REG(B11_8)], 0, cpu_sr, 0);
|
|
| 1190 |
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
|
|
| 1191 |
tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
|
|
| 1192 |
gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0);
|
|
| 1305 | 1193 |
return; |
| 1306 | 1194 |
case 0x4005: /* rotr Rn */ |
| 1307 |
gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 0);
|
|
| 1308 |
tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1);
|
|
| 1309 |
gen_copy_bit_i32(cpu_gregs[REG(B11_8)], 31, cpu_sr, 0);
|
|
| 1195 |
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
|
|
| 1196 |
tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
|
|
| 1197 |
gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0);
|
|
| 1310 | 1198 |
return; |
| 1311 | 1199 |
case 0x4000: /* shll Rn */ |
| 1312 | 1200 |
case 0x4020: /* shal Rn */ |
| 1313 |
gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 31);
|
|
| 1314 |
tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1);
|
|
| 1201 |
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
|
|
| 1202 |
tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
|
|
| 1315 | 1203 |
return; |
| 1316 | 1204 |
case 0x4021: /* shar Rn */ |
| 1317 |
gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 0);
|
|
| 1318 |
tcg_gen_sari_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1);
|
|
| 1205 |
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
|
|
| 1206 |
tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1);
|
|
| 1319 | 1207 |
return; |
| 1320 | 1208 |
case 0x4001: /* shlr Rn */ |
| 1321 |
gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 0);
|
|
| 1322 |
tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1);
|
|
| 1209 |
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
|
|
| 1210 |
tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
|
|
| 1323 | 1211 |
return; |
| 1324 | 1212 |
case 0x4008: /* shll2 Rn */ |
| 1325 |
tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 2);
|
|
| 1213 |
tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 2);
|
|
| 1326 | 1214 |
return; |
| 1327 | 1215 |
case 0x4018: /* shll8 Rn */ |
| 1328 |
tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 8);
|
|
| 1216 |
tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 8);
|
|
| 1329 | 1217 |
return; |
| 1330 | 1218 |
case 0x4028: /* shll16 Rn */ |
| 1331 |
tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 16);
|
|
| 1219 |
tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 16);
|
|
| 1332 | 1220 |
return; |
| 1333 | 1221 |
case 0x4009: /* shlr2 Rn */ |
| 1334 |
tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 2);
|
|
| 1222 |
tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 2);
|
|
| 1335 | 1223 |
return; |
| 1336 | 1224 |
case 0x4019: /* shlr8 Rn */ |
| 1337 |
tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 8);
|
|
| 1225 |
tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 8);
|
|
| 1338 | 1226 |
return; |
| 1339 | 1227 |
case 0x4029: /* shlr16 Rn */ |
| 1340 |
tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 16);
|
|
| 1228 |
tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
|
|
| 1341 | 1229 |
return; |
| 1342 | 1230 |
case 0x401b: /* tas.b @Rn */ |
| 1343 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); |
|
| 1344 |
tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); |
|
| 1345 |
tcg_gen_qemu_ld8u(cpu_T[0], cpu_T[0], ctx->memidx); |
|
| 1231 |
tcg_gen_mov_i32(cpu_T[1], REG(B11_8)); |
|
| 1232 |
tcg_gen_qemu_ld8u(cpu_T[0], cpu_T[1], ctx->memidx); |
|
| 1346 | 1233 |
gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0); |
| 1347 | 1234 |
tcg_gen_ori_i32(cpu_T[0], cpu_T[0], 0x80); |
| 1348 | 1235 |
tcg_gen_qemu_st8(cpu_T[0], cpu_T[1], ctx->memidx); |
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