Revision 7f5b7d3e

b/hw/acpi.c
88 88
static int get_pmsts(PIIX4PMState *s)
89 89
{
90 90
    int64_t d;
91
    int pmsts;
92
    pmsts = s->pmsts;
91

  
93 92
    d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec());
94 93
    if (d >= s->tmr_overflow_time)
95 94
        s->pmsts |= TMROF_EN;
......
206 205
static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
207 206
{
208 207
    //    PIIX4PMState *s = opaque;
209
    addr &= 0x3f;
210 208
#ifdef DEBUG
209
    addr &= 0x3f;
211 210
    printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
212 211
#endif
213 212
}
b/hw/i8259.c
234 234
                irq2 = 7;
235 235
            }
236 236
            intno = s->pics[1].irq_base + irq2;
237
#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
237 238
            irq = irq2 + 8;
239
#endif
238 240
        } else {
239 241
            intno = s->pics[0].irq_base + irq;
240 242
        }
b/hw/parallel.c
414 414

  
415 415
static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
416 416
{
417
    addr &= 7;
418
    pdebug("wecp%d=%02x\n", addr, val);
417
    pdebug("wecp%d=%02x\n", addr & 7, val);
419 418
}
420 419

  
421 420
static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
422 421
{
423 422
    uint8_t ret = 0xff;
424
    addr &= 7;
425
    pdebug("recp%d:%02x\n", addr, ret);
423

  
424
    pdebug("recp%d:%02x\n", addr & 7, ret);
426 425
    return ret;
427 426
}
428 427

  
b/hw/pc.c
813 813
    ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
814 814
    int bios_size, isa_bios_size;
815 815
    PCIBus *pci_bus;
816
    ISADevice *isa_dev;
817 816
    int piix3_devfn = -1;
818
    CPUState *env;
819 817
    qemu_irq *cpu_irq;
820 818
    qemu_irq *isa_irq;
821 819
    qemu_irq *i8259;
......
845 843
    }
846 844

  
847 845
    for (i = 0; i < smp_cpus; i++) {
848
        env = pc_new_cpu(cpu_model);
846
        pc_new_cpu(cpu_model);
849 847
    }
850 848

  
851 849
    vmport_init();
......
1014 1012
        }
1015 1013
    }
1016 1014

  
1017
    isa_dev = isa_create_simple("i8042");
1015
    isa_create_simple("i8042");
1018 1016
    DMA_init(0);
1019 1017
#ifdef HAS_AUDIO
1020 1018
    audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
b/hw/pci-hotplug.c
105 105
{
106 106
    int dom, pci_bus;
107 107
    unsigned slot;
108
    int type, bus;
108
    int type;
109 109
    PCIDevice *dev;
110 110
    DriveInfo *dinfo = NULL;
111 111
    const char *pci_addr = qdict_get_str(qdict, "pci_addr");
......
119 119
        goto err;
120 120
    }
121 121
    type = dinfo->type;
122
    bus = drive_get_max_bus (type);
123 122

  
124 123
    switch (type) {
125 124
    case IF_SCSI:
b/hw/vga.c
169 169
    int vretr_start_line;
170 170
    int vretr_end_line;
171 171

  
172
    int div2, sldiv2, dots;
172
    int dots;
173
#if 0
174
    int div2, sldiv2;
175
#endif
173 176
    int clocking_mode;
174 177
    int clock_sel;
175 178
    const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
......
190 193
    vretr_end_line = s->cr[0x11] & 0xf;
191 194

  
192 195

  
193
    div2 = (s->cr[0x17] >> 2) & 1;
194
    sldiv2 = (s->cr[0x17] >> 3) & 1;
195 196

  
196 197
    clocking_mode = (s->sr[0x01] >> 3) & 1;
197 198
    clock_sel = (s->msr >> 2) & 3;
......
216 217
    r->htotal = htotal_chars;
217 218

  
218 219
#if 0
220
    div2 = (s->cr[0x17] >> 2) & 1;
221
    sldiv2 = (s->cr[0x17] >> 3) & 1;
219 222
    printf (
220 223
        "hz=%f\n"
221 224
        "htotal = %d\n"
b/target-i386/translate.c
763 763
            if (s->cc_op != CC_OP_DYNAMIC)
764 764
                gen_op_set_cc_op(s->cc_op);
765 765
            gen_jmp_im(cur_eip);
766
            state_saved = 1;
767 766
        }
768 767
        svm_flags |= (1 << (4 + ot));
769 768
        next_eip = s->pc - s->cs_base;
......
7744 7743
    target_ulong pc_ptr;
7745 7744
    uint16_t *gen_opc_end;
7746 7745
    CPUBreakpoint *bp;
7747
    int j, lj, cflags;
7746
    int j, lj;
7748 7747
    uint64_t flags;
7749 7748
    target_ulong pc_start;
7750 7749
    target_ulong cs_base;
......
7755 7754
    pc_start = tb->pc;
7756 7755
    cs_base = tb->cs_base;
7757 7756
    flags = tb->flags;
7758
    cflags = tb->cflags;
7759 7757

  
7760 7758
    dc->pe = (flags >> HF_PE_SHIFT) & 1;
7761 7759
    dc->code32 = (flags >> HF_CS32_SHIFT) & 1;

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