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1 | 69b91039 | bellard | /*
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2 | 69b91039 | bellard | * QEMU PCI bus manager
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3 | 69b91039 | bellard | *
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4 | 69b91039 | bellard | * Copyright (c) 2004 Fabrice Bellard
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5 | 69b91039 | bellard | *
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6 | 69b91039 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 69b91039 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 69b91039 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 69b91039 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 69b91039 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 69b91039 | bellard | * furnished to do so, subject to the following conditions:
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12 | 69b91039 | bellard | *
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13 | 69b91039 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 69b91039 | bellard | * all copies or substantial portions of the Software.
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15 | 69b91039 | bellard | *
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16 | 69b91039 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 69b91039 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 69b91039 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 69b91039 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 69b91039 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 69b91039 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 69b91039 | bellard | * THE SOFTWARE.
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23 | 69b91039 | bellard | */
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24 | 69b91039 | bellard | #include "vl.h" |
25 | 69b91039 | bellard | |
26 | 69b91039 | bellard | //#define DEBUG_PCI
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27 | 69b91039 | bellard | |
28 | 0ac32c83 | bellard | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
29 | 0ac32c83 | bellard | #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
30 | 0ac32c83 | bellard | #define PCI_COMMAND 0x04 /* 16 bits */ |
31 | 0ac32c83 | bellard | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
32 | 0ac32c83 | bellard | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
33 | 0ac32c83 | bellard | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
34 | 0ac32c83 | bellard | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
35 | 0ac32c83 | bellard | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
36 | 0ac32c83 | bellard | #define PCI_MIN_GNT 0x3e /* 8 bits */ |
37 | 0ac32c83 | bellard | #define PCI_MAX_LAT 0x3f /* 8 bits */ |
38 | 0ac32c83 | bellard | |
39 | 0ac32c83 | bellard | /* just used for simpler irq handling. */
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40 | 0ac32c83 | bellard | #define PCI_DEVICES_MAX 64 |
41 | 0ac32c83 | bellard | #define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32) |
42 | 0ac32c83 | bellard | |
43 | 69b91039 | bellard | typedef struct PCIBridge { |
44 | 69b91039 | bellard | uint32_t config_reg; |
45 | 69b91039 | bellard | PCIDevice **pci_bus[256];
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46 | 69b91039 | bellard | } PCIBridge; |
47 | 69b91039 | bellard | |
48 | 69b91039 | bellard | static PCIBridge pci_bridge;
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49 | 69b91039 | bellard | target_phys_addr_t pci_mem_base; |
50 | 0ac32c83 | bellard | static int pci_irq_index; |
51 | 0ac32c83 | bellard | static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS]; |
52 | 69b91039 | bellard | |
53 | 69b91039 | bellard | /* -1 for devfn means auto assign */
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54 | 69b91039 | bellard | PCIDevice *pci_register_device(const char *name, int instance_size, |
55 | 69b91039 | bellard | int bus_num, int devfn, |
56 | 69b91039 | bellard | PCIConfigReadFunc *config_read, |
57 | 69b91039 | bellard | PCIConfigWriteFunc *config_write) |
58 | 69b91039 | bellard | { |
59 | 69b91039 | bellard | PCIBridge *s = &pci_bridge; |
60 | 69b91039 | bellard | PCIDevice *pci_dev, **bus; |
61 | 69b91039 | bellard | |
62 | 0ac32c83 | bellard | if (pci_irq_index >= PCI_DEVICES_MAX)
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63 | 0ac32c83 | bellard | return NULL; |
64 | 0ac32c83 | bellard | |
65 | 69b91039 | bellard | if (!s->pci_bus[bus_num]) {
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66 | 69b91039 | bellard | s->pci_bus[bus_num] = qemu_mallocz(256 * sizeof(PCIDevice *)); |
67 | 69b91039 | bellard | if (!s->pci_bus[bus_num])
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68 | 69b91039 | bellard | return NULL; |
69 | 69b91039 | bellard | } |
70 | 69b91039 | bellard | bus = s->pci_bus[bus_num]; |
71 | 69b91039 | bellard | if (devfn < 0) { |
72 | 69b91039 | bellard | for(devfn = 0 ; devfn < 256; devfn += 8) { |
73 | 69b91039 | bellard | if (!bus[devfn])
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74 | 69b91039 | bellard | goto found;
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75 | 69b91039 | bellard | } |
76 | 69b91039 | bellard | return NULL; |
77 | 69b91039 | bellard | found: ;
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78 | 69b91039 | bellard | } |
79 | 69b91039 | bellard | pci_dev = qemu_mallocz(instance_size); |
80 | 69b91039 | bellard | if (!pci_dev)
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81 | 69b91039 | bellard | return NULL; |
82 | 69b91039 | bellard | pci_dev->bus_num = bus_num; |
83 | 69b91039 | bellard | pci_dev->devfn = devfn; |
84 | 69b91039 | bellard | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
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85 | 0ac32c83 | bellard | |
86 | 0ac32c83 | bellard | if (!config_read)
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87 | 0ac32c83 | bellard | config_read = pci_default_read_config; |
88 | 0ac32c83 | bellard | if (!config_write)
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89 | 0ac32c83 | bellard | config_write = pci_default_write_config; |
90 | 69b91039 | bellard | pci_dev->config_read = config_read; |
91 | 69b91039 | bellard | pci_dev->config_write = config_write; |
92 | 0ac32c83 | bellard | pci_dev->irq_index = pci_irq_index++; |
93 | 69b91039 | bellard | bus[devfn] = pci_dev; |
94 | 69b91039 | bellard | return pci_dev;
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95 | 69b91039 | bellard | } |
96 | 69b91039 | bellard | |
97 | 69b91039 | bellard | void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
98 | 69b91039 | bellard | uint32_t size, int type,
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99 | 69b91039 | bellard | PCIMapIORegionFunc *map_func) |
100 | 69b91039 | bellard | { |
101 | 69b91039 | bellard | PCIIORegion *r; |
102 | 69b91039 | bellard | |
103 | 8a8696a3 | bellard | if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
104 | 69b91039 | bellard | return;
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105 | 69b91039 | bellard | r = &pci_dev->io_regions[region_num]; |
106 | 69b91039 | bellard | r->addr = -1;
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107 | 69b91039 | bellard | r->size = size; |
108 | 69b91039 | bellard | r->type = type; |
109 | 69b91039 | bellard | r->map_func = map_func; |
110 | 69b91039 | bellard | } |
111 | 69b91039 | bellard | |
112 | 0ac32c83 | bellard | static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val) |
113 | 69b91039 | bellard | { |
114 | 69b91039 | bellard | PCIBridge *s = opaque; |
115 | 69b91039 | bellard | s->config_reg = val; |
116 | 69b91039 | bellard | } |
117 | 69b91039 | bellard | |
118 | 0ac32c83 | bellard | static uint32_t pci_addr_readl(void* opaque, uint32_t addr) |
119 | 69b91039 | bellard | { |
120 | 69b91039 | bellard | PCIBridge *s = opaque; |
121 | 69b91039 | bellard | return s->config_reg;
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122 | 69b91039 | bellard | } |
123 | 69b91039 | bellard | |
124 | 0ac32c83 | bellard | static void pci_update_mappings(PCIDevice *d) |
125 | 0ac32c83 | bellard | { |
126 | 0ac32c83 | bellard | PCIIORegion *r; |
127 | 0ac32c83 | bellard | int cmd, i;
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128 | 8a8696a3 | bellard | uint32_t last_addr, new_addr, config_ofs; |
129 | 0ac32c83 | bellard | |
130 | 0ac32c83 | bellard | cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
131 | 8a8696a3 | bellard | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
132 | 0ac32c83 | bellard | r = &d->io_regions[i]; |
133 | 8a8696a3 | bellard | if (i == PCI_ROM_SLOT) {
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134 | 8a8696a3 | bellard | config_ofs = 0x30;
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135 | 8a8696a3 | bellard | } else {
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136 | 8a8696a3 | bellard | config_ofs = 0x10 + i * 4; |
137 | 8a8696a3 | bellard | } |
138 | 0ac32c83 | bellard | if (r->size != 0) { |
139 | 0ac32c83 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO) {
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140 | 0ac32c83 | bellard | if (cmd & PCI_COMMAND_IO) {
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141 | 0ac32c83 | bellard | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
142 | 8a8696a3 | bellard | config_ofs)); |
143 | 0ac32c83 | bellard | new_addr = new_addr & ~(r->size - 1);
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144 | 0ac32c83 | bellard | last_addr = new_addr + r->size - 1;
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145 | 0ac32c83 | bellard | /* NOTE: we have only 64K ioports on PC */
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146 | 0ac32c83 | bellard | if (last_addr <= new_addr || new_addr == 0 || |
147 | 0ac32c83 | bellard | last_addr >= 0x10000) {
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148 | 0ac32c83 | bellard | new_addr = -1;
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149 | 0ac32c83 | bellard | } |
150 | 0ac32c83 | bellard | } else {
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151 | 0ac32c83 | bellard | new_addr = -1;
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152 | 0ac32c83 | bellard | } |
153 | 0ac32c83 | bellard | } else {
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154 | 0ac32c83 | bellard | if (cmd & PCI_COMMAND_MEMORY) {
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155 | 0ac32c83 | bellard | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
156 | 8a8696a3 | bellard | config_ofs)); |
157 | 8a8696a3 | bellard | /* the ROM slot has a specific enable bit */
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158 | 8a8696a3 | bellard | if (i == PCI_ROM_SLOT && !(new_addr & 1)) |
159 | 8a8696a3 | bellard | goto no_mem_map;
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160 | 0ac32c83 | bellard | new_addr = new_addr & ~(r->size - 1);
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161 | 0ac32c83 | bellard | last_addr = new_addr + r->size - 1;
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162 | 0ac32c83 | bellard | /* NOTE: we do not support wrapping */
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163 | 0ac32c83 | bellard | /* XXX: as we cannot support really dynamic
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164 | 0ac32c83 | bellard | mappings, we handle specific values as invalid
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165 | 0ac32c83 | bellard | mappings. */
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166 | 0ac32c83 | bellard | if (last_addr <= new_addr || new_addr == 0 || |
167 | 0ac32c83 | bellard | last_addr == -1) {
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168 | 0ac32c83 | bellard | new_addr = -1;
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169 | 0ac32c83 | bellard | } |
170 | 0ac32c83 | bellard | } else {
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171 | 8a8696a3 | bellard | no_mem_map:
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172 | 0ac32c83 | bellard | new_addr = -1;
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173 | 0ac32c83 | bellard | } |
174 | 0ac32c83 | bellard | } |
175 | 0ac32c83 | bellard | /* now do the real mapping */
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176 | 0ac32c83 | bellard | if (new_addr != r->addr) {
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177 | 0ac32c83 | bellard | if (r->addr != -1) { |
178 | 0ac32c83 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO) {
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179 | 0ac32c83 | bellard | int class;
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180 | 0ac32c83 | bellard | /* NOTE: specific hack for IDE in PC case:
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181 | 0ac32c83 | bellard | only one byte must be mapped. */
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182 | 0ac32c83 | bellard | class = d->config[0x0a] | (d->config[0x0b] << 8); |
183 | 0ac32c83 | bellard | if (class == 0x0101 && r->size == 4) { |
184 | 0ac32c83 | bellard | isa_unassign_ioport(r->addr + 2, 1); |
185 | 0ac32c83 | bellard | } else {
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186 | 0ac32c83 | bellard | isa_unassign_ioport(r->addr, r->size); |
187 | 0ac32c83 | bellard | } |
188 | 0ac32c83 | bellard | } else {
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189 | 0ac32c83 | bellard | cpu_register_physical_memory(r->addr + pci_mem_base, |
190 | 0ac32c83 | bellard | r->size, |
191 | 0ac32c83 | bellard | IO_MEM_UNASSIGNED); |
192 | 0ac32c83 | bellard | } |
193 | 0ac32c83 | bellard | } |
194 | 0ac32c83 | bellard | r->addr = new_addr; |
195 | 0ac32c83 | bellard | if (r->addr != -1) { |
196 | 0ac32c83 | bellard | r->map_func(d, i, r->addr, r->size, r->type); |
197 | 0ac32c83 | bellard | } |
198 | 0ac32c83 | bellard | } |
199 | 0ac32c83 | bellard | } |
200 | 0ac32c83 | bellard | } |
201 | 0ac32c83 | bellard | } |
202 | 0ac32c83 | bellard | |
203 | 0ac32c83 | bellard | uint32_t pci_default_read_config(PCIDevice *d, |
204 | 0ac32c83 | bellard | uint32_t address, int len)
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205 | 69b91039 | bellard | { |
206 | 0ac32c83 | bellard | uint32_t val; |
207 | 0ac32c83 | bellard | switch(len) {
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208 | 0ac32c83 | bellard | case 1: |
209 | 0ac32c83 | bellard | val = d->config[address]; |
210 | 0ac32c83 | bellard | break;
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211 | 0ac32c83 | bellard | case 2: |
212 | 0ac32c83 | bellard | val = le16_to_cpu(*(uint16_t *)(d->config + address)); |
213 | 0ac32c83 | bellard | break;
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214 | 0ac32c83 | bellard | default:
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215 | 0ac32c83 | bellard | case 4: |
216 | 0ac32c83 | bellard | val = le32_to_cpu(*(uint32_t *)(d->config + address)); |
217 | 0ac32c83 | bellard | break;
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218 | 0ac32c83 | bellard | } |
219 | 0ac32c83 | bellard | return val;
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220 | 0ac32c83 | bellard | } |
221 | 0ac32c83 | bellard | |
222 | 0ac32c83 | bellard | void pci_default_write_config(PCIDevice *d,
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223 | 0ac32c83 | bellard | uint32_t address, uint32_t val, int len)
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224 | 0ac32c83 | bellard | { |
225 | 0ac32c83 | bellard | int can_write, i;
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226 | 7bf5be70 | bellard | uint32_t end, addr; |
227 | 0ac32c83 | bellard | |
228 | 8a8696a3 | bellard | if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) || |
229 | 8a8696a3 | bellard | (address >= 0x30 && address < 0x34))) { |
230 | 0ac32c83 | bellard | PCIIORegion *r; |
231 | 0ac32c83 | bellard | int reg;
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232 | 0ac32c83 | bellard | |
233 | 8a8696a3 | bellard | if ( address >= 0x30 ) { |
234 | 8a8696a3 | bellard | reg = PCI_ROM_SLOT; |
235 | 8a8696a3 | bellard | }else{
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236 | 8a8696a3 | bellard | reg = (address - 0x10) >> 2; |
237 | 8a8696a3 | bellard | } |
238 | 0ac32c83 | bellard | r = &d->io_regions[reg]; |
239 | 0ac32c83 | bellard | if (r->size == 0) |
240 | 0ac32c83 | bellard | goto default_config;
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241 | 0ac32c83 | bellard | /* compute the stored value */
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242 | 8a8696a3 | bellard | if (reg == PCI_ROM_SLOT) {
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243 | 8a8696a3 | bellard | /* keep ROM enable bit */
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244 | 8a8696a3 | bellard | val &= (~(r->size - 1)) | 1; |
245 | 8a8696a3 | bellard | } else {
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246 | 8a8696a3 | bellard | val &= ~(r->size - 1);
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247 | 8a8696a3 | bellard | val |= r->type; |
248 | 8a8696a3 | bellard | } |
249 | 8a8696a3 | bellard | *(uint32_t *)(d->config + address) = cpu_to_le32(val); |
250 | 0ac32c83 | bellard | pci_update_mappings(d); |
251 | 69b91039 | bellard | return;
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252 | 0ac32c83 | bellard | } |
253 | 0ac32c83 | bellard | default_config:
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254 | 0ac32c83 | bellard | /* not efficient, but simple */
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255 | 7bf5be70 | bellard | addr = address; |
256 | 0ac32c83 | bellard | for(i = 0; i < len; i++) { |
257 | 0ac32c83 | bellard | /* default read/write accesses */
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258 | 1f62d938 | bellard | switch(d->config[0x0e]) { |
259 | 0ac32c83 | bellard | case 0x00: |
260 | 1f62d938 | bellard | case 0x80: |
261 | 1f62d938 | bellard | switch(addr) {
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262 | 1f62d938 | bellard | case 0x00: |
263 | 1f62d938 | bellard | case 0x01: |
264 | 1f62d938 | bellard | case 0x02: |
265 | 1f62d938 | bellard | case 0x03: |
266 | 1f62d938 | bellard | case 0x08: |
267 | 1f62d938 | bellard | case 0x09: |
268 | 1f62d938 | bellard | case 0x0a: |
269 | 1f62d938 | bellard | case 0x0b: |
270 | 1f62d938 | bellard | case 0x0e: |
271 | 1f62d938 | bellard | case 0x10 ... 0x27: /* base */ |
272 | 1f62d938 | bellard | case 0x30 ... 0x33: /* rom */ |
273 | 1f62d938 | bellard | case 0x3d: |
274 | 1f62d938 | bellard | can_write = 0;
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275 | 1f62d938 | bellard | break;
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276 | 1f62d938 | bellard | default:
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277 | 1f62d938 | bellard | can_write = 1;
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278 | 1f62d938 | bellard | break;
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279 | 1f62d938 | bellard | } |
280 | 0ac32c83 | bellard | break;
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281 | 0ac32c83 | bellard | default:
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282 | 1f62d938 | bellard | case 0x01: |
283 | 1f62d938 | bellard | switch(addr) {
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284 | 1f62d938 | bellard | case 0x00: |
285 | 1f62d938 | bellard | case 0x01: |
286 | 1f62d938 | bellard | case 0x02: |
287 | 1f62d938 | bellard | case 0x03: |
288 | 1f62d938 | bellard | case 0x08: |
289 | 1f62d938 | bellard | case 0x09: |
290 | 1f62d938 | bellard | case 0x0a: |
291 | 1f62d938 | bellard | case 0x0b: |
292 | 1f62d938 | bellard | case 0x0e: |
293 | 1f62d938 | bellard | case 0x38 ... 0x3b: /* rom */ |
294 | 1f62d938 | bellard | case 0x3d: |
295 | 1f62d938 | bellard | can_write = 0;
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296 | 1f62d938 | bellard | break;
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297 | 1f62d938 | bellard | default:
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298 | 1f62d938 | bellard | can_write = 1;
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299 | 1f62d938 | bellard | break;
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300 | 1f62d938 | bellard | } |
301 | 0ac32c83 | bellard | break;
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302 | 0ac32c83 | bellard | } |
303 | 0ac32c83 | bellard | if (can_write) {
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304 | 7bf5be70 | bellard | d->config[addr] = val; |
305 | 0ac32c83 | bellard | } |
306 | 7bf5be70 | bellard | addr++; |
307 | 0ac32c83 | bellard | val >>= 8;
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308 | 0ac32c83 | bellard | } |
309 | 0ac32c83 | bellard | |
310 | 0ac32c83 | bellard | end = address + len; |
311 | 0ac32c83 | bellard | if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) { |
312 | 0ac32c83 | bellard | /* if the command register is modified, we must modify the mappings */
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313 | 0ac32c83 | bellard | pci_update_mappings(d); |
314 | 69b91039 | bellard | } |
315 | 69b91039 | bellard | } |
316 | 69b91039 | bellard | |
317 | 69b91039 | bellard | static void pci_data_write(void *opaque, uint32_t addr, |
318 | 69b91039 | bellard | uint32_t val, int len)
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319 | 69b91039 | bellard | { |
320 | 69b91039 | bellard | PCIBridge *s = opaque; |
321 | 69b91039 | bellard | PCIDevice **bus, *pci_dev; |
322 | 0ac32c83 | bellard | int config_addr;
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323 | 69b91039 | bellard | |
324 | 69b91039 | bellard | #if defined(DEBUG_PCI) && 0 |
325 | 69b91039 | bellard | printf("pci_data_write: addr=%08x val=%08x len=%d\n",
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326 | 69b91039 | bellard | s->config_reg, val, len); |
327 | 69b91039 | bellard | #endif
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328 | 69b91039 | bellard | if (!(s->config_reg & (1 << 31))) { |
329 | 69b91039 | bellard | return;
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330 | 69b91039 | bellard | } |
331 | 69b91039 | bellard | if ((s->config_reg & 0x3) != 0) { |
332 | 69b91039 | bellard | return;
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333 | 69b91039 | bellard | } |
334 | 69b91039 | bellard | bus = s->pci_bus[(s->config_reg >> 16) & 0xff]; |
335 | 69b91039 | bellard | if (!bus)
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336 | 69b91039 | bellard | return;
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337 | 69b91039 | bellard | pci_dev = bus[(s->config_reg >> 8) & 0xff]; |
338 | 69b91039 | bellard | if (!pci_dev)
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339 | 69b91039 | bellard | return;
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340 | 69b91039 | bellard | config_addr = (s->config_reg & 0xfc) | (addr & 3); |
341 | 69b91039 | bellard | #if defined(DEBUG_PCI)
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342 | 69b91039 | bellard | printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
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343 | 69b91039 | bellard | pci_dev->name, config_addr, val, len); |
344 | 69b91039 | bellard | #endif
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345 | 0ac32c83 | bellard | pci_dev->config_write(pci_dev, config_addr, val, len); |
346 | 69b91039 | bellard | } |
347 | 69b91039 | bellard | |
348 | 69b91039 | bellard | static uint32_t pci_data_read(void *opaque, uint32_t addr, |
349 | 69b91039 | bellard | int len)
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350 | 69b91039 | bellard | { |
351 | 69b91039 | bellard | PCIBridge *s = opaque; |
352 | 69b91039 | bellard | PCIDevice **bus, *pci_dev; |
353 | 69b91039 | bellard | int config_addr;
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354 | 69b91039 | bellard | uint32_t val; |
355 | 69b91039 | bellard | |
356 | 69b91039 | bellard | if (!(s->config_reg & (1 << 31))) |
357 | 69b91039 | bellard | goto fail;
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358 | 69b91039 | bellard | if ((s->config_reg & 0x3) != 0) |
359 | 69b91039 | bellard | goto fail;
|
360 | 69b91039 | bellard | bus = s->pci_bus[(s->config_reg >> 16) & 0xff]; |
361 | 69b91039 | bellard | if (!bus)
|
362 | 69b91039 | bellard | goto fail;
|
363 | 69b91039 | bellard | pci_dev = bus[(s->config_reg >> 8) & 0xff]; |
364 | 69b91039 | bellard | if (!pci_dev) {
|
365 | 69b91039 | bellard | fail:
|
366 | 63ce9e0a | bellard | switch(len) {
|
367 | 63ce9e0a | bellard | case 1: |
368 | 63ce9e0a | bellard | val = 0xff;
|
369 | 63ce9e0a | bellard | break;
|
370 | 63ce9e0a | bellard | case 2: |
371 | 63ce9e0a | bellard | val = 0xffff;
|
372 | 63ce9e0a | bellard | break;
|
373 | 63ce9e0a | bellard | default:
|
374 | 63ce9e0a | bellard | case 4: |
375 | 63ce9e0a | bellard | val = 0xffffffff;
|
376 | 63ce9e0a | bellard | break;
|
377 | 63ce9e0a | bellard | } |
378 | 69b91039 | bellard | goto the_end;
|
379 | 69b91039 | bellard | } |
380 | 69b91039 | bellard | config_addr = (s->config_reg & 0xfc) | (addr & 3); |
381 | 69b91039 | bellard | val = pci_dev->config_read(pci_dev, config_addr, len); |
382 | 69b91039 | bellard | #if defined(DEBUG_PCI)
|
383 | 69b91039 | bellard | printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
|
384 | 69b91039 | bellard | pci_dev->name, config_addr, val, len); |
385 | 69b91039 | bellard | #endif
|
386 | 69b91039 | bellard | the_end:
|
387 | 69b91039 | bellard | #if defined(DEBUG_PCI) && 0 |
388 | 69b91039 | bellard | printf("pci_data_read: addr=%08x val=%08x len=%d\n",
|
389 | 69b91039 | bellard | s->config_reg, val, len); |
390 | 69b91039 | bellard | #endif
|
391 | 69b91039 | bellard | return val;
|
392 | 69b91039 | bellard | } |
393 | 69b91039 | bellard | |
394 | 69b91039 | bellard | static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val) |
395 | 69b91039 | bellard | { |
396 | 69b91039 | bellard | pci_data_write(opaque, addr, val, 1);
|
397 | 69b91039 | bellard | } |
398 | 69b91039 | bellard | |
399 | 69b91039 | bellard | static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val) |
400 | 69b91039 | bellard | { |
401 | 69b91039 | bellard | pci_data_write(opaque, addr, val, 2);
|
402 | 69b91039 | bellard | } |
403 | 69b91039 | bellard | |
404 | 69b91039 | bellard | static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val) |
405 | 69b91039 | bellard | { |
406 | 69b91039 | bellard | pci_data_write(opaque, addr, val, 4);
|
407 | 69b91039 | bellard | } |
408 | 69b91039 | bellard | |
409 | 69b91039 | bellard | static uint32_t pci_data_readb(void* opaque, uint32_t addr) |
410 | 69b91039 | bellard | { |
411 | 69b91039 | bellard | return pci_data_read(opaque, addr, 1); |
412 | 69b91039 | bellard | } |
413 | 69b91039 | bellard | |
414 | 69b91039 | bellard | static uint32_t pci_data_readw(void* opaque, uint32_t addr) |
415 | 69b91039 | bellard | { |
416 | 69b91039 | bellard | return pci_data_read(opaque, addr, 2); |
417 | 69b91039 | bellard | } |
418 | 69b91039 | bellard | |
419 | 69b91039 | bellard | static uint32_t pci_data_readl(void* opaque, uint32_t addr) |
420 | 69b91039 | bellard | { |
421 | 69b91039 | bellard | return pci_data_read(opaque, addr, 4); |
422 | 69b91039 | bellard | } |
423 | 69b91039 | bellard | |
424 | 69b91039 | bellard | /* i440FX PCI bridge */
|
425 | 69b91039 | bellard | |
426 | 69b91039 | bellard | void i440fx_init(void) |
427 | 69b91039 | bellard | { |
428 | 69b91039 | bellard | PCIBridge *s = &pci_bridge; |
429 | 69b91039 | bellard | PCIDevice *d; |
430 | 69b91039 | bellard | |
431 | 0ac32c83 | bellard | register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s); |
432 | 0ac32c83 | bellard | register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s); |
433 | 69b91039 | bellard | |
434 | 69b91039 | bellard | register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s); |
435 | 69b91039 | bellard | register_ioport_write(0xcfc, 4, 2, pci_data_writew, s); |
436 | 69b91039 | bellard | register_ioport_write(0xcfc, 4, 4, pci_data_writel, s); |
437 | 69b91039 | bellard | register_ioport_read(0xcfc, 4, 1, pci_data_readb, s); |
438 | 69b91039 | bellard | register_ioport_read(0xcfc, 4, 2, pci_data_readw, s); |
439 | 69b91039 | bellard | register_ioport_read(0xcfc, 4, 4, pci_data_readl, s); |
440 | 69b91039 | bellard | |
441 | 69b91039 | bellard | d = pci_register_device("i440FX", sizeof(PCIDevice), 0, 0, |
442 | 0ac32c83 | bellard | NULL, NULL); |
443 | 69b91039 | bellard | |
444 | 69b91039 | bellard | d->config[0x00] = 0x86; // vendor_id |
445 | 69b91039 | bellard | d->config[0x01] = 0x80; |
446 | 69b91039 | bellard | d->config[0x02] = 0x37; // device_id |
447 | 69b91039 | bellard | d->config[0x03] = 0x12; |
448 | 69b91039 | bellard | d->config[0x08] = 0x02; // revision |
449 | 358c6407 | bellard | d->config[0x0a] = 0x00; // class_sub = host2pci |
450 | 69b91039 | bellard | d->config[0x0b] = 0x06; // class_base = PCI_bridge |
451 | 358c6407 | bellard | d->config[0x0e] = 0x00; // header_type |
452 | 69b91039 | bellard | } |
453 | 69b91039 | bellard | |
454 | 0ac32c83 | bellard | /* PIIX3 PCI to ISA bridge */
|
455 | 0ac32c83 | bellard | |
456 | 0ac32c83 | bellard | typedef struct PIIX3State { |
457 | 0ac32c83 | bellard | PCIDevice dev; |
458 | 0ac32c83 | bellard | } PIIX3State; |
459 | 0ac32c83 | bellard | |
460 | 0ac32c83 | bellard | PIIX3State *piix3_state; |
461 | 0ac32c83 | bellard | |
462 | 0ac32c83 | bellard | static void piix3_reset(PIIX3State *d) |
463 | 0ac32c83 | bellard | { |
464 | 0ac32c83 | bellard | uint8_t *pci_conf = d->dev.config; |
465 | 0ac32c83 | bellard | |
466 | 0ac32c83 | bellard | pci_conf[0x04] = 0x07; // master, memory and I/O |
467 | 0ac32c83 | bellard | pci_conf[0x05] = 0x00; |
468 | 0ac32c83 | bellard | pci_conf[0x06] = 0x00; |
469 | 0ac32c83 | bellard | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
470 | 0ac32c83 | bellard | pci_conf[0x4c] = 0x4d; |
471 | 0ac32c83 | bellard | pci_conf[0x4e] = 0x03; |
472 | 0ac32c83 | bellard | pci_conf[0x4f] = 0x00; |
473 | 0ac32c83 | bellard | pci_conf[0x60] = 0x80; |
474 | 0ac32c83 | bellard | pci_conf[0x69] = 0x02; |
475 | 0ac32c83 | bellard | pci_conf[0x70] = 0x80; |
476 | 0ac32c83 | bellard | pci_conf[0x76] = 0x0c; |
477 | 0ac32c83 | bellard | pci_conf[0x77] = 0x0c; |
478 | 0ac32c83 | bellard | pci_conf[0x78] = 0x02; |
479 | 0ac32c83 | bellard | pci_conf[0x79] = 0x00; |
480 | 0ac32c83 | bellard | pci_conf[0x80] = 0x00; |
481 | 0ac32c83 | bellard | pci_conf[0x82] = 0x00; |
482 | 0ac32c83 | bellard | pci_conf[0xa0] = 0x08; |
483 | 0ac32c83 | bellard | pci_conf[0xa0] = 0x08; |
484 | 0ac32c83 | bellard | pci_conf[0xa2] = 0x00; |
485 | 0ac32c83 | bellard | pci_conf[0xa3] = 0x00; |
486 | 0ac32c83 | bellard | pci_conf[0xa4] = 0x00; |
487 | 0ac32c83 | bellard | pci_conf[0xa5] = 0x00; |
488 | 0ac32c83 | bellard | pci_conf[0xa6] = 0x00; |
489 | 0ac32c83 | bellard | pci_conf[0xa7] = 0x00; |
490 | 0ac32c83 | bellard | pci_conf[0xa8] = 0x0f; |
491 | 0ac32c83 | bellard | pci_conf[0xaa] = 0x00; |
492 | 0ac32c83 | bellard | pci_conf[0xab] = 0x00; |
493 | 0ac32c83 | bellard | pci_conf[0xac] = 0x00; |
494 | 0ac32c83 | bellard | pci_conf[0xae] = 0x00; |
495 | 0ac32c83 | bellard | } |
496 | 0ac32c83 | bellard | |
497 | 0ac32c83 | bellard | void piix3_init(void) |
498 | 0ac32c83 | bellard | { |
499 | 0ac32c83 | bellard | PIIX3State *d; |
500 | 0ac32c83 | bellard | uint8_t *pci_conf; |
501 | 0ac32c83 | bellard | |
502 | 0ac32c83 | bellard | d = (PIIX3State *)pci_register_device("PIIX3", sizeof(PIIX3State), |
503 | 0ac32c83 | bellard | 0, -1, |
504 | 0ac32c83 | bellard | NULL, NULL); |
505 | 0ac32c83 | bellard | piix3_state = d; |
506 | 0ac32c83 | bellard | pci_conf = d->dev.config; |
507 | 0ac32c83 | bellard | |
508 | 0ac32c83 | bellard | pci_conf[0x00] = 0x86; // Intel |
509 | 0ac32c83 | bellard | pci_conf[0x01] = 0x80; |
510 | 0ac32c83 | bellard | pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) |
511 | 0ac32c83 | bellard | pci_conf[0x03] = 0x70; |
512 | 0ac32c83 | bellard | pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA |
513 | 0ac32c83 | bellard | pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
514 | 0ac32c83 | bellard | pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic |
515 | 0ac32c83 | bellard | |
516 | 0ac32c83 | bellard | piix3_reset(d); |
517 | 0ac32c83 | bellard | } |
518 | 0ac32c83 | bellard | |
519 | 77d4bc34 | bellard | /* PREP pci init */
|
520 | 77d4bc34 | bellard | |
521 | 77d4bc34 | bellard | static inline void set_config(PCIBridge *s, target_phys_addr_t addr) |
522 | 77d4bc34 | bellard | { |
523 | 77d4bc34 | bellard | int devfn, i;
|
524 | 77d4bc34 | bellard | |
525 | 77d4bc34 | bellard | for(i = 0; i < 11; i++) { |
526 | 77d4bc34 | bellard | if ((addr & (1 << (11 + i))) != 0) |
527 | 77d4bc34 | bellard | break;
|
528 | 77d4bc34 | bellard | } |
529 | 77d4bc34 | bellard | devfn = ((addr >> 8) & 7) | (i << 3); |
530 | 77d4bc34 | bellard | s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8); |
531 | 77d4bc34 | bellard | } |
532 | 77d4bc34 | bellard | |
533 | 8a8696a3 | bellard | static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) |
534 | 77d4bc34 | bellard | { |
535 | 8a8696a3 | bellard | PCIBridge *s = opaque; |
536 | 77d4bc34 | bellard | set_config(s, addr); |
537 | 77d4bc34 | bellard | pci_data_write(s, addr, val, 1);
|
538 | 77d4bc34 | bellard | } |
539 | 77d4bc34 | bellard | |
540 | 8a8696a3 | bellard | static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val) |
541 | 77d4bc34 | bellard | { |
542 | 8a8696a3 | bellard | PCIBridge *s = opaque; |
543 | 77d4bc34 | bellard | set_config(s, addr); |
544 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
545 | 77d4bc34 | bellard | val = bswap16(val); |
546 | 77d4bc34 | bellard | #endif
|
547 | 77d4bc34 | bellard | pci_data_write(s, addr, val, 2);
|
548 | 77d4bc34 | bellard | } |
549 | 77d4bc34 | bellard | |
550 | 8a8696a3 | bellard | static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val) |
551 | 77d4bc34 | bellard | { |
552 | 8a8696a3 | bellard | PCIBridge *s = opaque; |
553 | 77d4bc34 | bellard | set_config(s, addr); |
554 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
555 | 77d4bc34 | bellard | val = bswap32(val); |
556 | 77d4bc34 | bellard | #endif
|
557 | 77d4bc34 | bellard | pci_data_write(s, addr, val, 4);
|
558 | 77d4bc34 | bellard | } |
559 | 77d4bc34 | bellard | |
560 | 8a8696a3 | bellard | static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr) |
561 | 77d4bc34 | bellard | { |
562 | 8a8696a3 | bellard | PCIBridge *s = opaque; |
563 | 77d4bc34 | bellard | uint32_t val; |
564 | 77d4bc34 | bellard | set_config(s, addr); |
565 | 77d4bc34 | bellard | val = pci_data_read(s, addr, 1);
|
566 | 77d4bc34 | bellard | return val;
|
567 | 77d4bc34 | bellard | } |
568 | 77d4bc34 | bellard | |
569 | 8a8696a3 | bellard | static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr) |
570 | 77d4bc34 | bellard | { |
571 | 8a8696a3 | bellard | PCIBridge *s = opaque; |
572 | 77d4bc34 | bellard | uint32_t val; |
573 | 77d4bc34 | bellard | set_config(s, addr); |
574 | 77d4bc34 | bellard | val = pci_data_read(s, addr, 2);
|
575 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
576 | 77d4bc34 | bellard | val = bswap16(val); |
577 | 77d4bc34 | bellard | #endif
|
578 | 77d4bc34 | bellard | return val;
|
579 | 77d4bc34 | bellard | } |
580 | 77d4bc34 | bellard | |
581 | 8a8696a3 | bellard | static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr) |
582 | 77d4bc34 | bellard | { |
583 | 8a8696a3 | bellard | PCIBridge *s = opaque; |
584 | 77d4bc34 | bellard | uint32_t val; |
585 | 77d4bc34 | bellard | set_config(s, addr); |
586 | 77d4bc34 | bellard | val = pci_data_read(s, addr, 4);
|
587 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
588 | 77d4bc34 | bellard | val = bswap32(val); |
589 | 77d4bc34 | bellard | #endif
|
590 | 77d4bc34 | bellard | return val;
|
591 | 77d4bc34 | bellard | } |
592 | 77d4bc34 | bellard | |
593 | 77d4bc34 | bellard | static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
|
594 | 77d4bc34 | bellard | &PPC_PCIIO_writeb, |
595 | 77d4bc34 | bellard | &PPC_PCIIO_writew, |
596 | 77d4bc34 | bellard | &PPC_PCIIO_writel, |
597 | 77d4bc34 | bellard | }; |
598 | 77d4bc34 | bellard | |
599 | 77d4bc34 | bellard | static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
|
600 | 77d4bc34 | bellard | &PPC_PCIIO_readb, |
601 | 77d4bc34 | bellard | &PPC_PCIIO_readw, |
602 | 77d4bc34 | bellard | &PPC_PCIIO_readl, |
603 | 77d4bc34 | bellard | }; |
604 | 77d4bc34 | bellard | |
605 | 77d4bc34 | bellard | void pci_prep_init(void) |
606 | 77d4bc34 | bellard | { |
607 | 8a8696a3 | bellard | PCIBridge *s = &pci_bridge; |
608 | 77d4bc34 | bellard | PCIDevice *d; |
609 | 77d4bc34 | bellard | int PPC_io_memory;
|
610 | 77d4bc34 | bellard | |
611 | 8a8696a3 | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
|
612 | 8a8696a3 | bellard | PPC_PCIIO_write, s); |
613 | 77d4bc34 | bellard | cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory); |
614 | 77d4bc34 | bellard | |
615 | 77d4bc34 | bellard | d = pci_register_device("PREP PCI Bridge", sizeof(PCIDevice), 0, 0, |
616 | 77d4bc34 | bellard | NULL, NULL); |
617 | 77d4bc34 | bellard | |
618 | 77d4bc34 | bellard | /* XXX: put correct IDs */
|
619 | 77d4bc34 | bellard | d->config[0x00] = 0x11; // vendor_id |
620 | 77d4bc34 | bellard | d->config[0x01] = 0x10; |
621 | 77d4bc34 | bellard | d->config[0x02] = 0x26; // device_id |
622 | 77d4bc34 | bellard | d->config[0x03] = 0x00; |
623 | 77d4bc34 | bellard | d->config[0x08] = 0x02; // revision |
624 | 77d4bc34 | bellard | d->config[0x0a] = 0x04; // class_sub = pci2pci |
625 | 77d4bc34 | bellard | d->config[0x0b] = 0x06; // class_base = PCI_bridge |
626 | 77d4bc34 | bellard | d->config[0x0e] = 0x01; // header_type |
627 | 77d4bc34 | bellard | } |
628 | 77d4bc34 | bellard | |
629 | 77d4bc34 | bellard | |
630 | 77d4bc34 | bellard | /* pmac pci init */
|
631 | 77d4bc34 | bellard | |
632 | 8a8696a3 | bellard | static void pci_pmac_config_writel (void *opaque, target_phys_addr_t addr, uint32_t val) |
633 | 77d4bc34 | bellard | { |
634 | 8a8696a3 | bellard | PCIBridge *s = opaque; |
635 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
636 | 77d4bc34 | bellard | val = bswap32(val); |
637 | 77d4bc34 | bellard | #endif
|
638 | 77d4bc34 | bellard | s->config_reg = val; |
639 | 77d4bc34 | bellard | } |
640 | 77d4bc34 | bellard | |
641 | 8a8696a3 | bellard | static uint32_t pci_pmac_config_readl (void *opaque, target_phys_addr_t addr) |
642 | 77d4bc34 | bellard | { |
643 | 8a8696a3 | bellard | PCIBridge *s = opaque; |
644 | 77d4bc34 | bellard | uint32_t val; |
645 | 77d4bc34 | bellard | |
646 | 77d4bc34 | bellard | val = s->config_reg; |
647 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
648 | 77d4bc34 | bellard | val = bswap32(val); |
649 | 77d4bc34 | bellard | #endif
|
650 | 77d4bc34 | bellard | return val;
|
651 | 77d4bc34 | bellard | } |
652 | 77d4bc34 | bellard | |
653 | 77d4bc34 | bellard | static CPUWriteMemoryFunc *pci_pmac_config_write[] = {
|
654 | 77d4bc34 | bellard | &pci_pmac_config_writel, |
655 | 77d4bc34 | bellard | &pci_pmac_config_writel, |
656 | 77d4bc34 | bellard | &pci_pmac_config_writel, |
657 | 77d4bc34 | bellard | }; |
658 | 77d4bc34 | bellard | |
659 | 77d4bc34 | bellard | static CPUReadMemoryFunc *pci_pmac_config_read[] = {
|
660 | 77d4bc34 | bellard | &pci_pmac_config_readl, |
661 | 77d4bc34 | bellard | &pci_pmac_config_readl, |
662 | 77d4bc34 | bellard | &pci_pmac_config_readl, |
663 | 77d4bc34 | bellard | }; |
664 | 77d4bc34 | bellard | |
665 | 8a8696a3 | bellard | static void pci_pmac_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) |
666 | 77d4bc34 | bellard | { |
667 | 8a8696a3 | bellard | PCIBridge *s = opaque; |
668 | 77d4bc34 | bellard | pci_data_write(s, addr, val, 1);
|
669 | 77d4bc34 | bellard | } |
670 | 77d4bc34 | bellard | |
671 | 8a8696a3 | bellard | static void pci_pmac_writew (void *opaque, target_phys_addr_t addr, uint32_t val) |
672 | 77d4bc34 | bellard | { |
673 | 8a8696a3 | bellard | PCIBridge *s = opaque; |
674 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
675 | 77d4bc34 | bellard | val = bswap16(val); |
676 | 77d4bc34 | bellard | #endif
|
677 | 77d4bc34 | bellard | pci_data_write(s, addr, val, 2);
|
678 | 77d4bc34 | bellard | } |
679 | 77d4bc34 | bellard | |
680 | 8a8696a3 | bellard | static void pci_pmac_writel (void *opaque, target_phys_addr_t addr, uint32_t val) |
681 | 77d4bc34 | bellard | { |
682 | 8a8696a3 | bellard | PCIBridge *s = opaque; |
683 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
684 | 77d4bc34 | bellard | val = bswap32(val); |
685 | 77d4bc34 | bellard | #endif
|
686 | 77d4bc34 | bellard | pci_data_write(s, addr, val, 4);
|
687 | 77d4bc34 | bellard | } |
688 | 77d4bc34 | bellard | |
689 | 8a8696a3 | bellard | static uint32_t pci_pmac_readb (void *opaque, target_phys_addr_t addr) |
690 | 77d4bc34 | bellard | { |
691 | 8a8696a3 | bellard | PCIBridge *s = opaque; |
692 | 77d4bc34 | bellard | uint32_t val; |
693 | 77d4bc34 | bellard | val = pci_data_read(s, addr, 1);
|
694 | 77d4bc34 | bellard | return val;
|
695 | 77d4bc34 | bellard | } |
696 | 77d4bc34 | bellard | |
697 | 8a8696a3 | bellard | static uint32_t pci_pmac_readw (void *opaque, target_phys_addr_t addr) |
698 | 77d4bc34 | bellard | { |
699 | 8a8696a3 | bellard | PCIBridge *s = opaque; |
700 | 77d4bc34 | bellard | uint32_t val; |
701 | 77d4bc34 | bellard | val = pci_data_read(s, addr, 2);
|
702 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
703 | 77d4bc34 | bellard | val = bswap16(val); |
704 | 77d4bc34 | bellard | #endif
|
705 | 77d4bc34 | bellard | return val;
|
706 | 77d4bc34 | bellard | } |
707 | 77d4bc34 | bellard | |
708 | 8a8696a3 | bellard | static uint32_t pci_pmac_readl (void *opaque, target_phys_addr_t addr) |
709 | 77d4bc34 | bellard | { |
710 | 8a8696a3 | bellard | PCIBridge *s = opaque; |
711 | 77d4bc34 | bellard | uint32_t val; |
712 | 77d4bc34 | bellard | |
713 | 77d4bc34 | bellard | val = pci_data_read(s, addr, 4);
|
714 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
715 | 77d4bc34 | bellard | val = bswap32(val); |
716 | 77d4bc34 | bellard | #endif
|
717 | 77d4bc34 | bellard | return val;
|
718 | 77d4bc34 | bellard | } |
719 | 77d4bc34 | bellard | |
720 | 77d4bc34 | bellard | static CPUWriteMemoryFunc *pci_pmac_write[] = {
|
721 | 77d4bc34 | bellard | &pci_pmac_writeb, |
722 | 77d4bc34 | bellard | &pci_pmac_writew, |
723 | 77d4bc34 | bellard | &pci_pmac_writel, |
724 | 77d4bc34 | bellard | }; |
725 | 77d4bc34 | bellard | |
726 | 77d4bc34 | bellard | static CPUReadMemoryFunc *pci_pmac_read[] = {
|
727 | 77d4bc34 | bellard | &pci_pmac_readb, |
728 | 77d4bc34 | bellard | &pci_pmac_readw, |
729 | 77d4bc34 | bellard | &pci_pmac_readl, |
730 | 77d4bc34 | bellard | }; |
731 | 77d4bc34 | bellard | |
732 | 77d4bc34 | bellard | void pci_pmac_init(void) |
733 | 77d4bc34 | bellard | { |
734 | 8a8696a3 | bellard | PCIBridge *s = &pci_bridge; |
735 | 77d4bc34 | bellard | PCIDevice *d; |
736 | 77d4bc34 | bellard | int pci_mem_config, pci_mem_data;
|
737 | 77d4bc34 | bellard | |
738 | 77d4bc34 | bellard | pci_mem_config = cpu_register_io_memory(0, pci_pmac_config_read,
|
739 | 8a8696a3 | bellard | pci_pmac_config_write, s); |
740 | 8a8696a3 | bellard | pci_mem_data = cpu_register_io_memory(0, pci_pmac_read, pci_pmac_write, s);
|
741 | 77d4bc34 | bellard | |
742 | 77d4bc34 | bellard | cpu_register_physical_memory(0xfec00000, 0x1000, pci_mem_config); |
743 | 77d4bc34 | bellard | cpu_register_physical_memory(0xfee00000, 0x1000, pci_mem_data); |
744 | 77d4bc34 | bellard | |
745 | 77d4bc34 | bellard | d = pci_register_device("MPC106", sizeof(PCIDevice), 0, 0, |
746 | 77d4bc34 | bellard | NULL, NULL); |
747 | 77d4bc34 | bellard | |
748 | 77d4bc34 | bellard | /* same values as PearPC - check this */
|
749 | 77d4bc34 | bellard | d->config[0x00] = 0x11; // vendor_id |
750 | 77d4bc34 | bellard | d->config[0x01] = 0x10; |
751 | 77d4bc34 | bellard | d->config[0x02] = 0x26; // device_id |
752 | 77d4bc34 | bellard | d->config[0x03] = 0x00; |
753 | 77d4bc34 | bellard | d->config[0x08] = 0x02; // revision |
754 | 77d4bc34 | bellard | d->config[0x0a] = 0x04; // class_sub = pci2pci |
755 | 77d4bc34 | bellard | d->config[0x0b] = 0x06; // class_base = PCI_bridge |
756 | 77d4bc34 | bellard | d->config[0x0e] = 0x01; // header_type |
757 | 77d4bc34 | bellard | |
758 | 77d4bc34 | bellard | d->config[0x18] = 0x0; // primary_bus |
759 | 77d4bc34 | bellard | d->config[0x19] = 0x1; // secondary_bus |
760 | 77d4bc34 | bellard | d->config[0x1a] = 0x1; // subordinate_bus |
761 | 77d4bc34 | bellard | d->config[0x1c] = 0x10; // io_base |
762 | 77d4bc34 | bellard | d->config[0x1d] = 0x20; // io_limit |
763 | 77d4bc34 | bellard | |
764 | 77d4bc34 | bellard | d->config[0x20] = 0x80; // memory_base |
765 | 77d4bc34 | bellard | d->config[0x21] = 0x80; |
766 | 77d4bc34 | bellard | d->config[0x22] = 0x90; // memory_limit |
767 | 77d4bc34 | bellard | d->config[0x23] = 0x80; |
768 | 77d4bc34 | bellard | |
769 | 77d4bc34 | bellard | d->config[0x24] = 0x00; // prefetchable_memory_base |
770 | 77d4bc34 | bellard | d->config[0x25] = 0x84; |
771 | 77d4bc34 | bellard | d->config[0x26] = 0x00; // prefetchable_memory_limit |
772 | 77d4bc34 | bellard | d->config[0x27] = 0x85; |
773 | 77d4bc34 | bellard | } |
774 | 77d4bc34 | bellard | |
775 | 0ac32c83 | bellard | /***********************************************************/
|
776 | 0ac32c83 | bellard | /* generic PCI irq support */
|
777 | 0ac32c83 | bellard | |
778 | 0ac32c83 | bellard | /* return the global irq number corresponding to a given device irq
|
779 | 0ac32c83 | bellard | pin. We could also use the bus number to have a more precise
|
780 | 0ac32c83 | bellard | mapping. */
|
781 | 0ac32c83 | bellard | static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) |
782 | 0ac32c83 | bellard | { |
783 | 0ac32c83 | bellard | int slot_addend;
|
784 | 0ac32c83 | bellard | slot_addend = (pci_dev->devfn >> 3);
|
785 | 0ac32c83 | bellard | return (irq_num + slot_addend) & 3; |
786 | 0ac32c83 | bellard | } |
787 | 0ac32c83 | bellard | |
788 | 0ac32c83 | bellard | /* 0 <= irq_num <= 3. level must be 0 or 1 */
|
789 | 77d4bc34 | bellard | #ifdef TARGET_PPC
|
790 | 77d4bc34 | bellard | void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level) |
791 | 77d4bc34 | bellard | { |
792 | 77d4bc34 | bellard | } |
793 | 77d4bc34 | bellard | #else
|
794 | 0ac32c83 | bellard | void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level) |
795 | 0ac32c83 | bellard | { |
796 | 0ac32c83 | bellard | int irq_index, shift, pic_irq, pic_level;
|
797 | 0ac32c83 | bellard | uint32_t *p; |
798 | 0ac32c83 | bellard | |
799 | 0ac32c83 | bellard | irq_num = pci_slot_get_pirq(pci_dev, irq_num); |
800 | 0ac32c83 | bellard | irq_index = pci_dev->irq_index; |
801 | 0ac32c83 | bellard | p = &pci_irq_levels[irq_num][irq_index >> 5];
|
802 | 0ac32c83 | bellard | shift = (irq_index & 0x1f);
|
803 | 0ac32c83 | bellard | *p = (*p & ~(1 << shift)) | (level << shift);
|
804 | 0ac32c83 | bellard | |
805 | 0ac32c83 | bellard | /* now we change the pic irq level according to the piix irq mappings */
|
806 | 0ac32c83 | bellard | pic_irq = piix3_state->dev.config[0x60 + irq_num];
|
807 | 0ac32c83 | bellard | if (pic_irq < 16) { |
808 | 0ac32c83 | bellard | /* the pic level is the logical OR of all the PCI irqs mapped
|
809 | 0ac32c83 | bellard | to it */
|
810 | 0ac32c83 | bellard | pic_level = 0;
|
811 | 0ac32c83 | bellard | #if (PCI_IRQ_WORDS == 2) |
812 | 0ac32c83 | bellard | pic_level = ((pci_irq_levels[irq_num][0] |
|
813 | 0ac32c83 | bellard | pci_irq_levels[irq_num][1]) != 0); |
814 | 0ac32c83 | bellard | #else
|
815 | 0ac32c83 | bellard | { |
816 | 0ac32c83 | bellard | int i;
|
817 | 0ac32c83 | bellard | pic_level = 0;
|
818 | 0ac32c83 | bellard | for(i = 0; i < PCI_IRQ_WORDS; i++) { |
819 | 0ac32c83 | bellard | if (pci_irq_levels[irq_num][i]) {
|
820 | 0ac32c83 | bellard | pic_level = 1;
|
821 | 0ac32c83 | bellard | break;
|
822 | 0ac32c83 | bellard | } |
823 | 0ac32c83 | bellard | } |
824 | 0ac32c83 | bellard | } |
825 | 0ac32c83 | bellard | #endif
|
826 | 0ac32c83 | bellard | pic_set_irq(pic_irq, pic_level); |
827 | 0ac32c83 | bellard | } |
828 | 0ac32c83 | bellard | } |
829 | 77d4bc34 | bellard | #endif
|
830 | 0ac32c83 | bellard | |
831 | 0ac32c83 | bellard | /***********************************************************/
|
832 | 0ac32c83 | bellard | /* monitor info on PCI */
|
833 | 0ac32c83 | bellard | |
834 | 0ac32c83 | bellard | static void pci_info_device(PCIDevice *d) |
835 | 0ac32c83 | bellard | { |
836 | 0ac32c83 | bellard | int i, class;
|
837 | 0ac32c83 | bellard | PCIIORegion *r; |
838 | 0ac32c83 | bellard | |
839 | 0ac32c83 | bellard | printf(" Bus %2d, device %3d, function %d:\n",
|
840 | 0ac32c83 | bellard | d->bus_num, d->devfn >> 3, d->devfn & 7); |
841 | 0ac32c83 | bellard | class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
842 | 0ac32c83 | bellard | printf(" ");
|
843 | 0ac32c83 | bellard | switch(class) {
|
844 | 0ac32c83 | bellard | case 0x0101: |
845 | 0ac32c83 | bellard | printf("IDE controller");
|
846 | 0ac32c83 | bellard | break;
|
847 | 0ac32c83 | bellard | case 0x0200: |
848 | 0ac32c83 | bellard | printf("Ethernet controller");
|
849 | 0ac32c83 | bellard | break;
|
850 | 0ac32c83 | bellard | case 0x0300: |
851 | 0ac32c83 | bellard | printf("VGA controller");
|
852 | 0ac32c83 | bellard | break;
|
853 | 0ac32c83 | bellard | default:
|
854 | 0ac32c83 | bellard | printf("Class %04x", class);
|
855 | 0ac32c83 | bellard | break;
|
856 | 0ac32c83 | bellard | } |
857 | 0ac32c83 | bellard | printf(": PCI device %04x:%04x\n",
|
858 | 0ac32c83 | bellard | le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
859 | 0ac32c83 | bellard | le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
860 | 0ac32c83 | bellard | |
861 | 0ac32c83 | bellard | if (d->config[PCI_INTERRUPT_PIN] != 0) { |
862 | 0ac32c83 | bellard | printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
|
863 | 0ac32c83 | bellard | } |
864 | 8a8696a3 | bellard | for(i = 0;i < PCI_NUM_REGIONS; i++) { |
865 | 0ac32c83 | bellard | r = &d->io_regions[i]; |
866 | 0ac32c83 | bellard | if (r->size != 0) { |
867 | 0ac32c83 | bellard | printf(" BAR%d: ", i);
|
868 | 0ac32c83 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO) {
|
869 | 0ac32c83 | bellard | printf("I/O at 0x%04x [0x%04x].\n",
|
870 | 0ac32c83 | bellard | r->addr, r->addr + r->size - 1);
|
871 | 0ac32c83 | bellard | } else {
|
872 | 0ac32c83 | bellard | printf("32 bit memory at 0x%08x [0x%08x].\n",
|
873 | 0ac32c83 | bellard | r->addr, r->addr + r->size - 1);
|
874 | 0ac32c83 | bellard | } |
875 | 0ac32c83 | bellard | } |
876 | 0ac32c83 | bellard | } |
877 | 0ac32c83 | bellard | } |
878 | 0ac32c83 | bellard | |
879 | 0ac32c83 | bellard | void pci_info(void) |
880 | 0ac32c83 | bellard | { |
881 | 0ac32c83 | bellard | PCIBridge *s = &pci_bridge; |
882 | 0ac32c83 | bellard | PCIDevice **bus; |
883 | 0ac32c83 | bellard | int bus_num, devfn;
|
884 | 0ac32c83 | bellard | |
885 | 0ac32c83 | bellard | for(bus_num = 0; bus_num < 256; bus_num++) { |
886 | 0ac32c83 | bellard | bus = s->pci_bus[bus_num]; |
887 | 0ac32c83 | bellard | if (bus) {
|
888 | 0ac32c83 | bellard | for(devfn = 0; devfn < 256; devfn++) { |
889 | 0ac32c83 | bellard | if (bus[devfn])
|
890 | 0ac32c83 | bellard | pci_info_device(bus[devfn]); |
891 | 0ac32c83 | bellard | } |
892 | 0ac32c83 | bellard | } |
893 | 0ac32c83 | bellard | } |
894 | 0ac32c83 | bellard | } |
895 | 0ac32c83 | bellard | |
896 | 0ac32c83 | bellard | /***********************************************************/
|
897 | 0ac32c83 | bellard | /* XXX: the following should be moved to the PC BIOS */
|
898 | 0ac32c83 | bellard | |
899 | 0ac32c83 | bellard | static uint32_t isa_inb(uint32_t addr)
|
900 | 0ac32c83 | bellard | { |
901 | 0ac32c83 | bellard | return cpu_inb(cpu_single_env, addr);
|
902 | 0ac32c83 | bellard | } |
903 | 0ac32c83 | bellard | |
904 | 0ac32c83 | bellard | static void isa_outb(uint32_t val, uint32_t addr) |
905 | 0ac32c83 | bellard | { |
906 | 0ac32c83 | bellard | cpu_outb(cpu_single_env, addr, val); |
907 | 0ac32c83 | bellard | } |
908 | 0ac32c83 | bellard | |
909 | 0ac32c83 | bellard | static uint32_t isa_inw(uint32_t addr)
|
910 | 0ac32c83 | bellard | { |
911 | 0ac32c83 | bellard | return cpu_inw(cpu_single_env, addr);
|
912 | 0ac32c83 | bellard | } |
913 | 0ac32c83 | bellard | |
914 | 0ac32c83 | bellard | static void isa_outw(uint32_t val, uint32_t addr) |
915 | 0ac32c83 | bellard | { |
916 | 0ac32c83 | bellard | cpu_outw(cpu_single_env, addr, val); |
917 | 0ac32c83 | bellard | } |
918 | 0ac32c83 | bellard | |
919 | 0ac32c83 | bellard | static uint32_t isa_inl(uint32_t addr)
|
920 | 0ac32c83 | bellard | { |
921 | 0ac32c83 | bellard | return cpu_inl(cpu_single_env, addr);
|
922 | 0ac32c83 | bellard | } |
923 | 0ac32c83 | bellard | |
924 | 0ac32c83 | bellard | static void isa_outl(uint32_t val, uint32_t addr) |
925 | 0ac32c83 | bellard | { |
926 | 0ac32c83 | bellard | cpu_outl(cpu_single_env, addr, val); |
927 | 0ac32c83 | bellard | } |
928 | 0ac32c83 | bellard | |
929 | 0ac32c83 | bellard | static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val) |
930 | 0ac32c83 | bellard | { |
931 | 0ac32c83 | bellard | PCIBridge *s = &pci_bridge; |
932 | 0ac32c83 | bellard | s->config_reg = 0x80000000 | (d->bus_num << 16) | |
933 | 0ac32c83 | bellard | (d->devfn << 8) | addr;
|
934 | 0ac32c83 | bellard | pci_data_write(s, 0, val, 4); |
935 | 0ac32c83 | bellard | } |
936 | 0ac32c83 | bellard | |
937 | 0ac32c83 | bellard | static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val) |
938 | 0ac32c83 | bellard | { |
939 | 0ac32c83 | bellard | PCIBridge *s = &pci_bridge; |
940 | 0ac32c83 | bellard | s->config_reg = 0x80000000 | (d->bus_num << 16) | |
941 | 0ac32c83 | bellard | (d->devfn << 8) | (addr & ~3); |
942 | 0ac32c83 | bellard | pci_data_write(s, addr & 3, val, 2); |
943 | 0ac32c83 | bellard | } |
944 | 0ac32c83 | bellard | |
945 | 0ac32c83 | bellard | static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val) |
946 | 0ac32c83 | bellard | { |
947 | 0ac32c83 | bellard | PCIBridge *s = &pci_bridge; |
948 | 0ac32c83 | bellard | s->config_reg = 0x80000000 | (d->bus_num << 16) | |
949 | 0ac32c83 | bellard | (d->devfn << 8) | (addr & ~3); |
950 | 0ac32c83 | bellard | pci_data_write(s, addr & 3, val, 1); |
951 | 0ac32c83 | bellard | } |
952 | 0ac32c83 | bellard | |
953 | 0ac32c83 | bellard | static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
|
954 | 0ac32c83 | bellard | { |
955 | 0ac32c83 | bellard | PCIBridge *s = &pci_bridge; |
956 | 0ac32c83 | bellard | s->config_reg = 0x80000000 | (d->bus_num << 16) | |
957 | 0ac32c83 | bellard | (d->devfn << 8) | addr;
|
958 | 0ac32c83 | bellard | return pci_data_read(s, 0, 4); |
959 | 0ac32c83 | bellard | } |
960 | 0ac32c83 | bellard | |
961 | 0ac32c83 | bellard | static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
|
962 | 0ac32c83 | bellard | { |
963 | 0ac32c83 | bellard | PCIBridge *s = &pci_bridge; |
964 | 0ac32c83 | bellard | s->config_reg = 0x80000000 | (d->bus_num << 16) | |
965 | 0ac32c83 | bellard | (d->devfn << 8) | (addr & ~3); |
966 | 0ac32c83 | bellard | return pci_data_read(s, addr & 3, 2); |
967 | 0ac32c83 | bellard | } |
968 | 0ac32c83 | bellard | |
969 | 0ac32c83 | bellard | static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
|
970 | 0ac32c83 | bellard | { |
971 | 0ac32c83 | bellard | PCIBridge *s = &pci_bridge; |
972 | 0ac32c83 | bellard | s->config_reg = 0x80000000 | (d->bus_num << 16) | |
973 | 0ac32c83 | bellard | (d->devfn << 8) | (addr & ~3); |
974 | 0ac32c83 | bellard | return pci_data_read(s, addr & 3, 1); |
975 | 0ac32c83 | bellard | } |
976 | 69b91039 | bellard | |
977 | 69b91039 | bellard | static uint32_t pci_bios_io_addr;
|
978 | 69b91039 | bellard | static uint32_t pci_bios_mem_addr;
|
979 | 0ac32c83 | bellard | /* host irqs corresponding to PCI irqs A-D */
|
980 | 0ac32c83 | bellard | static uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; |
981 | 69b91039 | bellard | |
982 | 69b91039 | bellard | static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr) |
983 | 69b91039 | bellard | { |
984 | 69b91039 | bellard | PCIIORegion *r; |
985 | 0ac32c83 | bellard | uint16_t cmd; |
986 | 8a8696a3 | bellard | uint32_t ofs; |
987 | 8a8696a3 | bellard | |
988 | 8a8696a3 | bellard | if ( region_num == PCI_ROM_SLOT ) {
|
989 | 8a8696a3 | bellard | ofs = 0x30;
|
990 | 8a8696a3 | bellard | }else{
|
991 | 8a8696a3 | bellard | ofs = 0x10 + region_num * 4; |
992 | 8a8696a3 | bellard | } |
993 | 69b91039 | bellard | |
994 | 8a8696a3 | bellard | pci_config_writel(d, ofs, addr); |
995 | 69b91039 | bellard | r = &d->io_regions[region_num]; |
996 | 69b91039 | bellard | |
997 | 69b91039 | bellard | /* enable memory mappings */
|
998 | 0ac32c83 | bellard | cmd = pci_config_readw(d, PCI_COMMAND); |
999 | 8a8696a3 | bellard | if ( region_num == PCI_ROM_SLOT )
|
1000 | 8a8696a3 | bellard | cmd |= 2;
|
1001 | 8a8696a3 | bellard | else if (r->type & PCI_ADDRESS_SPACE_IO) |
1002 | 0ac32c83 | bellard | cmd |= 1;
|
1003 | 69b91039 | bellard | else
|
1004 | 0ac32c83 | bellard | cmd |= 2;
|
1005 | 0ac32c83 | bellard | pci_config_writew(d, PCI_COMMAND, cmd); |
1006 | 69b91039 | bellard | } |
1007 | 69b91039 | bellard | |
1008 | 69b91039 | bellard | static void pci_bios_init_device(PCIDevice *d) |
1009 | 69b91039 | bellard | { |
1010 | 69b91039 | bellard | int class;
|
1011 | 69b91039 | bellard | PCIIORegion *r; |
1012 | 69b91039 | bellard | uint32_t *paddr; |
1013 | 63ce9e0a | bellard | int i, pin, pic_irq, vendor_id, device_id;
|
1014 | 69b91039 | bellard | |
1015 | 63ce9e0a | bellard | class = pci_config_readw(d, PCI_CLASS_DEVICE); |
1016 | 1f62d938 | bellard | vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
1017 | 1f62d938 | bellard | device_id = pci_config_readw(d, PCI_DEVICE_ID); |
1018 | 69b91039 | bellard | switch(class) {
|
1019 | 69b91039 | bellard | case 0x0101: |
1020 | 63ce9e0a | bellard | if (vendor_id == 0x8086 && device_id == 0x7010) { |
1021 | 63ce9e0a | bellard | /* PIIX3 IDE */
|
1022 | 63ce9e0a | bellard | pci_config_writew(d, PCI_COMMAND, PCI_COMMAND_IO); |
1023 | 63ce9e0a | bellard | pci_config_writew(d, 0x40, 0x8000); // enable IDE0 |
1024 | 7f647cf6 | bellard | pci_config_writew(d, 0x42, 0x8000); // enable IDE1 |
1025 | 63ce9e0a | bellard | } else {
|
1026 | 63ce9e0a | bellard | /* IDE: we map it as in ISA mode */
|
1027 | 63ce9e0a | bellard | pci_set_io_region_addr(d, 0, 0x1f0); |
1028 | 63ce9e0a | bellard | pci_set_io_region_addr(d, 1, 0x3f4); |
1029 | 63ce9e0a | bellard | pci_set_io_region_addr(d, 2, 0x170); |
1030 | 63ce9e0a | bellard | pci_set_io_region_addr(d, 3, 0x374); |
1031 | 63ce9e0a | bellard | } |
1032 | 69b91039 | bellard | break;
|
1033 | 0ac32c83 | bellard | case 0x0300: |
1034 | 4c7634bc | bellard | if (vendor_id != 0x1234) |
1035 | 4c7634bc | bellard | goto default_map;
|
1036 | 0ac32c83 | bellard | /* VGA: map frame buffer to default Bochs VBE address */
|
1037 | 0ac32c83 | bellard | pci_set_io_region_addr(d, 0, 0xE0000000); |
1038 | 0ac32c83 | bellard | break;
|
1039 | 1f62d938 | bellard | case 0xff00: |
1040 | 1f62d938 | bellard | if (vendor_id == 0x0106b && device_id == 0x0017) { |
1041 | 1f62d938 | bellard | /* macio bridge */
|
1042 | 1f62d938 | bellard | pci_set_io_region_addr(d, 0, 0x80800000); |
1043 | 1f62d938 | bellard | } |
1044 | 1f62d938 | bellard | break;
|
1045 | 69b91039 | bellard | default:
|
1046 | 4c7634bc | bellard | default_map:
|
1047 | 69b91039 | bellard | /* default memory mappings */
|
1048 | 8a8696a3 | bellard | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
1049 | 69b91039 | bellard | r = &d->io_regions[i]; |
1050 | 69b91039 | bellard | if (r->size) {
|
1051 | 69b91039 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO)
|
1052 | 69b91039 | bellard | paddr = &pci_bios_io_addr; |
1053 | 69b91039 | bellard | else
|
1054 | 69b91039 | bellard | paddr = &pci_bios_mem_addr; |
1055 | 69b91039 | bellard | *paddr = (*paddr + r->size - 1) & ~(r->size - 1); |
1056 | 69b91039 | bellard | pci_set_io_region_addr(d, i, *paddr); |
1057 | 69b91039 | bellard | *paddr += r->size; |
1058 | 69b91039 | bellard | } |
1059 | 69b91039 | bellard | } |
1060 | 69b91039 | bellard | break;
|
1061 | 69b91039 | bellard | } |
1062 | 0ac32c83 | bellard | |
1063 | 0ac32c83 | bellard | /* map the interrupt */
|
1064 | 0ac32c83 | bellard | pin = pci_config_readb(d, PCI_INTERRUPT_PIN); |
1065 | 0ac32c83 | bellard | if (pin != 0) { |
1066 | 0ac32c83 | bellard | pin = pci_slot_get_pirq(d, pin - 1);
|
1067 | 0ac32c83 | bellard | pic_irq = pci_irqs[pin]; |
1068 | 0ac32c83 | bellard | pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq); |
1069 | 0ac32c83 | bellard | } |
1070 | 69b91039 | bellard | } |
1071 | 69b91039 | bellard | |
1072 | 69b91039 | bellard | /*
|
1073 | 69b91039 | bellard | * This function initializes the PCI devices as a normal PCI BIOS
|
1074 | 69b91039 | bellard | * would do. It is provided just in case the BIOS has no support for
|
1075 | 69b91039 | bellard | * PCI.
|
1076 | 69b91039 | bellard | */
|
1077 | 69b91039 | bellard | void pci_bios_init(void) |
1078 | 69b91039 | bellard | { |
1079 | 69b91039 | bellard | PCIBridge *s = &pci_bridge; |
1080 | 69b91039 | bellard | PCIDevice **bus; |
1081 | 0ac32c83 | bellard | int bus_num, devfn, i, irq;
|
1082 | 0ac32c83 | bellard | uint8_t elcr[2];
|
1083 | 69b91039 | bellard | |
1084 | 69b91039 | bellard | pci_bios_io_addr = 0xc000;
|
1085 | 69b91039 | bellard | pci_bios_mem_addr = 0xf0000000;
|
1086 | 69b91039 | bellard | |
1087 | 0ac32c83 | bellard | /* activate IRQ mappings */
|
1088 | 0ac32c83 | bellard | elcr[0] = 0x00; |
1089 | 0ac32c83 | bellard | elcr[1] = 0x00; |
1090 | 0ac32c83 | bellard | for(i = 0; i < 4; i++) { |
1091 | 0ac32c83 | bellard | irq = pci_irqs[i]; |
1092 | 0ac32c83 | bellard | /* set to trigger level */
|
1093 | 0ac32c83 | bellard | elcr[irq >> 3] |= (1 << (irq & 7)); |
1094 | 0ac32c83 | bellard | /* activate irq remapping in PIIX */
|
1095 | 0ac32c83 | bellard | pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
|
1096 | 0ac32c83 | bellard | } |
1097 | 0ac32c83 | bellard | isa_outb(elcr[0], 0x4d0); |
1098 | 0ac32c83 | bellard | isa_outb(elcr[1], 0x4d1); |
1099 | 0ac32c83 | bellard | |
1100 | 69b91039 | bellard | for(bus_num = 0; bus_num < 256; bus_num++) { |
1101 | 69b91039 | bellard | bus = s->pci_bus[bus_num]; |
1102 | 69b91039 | bellard | if (bus) {
|
1103 | 69b91039 | bellard | for(devfn = 0; devfn < 256; devfn++) { |
1104 | 69b91039 | bellard | if (bus[devfn])
|
1105 | 69b91039 | bellard | pci_bios_init_device(bus[devfn]); |
1106 | 69b91039 | bellard | } |
1107 | 69b91039 | bellard | } |
1108 | 69b91039 | bellard | } |
1109 | 69b91039 | bellard | } |
1110 | 77d4bc34 | bellard | |
1111 | 77d4bc34 | bellard | /*
|
1112 | 77d4bc34 | bellard | * This function initializes the PCI devices as a normal PCI BIOS
|
1113 | 77d4bc34 | bellard | * would do. It is provided just in case the BIOS has no support for
|
1114 | 77d4bc34 | bellard | * PCI.
|
1115 | 77d4bc34 | bellard | */
|
1116 | 77d4bc34 | bellard | void pci_ppc_bios_init(void) |
1117 | 77d4bc34 | bellard | { |
1118 | 77d4bc34 | bellard | PCIBridge *s = &pci_bridge; |
1119 | 77d4bc34 | bellard | PCIDevice **bus; |
1120 | 77d4bc34 | bellard | int bus_num, devfn, i, irq;
|
1121 | 77d4bc34 | bellard | uint8_t elcr[2];
|
1122 | 77d4bc34 | bellard | |
1123 | 77d4bc34 | bellard | pci_bios_io_addr = 0xc000;
|
1124 | 77d4bc34 | bellard | pci_bios_mem_addr = 0xc0000000;
|
1125 | 77d4bc34 | bellard | |
1126 | 77d4bc34 | bellard | #if 0
|
1127 | 77d4bc34 | bellard | /* activate IRQ mappings */
|
1128 | 77d4bc34 | bellard | elcr[0] = 0x00;
|
1129 | 77d4bc34 | bellard | elcr[1] = 0x00;
|
1130 | 77d4bc34 | bellard | for(i = 0; i < 4; i++) {
|
1131 | 77d4bc34 | bellard | irq = pci_irqs[i];
|
1132 | 77d4bc34 | bellard | /* set to trigger level */
|
1133 | 77d4bc34 | bellard | elcr[irq >> 3] |= (1 << (irq & 7));
|
1134 | 77d4bc34 | bellard | /* activate irq remapping in PIIX */
|
1135 | 77d4bc34 | bellard | pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
|
1136 | 77d4bc34 | bellard | }
|
1137 | 77d4bc34 | bellard | isa_outb(elcr[0], 0x4d0);
|
1138 | 77d4bc34 | bellard | isa_outb(elcr[1], 0x4d1);
|
1139 | 77d4bc34 | bellard | #endif
|
1140 | 77d4bc34 | bellard | |
1141 | 77d4bc34 | bellard | for(bus_num = 0; bus_num < 256; bus_num++) { |
1142 | 77d4bc34 | bellard | bus = s->pci_bus[bus_num]; |
1143 | 77d4bc34 | bellard | if (bus) {
|
1144 | 77d4bc34 | bellard | for(devfn = 0; devfn < 256; devfn++) { |
1145 | 77d4bc34 | bellard | if (bus[devfn])
|
1146 | 77d4bc34 | bellard | pci_bios_init_device(bus[devfn]); |
1147 | 77d4bc34 | bellard | } |
1148 | 77d4bc34 | bellard | } |
1149 | 77d4bc34 | bellard | } |
1150 | 77d4bc34 | bellard | } |