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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * i386 virtual CPU header
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3 | 5fafdf24 | ths | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | 2c0262af | bellard | #ifndef CPU_I386_H
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21 | 2c0262af | bellard | #define CPU_I386_H
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22 | 2c0262af | bellard | |
23 | 14ce26e7 | bellard | #include "config.h" |
24 | 14ce26e7 | bellard | |
25 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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26 | 14ce26e7 | bellard | #define TARGET_LONG_BITS 64 |
27 | 14ce26e7 | bellard | #else
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28 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
29 | 14ce26e7 | bellard | #endif
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30 | 3cf1e035 | bellard | |
31 | d720b93d | bellard | /* target supports implicit self modifying code */
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32 | d720b93d | bellard | #define TARGET_HAS_SMC
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33 | d720b93d | bellard | /* support for self modifying code even if the modified instruction is
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34 | d720b93d | bellard | close to the modifying instruction */
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35 | d720b93d | bellard | #define TARGET_HAS_PRECISE_SMC
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36 | d720b93d | bellard | |
37 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
38 | 1fddef4b | bellard | |
39 | 9042c0e2 | ths | #ifdef TARGET_X86_64
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40 | 9042c0e2 | ths | #define ELF_MACHINE EM_X86_64
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41 | 9042c0e2 | ths | #else
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42 | 9042c0e2 | ths | #define ELF_MACHINE EM_386
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43 | 9042c0e2 | ths | #endif
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44 | 9042c0e2 | ths | |
45 | 2c0262af | bellard | #include "cpu-defs.h" |
46 | 2c0262af | bellard | |
47 | 7a0e1f41 | bellard | #include "softfloat.h" |
48 | 7a0e1f41 | bellard | |
49 | 26a16623 | bellard | #if defined(__i386__) && !defined(CONFIG_SOFTMMU) && !defined(__APPLE__)
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50 | 58fe2f10 | bellard | #define USE_CODE_COPY
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51 | 58fe2f10 | bellard | #endif
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52 | 58fe2f10 | bellard | |
53 | 2c0262af | bellard | #define R_EAX 0 |
54 | 2c0262af | bellard | #define R_ECX 1 |
55 | 2c0262af | bellard | #define R_EDX 2 |
56 | 2c0262af | bellard | #define R_EBX 3 |
57 | 2c0262af | bellard | #define R_ESP 4 |
58 | 2c0262af | bellard | #define R_EBP 5 |
59 | 2c0262af | bellard | #define R_ESI 6 |
60 | 2c0262af | bellard | #define R_EDI 7 |
61 | 2c0262af | bellard | |
62 | 2c0262af | bellard | #define R_AL 0 |
63 | 2c0262af | bellard | #define R_CL 1 |
64 | 2c0262af | bellard | #define R_DL 2 |
65 | 2c0262af | bellard | #define R_BL 3 |
66 | 2c0262af | bellard | #define R_AH 4 |
67 | 2c0262af | bellard | #define R_CH 5 |
68 | 2c0262af | bellard | #define R_DH 6 |
69 | 2c0262af | bellard | #define R_BH 7 |
70 | 2c0262af | bellard | |
71 | 2c0262af | bellard | #define R_ES 0 |
72 | 2c0262af | bellard | #define R_CS 1 |
73 | 2c0262af | bellard | #define R_SS 2 |
74 | 2c0262af | bellard | #define R_DS 3 |
75 | 2c0262af | bellard | #define R_FS 4 |
76 | 2c0262af | bellard | #define R_GS 5 |
77 | 2c0262af | bellard | |
78 | 2c0262af | bellard | /* segment descriptor fields */
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79 | 2c0262af | bellard | #define DESC_G_MASK (1 << 23) |
80 | 2c0262af | bellard | #define DESC_B_SHIFT 22 |
81 | 2c0262af | bellard | #define DESC_B_MASK (1 << DESC_B_SHIFT) |
82 | 14ce26e7 | bellard | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
83 | 14ce26e7 | bellard | #define DESC_L_MASK (1 << DESC_L_SHIFT) |
84 | 2c0262af | bellard | #define DESC_AVL_MASK (1 << 20) |
85 | 2c0262af | bellard | #define DESC_P_MASK (1 << 15) |
86 | 2c0262af | bellard | #define DESC_DPL_SHIFT 13 |
87 | 0573fbfc | ths | #define DESC_DPL_MASK (1 << DESC_DPL_SHIFT) |
88 | 2c0262af | bellard | #define DESC_S_MASK (1 << 12) |
89 | 2c0262af | bellard | #define DESC_TYPE_SHIFT 8 |
90 | 2c0262af | bellard | #define DESC_A_MASK (1 << 8) |
91 | 2c0262af | bellard | |
92 | e670b89e | bellard | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
93 | e670b89e | bellard | #define DESC_C_MASK (1 << 10) /* code: conforming */ |
94 | e670b89e | bellard | #define DESC_R_MASK (1 << 9) /* code: readable */ |
95 | 2c0262af | bellard | |
96 | e670b89e | bellard | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
97 | e670b89e | bellard | #define DESC_W_MASK (1 << 9) /* data: writable */ |
98 | e670b89e | bellard | |
99 | e670b89e | bellard | #define DESC_TSS_BUSY_MASK (1 << 9) |
100 | 2c0262af | bellard | |
101 | 2c0262af | bellard | /* eflags masks */
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102 | 2c0262af | bellard | #define CC_C 0x0001 |
103 | 2c0262af | bellard | #define CC_P 0x0004 |
104 | 2c0262af | bellard | #define CC_A 0x0010 |
105 | 2c0262af | bellard | #define CC_Z 0x0040 |
106 | 2c0262af | bellard | #define CC_S 0x0080 |
107 | 2c0262af | bellard | #define CC_O 0x0800 |
108 | 2c0262af | bellard | |
109 | 2c0262af | bellard | #define TF_SHIFT 8 |
110 | 2c0262af | bellard | #define IOPL_SHIFT 12 |
111 | 2c0262af | bellard | #define VM_SHIFT 17 |
112 | 2c0262af | bellard | |
113 | 2c0262af | bellard | #define TF_MASK 0x00000100 |
114 | 2c0262af | bellard | #define IF_MASK 0x00000200 |
115 | 2c0262af | bellard | #define DF_MASK 0x00000400 |
116 | 2c0262af | bellard | #define IOPL_MASK 0x00003000 |
117 | 2c0262af | bellard | #define NT_MASK 0x00004000 |
118 | 2c0262af | bellard | #define RF_MASK 0x00010000 |
119 | 2c0262af | bellard | #define VM_MASK 0x00020000 |
120 | 5fafdf24 | ths | #define AC_MASK 0x00040000 |
121 | 2c0262af | bellard | #define VIF_MASK 0x00080000 |
122 | 2c0262af | bellard | #define VIP_MASK 0x00100000 |
123 | 2c0262af | bellard | #define ID_MASK 0x00200000 |
124 | 2c0262af | bellard | |
125 | aa1f17c1 | ths | /* hidden flags - used internally by qemu to represent additional cpu
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126 | d2ac63e0 | bellard | states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid
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127 | 2c0262af | bellard | using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
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128 | 2c0262af | bellard | with eflags. */
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129 | 2c0262af | bellard | /* current cpl */
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130 | 2c0262af | bellard | #define HF_CPL_SHIFT 0 |
131 | 2c0262af | bellard | /* true if soft mmu is being used */
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132 | 2c0262af | bellard | #define HF_SOFTMMU_SHIFT 2 |
133 | 2c0262af | bellard | /* true if hardware interrupts must be disabled for next instruction */
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134 | 2c0262af | bellard | #define HF_INHIBIT_IRQ_SHIFT 3 |
135 | 2c0262af | bellard | /* 16 or 32 segments */
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136 | 2c0262af | bellard | #define HF_CS32_SHIFT 4 |
137 | 2c0262af | bellard | #define HF_SS32_SHIFT 5 |
138 | dc196a57 | bellard | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
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139 | 2c0262af | bellard | #define HF_ADDSEG_SHIFT 6 |
140 | 65262d57 | bellard | /* copy of CR0.PE (protected mode) */
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141 | 65262d57 | bellard | #define HF_PE_SHIFT 7 |
142 | 65262d57 | bellard | #define HF_TF_SHIFT 8 /* must be same as eflags */ |
143 | 7eee2a50 | bellard | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
144 | 7eee2a50 | bellard | #define HF_EM_SHIFT 10 |
145 | 7eee2a50 | bellard | #define HF_TS_SHIFT 11 |
146 | 65262d57 | bellard | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
147 | 14ce26e7 | bellard | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
148 | 14ce26e7 | bellard | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ |
149 | 664e0f19 | bellard | #define HF_OSFXSR_SHIFT 16 /* CR4.OSFXSR */ |
150 | 65262d57 | bellard | #define HF_VM_SHIFT 17 /* must be same as eflags */ |
151 | d2ac63e0 | bellard | #define HF_HALTED_SHIFT 18 /* CPU halted */ |
152 | 3b21e03e | bellard | #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ |
153 | 0573fbfc | ths | #define HF_GIF_SHIFT 20 /* if set CPU takes interrupts */ |
154 | 0573fbfc | ths | #define HF_HIF_SHIFT 21 /* shadow copy of IF_MASK when in SVM */ |
155 | 2c0262af | bellard | |
156 | 2c0262af | bellard | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) |
157 | 2c0262af | bellard | #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) |
158 | 2c0262af | bellard | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) |
159 | 2c0262af | bellard | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) |
160 | 2c0262af | bellard | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) |
161 | 2c0262af | bellard | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) |
162 | 65262d57 | bellard | #define HF_PE_MASK (1 << HF_PE_SHIFT) |
163 | 58fe2f10 | bellard | #define HF_TF_MASK (1 << HF_TF_SHIFT) |
164 | 7eee2a50 | bellard | #define HF_MP_MASK (1 << HF_MP_SHIFT) |
165 | 7eee2a50 | bellard | #define HF_EM_MASK (1 << HF_EM_SHIFT) |
166 | 7eee2a50 | bellard | #define HF_TS_MASK (1 << HF_TS_SHIFT) |
167 | 14ce26e7 | bellard | #define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
168 | 14ce26e7 | bellard | #define HF_CS64_MASK (1 << HF_CS64_SHIFT) |
169 | 664e0f19 | bellard | #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
170 | d2ac63e0 | bellard | #define HF_HALTED_MASK (1 << HF_HALTED_SHIFT) |
171 | 3b21e03e | bellard | #define HF_SMM_MASK (1 << HF_SMM_SHIFT) |
172 | 0573fbfc | ths | #define HF_GIF_MASK (1 << HF_GIF_SHIFT) |
173 | 0573fbfc | ths | #define HF_HIF_MASK (1 << HF_HIF_SHIFT) |
174 | 2c0262af | bellard | |
175 | 2c0262af | bellard | #define CR0_PE_MASK (1 << 0) |
176 | 7eee2a50 | bellard | #define CR0_MP_MASK (1 << 1) |
177 | 7eee2a50 | bellard | #define CR0_EM_MASK (1 << 2) |
178 | 2c0262af | bellard | #define CR0_TS_MASK (1 << 3) |
179 | 2ee73ac3 | bellard | #define CR0_ET_MASK (1 << 4) |
180 | 7eee2a50 | bellard | #define CR0_NE_MASK (1 << 5) |
181 | 2c0262af | bellard | #define CR0_WP_MASK (1 << 16) |
182 | 2c0262af | bellard | #define CR0_AM_MASK (1 << 18) |
183 | 2c0262af | bellard | #define CR0_PG_MASK (1 << 31) |
184 | 2c0262af | bellard | |
185 | 2c0262af | bellard | #define CR4_VME_MASK (1 << 0) |
186 | 2c0262af | bellard | #define CR4_PVI_MASK (1 << 1) |
187 | 2c0262af | bellard | #define CR4_TSD_MASK (1 << 2) |
188 | 2c0262af | bellard | #define CR4_DE_MASK (1 << 3) |
189 | 2c0262af | bellard | #define CR4_PSE_MASK (1 << 4) |
190 | 64a595f2 | bellard | #define CR4_PAE_MASK (1 << 5) |
191 | 64a595f2 | bellard | #define CR4_PGE_MASK (1 << 7) |
192 | 14ce26e7 | bellard | #define CR4_PCE_MASK (1 << 8) |
193 | 14ce26e7 | bellard | #define CR4_OSFXSR_MASK (1 << 9) |
194 | 14ce26e7 | bellard | #define CR4_OSXMMEXCPT_MASK (1 << 10) |
195 | 2c0262af | bellard | |
196 | 2c0262af | bellard | #define PG_PRESENT_BIT 0 |
197 | 2c0262af | bellard | #define PG_RW_BIT 1 |
198 | 2c0262af | bellard | #define PG_USER_BIT 2 |
199 | 2c0262af | bellard | #define PG_PWT_BIT 3 |
200 | 2c0262af | bellard | #define PG_PCD_BIT 4 |
201 | 2c0262af | bellard | #define PG_ACCESSED_BIT 5 |
202 | 2c0262af | bellard | #define PG_DIRTY_BIT 6 |
203 | 2c0262af | bellard | #define PG_PSE_BIT 7 |
204 | 2c0262af | bellard | #define PG_GLOBAL_BIT 8 |
205 | 5cf38396 | bellard | #define PG_NX_BIT 63 |
206 | 2c0262af | bellard | |
207 | 2c0262af | bellard | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) |
208 | 2c0262af | bellard | #define PG_RW_MASK (1 << PG_RW_BIT) |
209 | 2c0262af | bellard | #define PG_USER_MASK (1 << PG_USER_BIT) |
210 | 2c0262af | bellard | #define PG_PWT_MASK (1 << PG_PWT_BIT) |
211 | 2c0262af | bellard | #define PG_PCD_MASK (1 << PG_PCD_BIT) |
212 | 2c0262af | bellard | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
213 | 2c0262af | bellard | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
214 | 2c0262af | bellard | #define PG_PSE_MASK (1 << PG_PSE_BIT) |
215 | 2c0262af | bellard | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) |
216 | 5cf38396 | bellard | #define PG_NX_MASK (1LL << PG_NX_BIT) |
217 | 2c0262af | bellard | |
218 | 2c0262af | bellard | #define PG_ERROR_W_BIT 1 |
219 | 2c0262af | bellard | |
220 | 2c0262af | bellard | #define PG_ERROR_P_MASK 0x01 |
221 | 2c0262af | bellard | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) |
222 | 2c0262af | bellard | #define PG_ERROR_U_MASK 0x04 |
223 | 2c0262af | bellard | #define PG_ERROR_RSVD_MASK 0x08 |
224 | 5cf38396 | bellard | #define PG_ERROR_I_D_MASK 0x10 |
225 | 2c0262af | bellard | |
226 | 2c0262af | bellard | #define MSR_IA32_APICBASE 0x1b |
227 | 2c0262af | bellard | #define MSR_IA32_APICBASE_BSP (1<<8) |
228 | 2c0262af | bellard | #define MSR_IA32_APICBASE_ENABLE (1<<11) |
229 | 2c0262af | bellard | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
230 | 2c0262af | bellard | |
231 | 2c0262af | bellard | #define MSR_IA32_SYSENTER_CS 0x174 |
232 | 2c0262af | bellard | #define MSR_IA32_SYSENTER_ESP 0x175 |
233 | 2c0262af | bellard | #define MSR_IA32_SYSENTER_EIP 0x176 |
234 | 2c0262af | bellard | |
235 | 8f091a59 | bellard | #define MSR_MCG_CAP 0x179 |
236 | 8f091a59 | bellard | #define MSR_MCG_STATUS 0x17a |
237 | 8f091a59 | bellard | #define MSR_MCG_CTL 0x17b |
238 | 8f091a59 | bellard | |
239 | 8f091a59 | bellard | #define MSR_PAT 0x277 |
240 | 8f091a59 | bellard | |
241 | 14ce26e7 | bellard | #define MSR_EFER 0xc0000080 |
242 | 14ce26e7 | bellard | |
243 | 14ce26e7 | bellard | #define MSR_EFER_SCE (1 << 0) |
244 | 14ce26e7 | bellard | #define MSR_EFER_LME (1 << 8) |
245 | 14ce26e7 | bellard | #define MSR_EFER_LMA (1 << 10) |
246 | 14ce26e7 | bellard | #define MSR_EFER_NXE (1 << 11) |
247 | 14ce26e7 | bellard | #define MSR_EFER_FFXSR (1 << 14) |
248 | 14ce26e7 | bellard | |
249 | 14ce26e7 | bellard | #define MSR_STAR 0xc0000081 |
250 | 14ce26e7 | bellard | #define MSR_LSTAR 0xc0000082 |
251 | 14ce26e7 | bellard | #define MSR_CSTAR 0xc0000083 |
252 | 14ce26e7 | bellard | #define MSR_FMASK 0xc0000084 |
253 | 14ce26e7 | bellard | #define MSR_FSBASE 0xc0000100 |
254 | 14ce26e7 | bellard | #define MSR_GSBASE 0xc0000101 |
255 | 14ce26e7 | bellard | #define MSR_KERNELGSBASE 0xc0000102 |
256 | 14ce26e7 | bellard | |
257 | 0573fbfc | ths | #define MSR_VM_HSAVE_PA 0xc0010117 |
258 | 0573fbfc | ths | |
259 | 14ce26e7 | bellard | /* cpuid_features bits */
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260 | 14ce26e7 | bellard | #define CPUID_FP87 (1 << 0) |
261 | 14ce26e7 | bellard | #define CPUID_VME (1 << 1) |
262 | 14ce26e7 | bellard | #define CPUID_DE (1 << 2) |
263 | 14ce26e7 | bellard | #define CPUID_PSE (1 << 3) |
264 | 14ce26e7 | bellard | #define CPUID_TSC (1 << 4) |
265 | 14ce26e7 | bellard | #define CPUID_MSR (1 << 5) |
266 | 14ce26e7 | bellard | #define CPUID_PAE (1 << 6) |
267 | 14ce26e7 | bellard | #define CPUID_MCE (1 << 7) |
268 | 14ce26e7 | bellard | #define CPUID_CX8 (1 << 8) |
269 | 14ce26e7 | bellard | #define CPUID_APIC (1 << 9) |
270 | 14ce26e7 | bellard | #define CPUID_SEP (1 << 11) /* sysenter/sysexit */ |
271 | 14ce26e7 | bellard | #define CPUID_MTRR (1 << 12) |
272 | 14ce26e7 | bellard | #define CPUID_PGE (1 << 13) |
273 | 14ce26e7 | bellard | #define CPUID_MCA (1 << 14) |
274 | 14ce26e7 | bellard | #define CPUID_CMOV (1 << 15) |
275 | 8f091a59 | bellard | #define CPUID_PAT (1 << 16) |
276 | 8988ae89 | bellard | #define CPUID_PSE36 (1 << 17) |
277 | 8f091a59 | bellard | #define CPUID_CLFLUSH (1 << 19) |
278 | 14ce26e7 | bellard | /* ... */
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279 | 14ce26e7 | bellard | #define CPUID_MMX (1 << 23) |
280 | 14ce26e7 | bellard | #define CPUID_FXSR (1 << 24) |
281 | 14ce26e7 | bellard | #define CPUID_SSE (1 << 25) |
282 | 14ce26e7 | bellard | #define CPUID_SSE2 (1 << 26) |
283 | 14ce26e7 | bellard | |
284 | 465e9838 | bellard | #define CPUID_EXT_SSE3 (1 << 0) |
285 | 9df217a3 | bellard | #define CPUID_EXT_MONITOR (1 << 3) |
286 | 9df217a3 | bellard | #define CPUID_EXT_CX16 (1 << 13) |
287 | 9df217a3 | bellard | |
288 | 9df217a3 | bellard | #define CPUID_EXT2_SYSCALL (1 << 11) |
289 | 9df217a3 | bellard | #define CPUID_EXT2_NX (1 << 20) |
290 | 8d9bfc2b | bellard | #define CPUID_EXT2_FFXSR (1 << 25) |
291 | 9df217a3 | bellard | #define CPUID_EXT2_LM (1 << 29) |
292 | 9df217a3 | bellard | |
293 | 0573fbfc | ths | #define CPUID_EXT3_SVM (1 << 2) |
294 | 0573fbfc | ths | |
295 | 2c0262af | bellard | #define EXCP00_DIVZ 0 |
296 | 2c0262af | bellard | #define EXCP01_SSTP 1 |
297 | 2c0262af | bellard | #define EXCP02_NMI 2 |
298 | 2c0262af | bellard | #define EXCP03_INT3 3 |
299 | 2c0262af | bellard | #define EXCP04_INTO 4 |
300 | 2c0262af | bellard | #define EXCP05_BOUND 5 |
301 | 2c0262af | bellard | #define EXCP06_ILLOP 6 |
302 | 2c0262af | bellard | #define EXCP07_PREX 7 |
303 | 2c0262af | bellard | #define EXCP08_DBLE 8 |
304 | 2c0262af | bellard | #define EXCP09_XERR 9 |
305 | 2c0262af | bellard | #define EXCP0A_TSS 10 |
306 | 2c0262af | bellard | #define EXCP0B_NOSEG 11 |
307 | 2c0262af | bellard | #define EXCP0C_STACK 12 |
308 | 2c0262af | bellard | #define EXCP0D_GPF 13 |
309 | 2c0262af | bellard | #define EXCP0E_PAGE 14 |
310 | 2c0262af | bellard | #define EXCP10_COPR 16 |
311 | 2c0262af | bellard | #define EXCP11_ALGN 17 |
312 | 2c0262af | bellard | #define EXCP12_MCHK 18 |
313 | 2c0262af | bellard | |
314 | 2c0262af | bellard | enum {
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315 | 2c0262af | bellard | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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316 | 2c0262af | bellard | CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
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317 | d36cd60e | bellard | |
318 | d36cd60e | bellard | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
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319 | d36cd60e | bellard | CC_OP_MULW, |
320 | d36cd60e | bellard | CC_OP_MULL, |
321 | 14ce26e7 | bellard | CC_OP_MULQ, |
322 | 2c0262af | bellard | |
323 | 2c0262af | bellard | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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324 | 2c0262af | bellard | CC_OP_ADDW, |
325 | 2c0262af | bellard | CC_OP_ADDL, |
326 | 14ce26e7 | bellard | CC_OP_ADDQ, |
327 | 2c0262af | bellard | |
328 | 2c0262af | bellard | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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329 | 2c0262af | bellard | CC_OP_ADCW, |
330 | 2c0262af | bellard | CC_OP_ADCL, |
331 | 14ce26e7 | bellard | CC_OP_ADCQ, |
332 | 2c0262af | bellard | |
333 | 2c0262af | bellard | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
334 | 2c0262af | bellard | CC_OP_SUBW, |
335 | 2c0262af | bellard | CC_OP_SUBL, |
336 | 14ce26e7 | bellard | CC_OP_SUBQ, |
337 | 2c0262af | bellard | |
338 | 2c0262af | bellard | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
339 | 2c0262af | bellard | CC_OP_SBBW, |
340 | 2c0262af | bellard | CC_OP_SBBL, |
341 | 14ce26e7 | bellard | CC_OP_SBBQ, |
342 | 2c0262af | bellard | |
343 | 2c0262af | bellard | CC_OP_LOGICB, /* modify all flags, CC_DST = res */
|
344 | 2c0262af | bellard | CC_OP_LOGICW, |
345 | 2c0262af | bellard | CC_OP_LOGICL, |
346 | 14ce26e7 | bellard | CC_OP_LOGICQ, |
347 | 2c0262af | bellard | |
348 | 2c0262af | bellard | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
|
349 | 2c0262af | bellard | CC_OP_INCW, |
350 | 2c0262af | bellard | CC_OP_INCL, |
351 | 14ce26e7 | bellard | CC_OP_INCQ, |
352 | 2c0262af | bellard | |
353 | 2c0262af | bellard | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
|
354 | 2c0262af | bellard | CC_OP_DECW, |
355 | 2c0262af | bellard | CC_OP_DECL, |
356 | 14ce26e7 | bellard | CC_OP_DECQ, |
357 | 2c0262af | bellard | |
358 | 6b652794 | bellard | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
|
359 | 2c0262af | bellard | CC_OP_SHLW, |
360 | 2c0262af | bellard | CC_OP_SHLL, |
361 | 14ce26e7 | bellard | CC_OP_SHLQ, |
362 | 2c0262af | bellard | |
363 | 2c0262af | bellard | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
|
364 | 2c0262af | bellard | CC_OP_SARW, |
365 | 2c0262af | bellard | CC_OP_SARL, |
366 | 14ce26e7 | bellard | CC_OP_SARQ, |
367 | 2c0262af | bellard | |
368 | 2c0262af | bellard | CC_OP_NB, |
369 | 2c0262af | bellard | }; |
370 | 2c0262af | bellard | |
371 | 7a0e1f41 | bellard | #ifdef FLOATX80
|
372 | 2c0262af | bellard | #define USE_X86LDOUBLE
|
373 | 2c0262af | bellard | #endif
|
374 | 2c0262af | bellard | |
375 | 2c0262af | bellard | #ifdef USE_X86LDOUBLE
|
376 | 7a0e1f41 | bellard | typedef floatx80 CPU86_LDouble;
|
377 | 2c0262af | bellard | #else
|
378 | 7a0e1f41 | bellard | typedef float64 CPU86_LDouble;
|
379 | 2c0262af | bellard | #endif
|
380 | 2c0262af | bellard | |
381 | 2c0262af | bellard | typedef struct SegmentCache { |
382 | 2c0262af | bellard | uint32_t selector; |
383 | 14ce26e7 | bellard | target_ulong base; |
384 | 2c0262af | bellard | uint32_t limit; |
385 | 2c0262af | bellard | uint32_t flags; |
386 | 2c0262af | bellard | } SegmentCache; |
387 | 2c0262af | bellard | |
388 | 826461bb | bellard | typedef union { |
389 | 664e0f19 | bellard | uint8_t _b[16];
|
390 | 664e0f19 | bellard | uint16_t _w[8];
|
391 | 664e0f19 | bellard | uint32_t _l[4];
|
392 | 664e0f19 | bellard | uint64_t _q[2];
|
393 | 7a0e1f41 | bellard | float32 _s[4];
|
394 | 7a0e1f41 | bellard | float64 _d[2];
|
395 | 14ce26e7 | bellard | } XMMReg; |
396 | 14ce26e7 | bellard | |
397 | 826461bb | bellard | typedef union { |
398 | 826461bb | bellard | uint8_t _b[8];
|
399 | 826461bb | bellard | uint16_t _w[2];
|
400 | 826461bb | bellard | uint32_t _l[1];
|
401 | 826461bb | bellard | uint64_t q; |
402 | 826461bb | bellard | } MMXReg; |
403 | 826461bb | bellard | |
404 | 826461bb | bellard | #ifdef WORDS_BIGENDIAN
|
405 | 826461bb | bellard | #define XMM_B(n) _b[15 - (n)] |
406 | 826461bb | bellard | #define XMM_W(n) _w[7 - (n)] |
407 | 826461bb | bellard | #define XMM_L(n) _l[3 - (n)] |
408 | 664e0f19 | bellard | #define XMM_S(n) _s[3 - (n)] |
409 | 826461bb | bellard | #define XMM_Q(n) _q[1 - (n)] |
410 | 664e0f19 | bellard | #define XMM_D(n) _d[1 - (n)] |
411 | 826461bb | bellard | |
412 | 826461bb | bellard | #define MMX_B(n) _b[7 - (n)] |
413 | 826461bb | bellard | #define MMX_W(n) _w[3 - (n)] |
414 | 826461bb | bellard | #define MMX_L(n) _l[1 - (n)] |
415 | 826461bb | bellard | #else
|
416 | 826461bb | bellard | #define XMM_B(n) _b[n]
|
417 | 826461bb | bellard | #define XMM_W(n) _w[n]
|
418 | 826461bb | bellard | #define XMM_L(n) _l[n]
|
419 | 664e0f19 | bellard | #define XMM_S(n) _s[n]
|
420 | 826461bb | bellard | #define XMM_Q(n) _q[n]
|
421 | 664e0f19 | bellard | #define XMM_D(n) _d[n]
|
422 | 826461bb | bellard | |
423 | 826461bb | bellard | #define MMX_B(n) _b[n]
|
424 | 826461bb | bellard | #define MMX_W(n) _w[n]
|
425 | 826461bb | bellard | #define MMX_L(n) _l[n]
|
426 | 826461bb | bellard | #endif
|
427 | 664e0f19 | bellard | #define MMX_Q(n) q
|
428 | 826461bb | bellard | |
429 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
430 | 14ce26e7 | bellard | #define CPU_NB_REGS 16 |
431 | 14ce26e7 | bellard | #else
|
432 | 14ce26e7 | bellard | #define CPU_NB_REGS 8 |
433 | 14ce26e7 | bellard | #endif
|
434 | 14ce26e7 | bellard | |
435 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 2 |
436 | 6ebbf390 | j_mayer | |
437 | 2c0262af | bellard | typedef struct CPUX86State { |
438 | 14ce26e7 | bellard | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
439 | 14ce26e7 | bellard | /* temporaries if we cannot store them in host registers */
|
440 | 14ce26e7 | bellard | target_ulong t0, t1, t2; |
441 | 14ce26e7 | bellard | #endif
|
442 | 14ce26e7 | bellard | |
443 | 2c0262af | bellard | /* standard registers */
|
444 | 14ce26e7 | bellard | target_ulong regs[CPU_NB_REGS]; |
445 | 14ce26e7 | bellard | target_ulong eip; |
446 | 14ce26e7 | bellard | target_ulong eflags; /* eflags register. During CPU emulation, CC
|
447 | 2c0262af | bellard | flags and DF are set to zero because they are
|
448 | 2c0262af | bellard | stored elsewhere */
|
449 | 2c0262af | bellard | |
450 | 2c0262af | bellard | /* emulator internal eflags handling */
|
451 | 14ce26e7 | bellard | target_ulong cc_src; |
452 | 14ce26e7 | bellard | target_ulong cc_dst; |
453 | 2c0262af | bellard | uint32_t cc_op; |
454 | 2c0262af | bellard | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
|
455 | 2c0262af | bellard | uint32_t hflags; /* hidden flags, see HF_xxx constants */
|
456 | 2c0262af | bellard | |
457 | 9df217a3 | bellard | /* segments */
|
458 | 9df217a3 | bellard | SegmentCache segs[6]; /* selector values */ |
459 | 9df217a3 | bellard | SegmentCache ldt; |
460 | 9df217a3 | bellard | SegmentCache tr; |
461 | 9df217a3 | bellard | SegmentCache gdt; /* only base and limit are used */
|
462 | 9df217a3 | bellard | SegmentCache idt; /* only base and limit are used */
|
463 | 9df217a3 | bellard | |
464 | 9df217a3 | bellard | target_ulong cr[5]; /* NOTE: cr1 is unused */ |
465 | 9df217a3 | bellard | uint32_t a20_mask; |
466 | 9df217a3 | bellard | |
467 | 2c0262af | bellard | /* FPU state */
|
468 | 2c0262af | bellard | unsigned int fpstt; /* top of stack index */ |
469 | 2c0262af | bellard | unsigned int fpus; |
470 | 2c0262af | bellard | unsigned int fpuc; |
471 | 2c0262af | bellard | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
472 | 664e0f19 | bellard | union {
|
473 | 664e0f19 | bellard | #ifdef USE_X86LDOUBLE
|
474 | 664e0f19 | bellard | CPU86_LDouble d __attribute__((aligned(16)));
|
475 | 664e0f19 | bellard | #else
|
476 | 664e0f19 | bellard | CPU86_LDouble d; |
477 | 664e0f19 | bellard | #endif
|
478 | 664e0f19 | bellard | MMXReg mmx; |
479 | 664e0f19 | bellard | } fpregs[8];
|
480 | 2c0262af | bellard | |
481 | 2c0262af | bellard | /* emulator internal variables */
|
482 | 7a0e1f41 | bellard | float_status fp_status; |
483 | 2c0262af | bellard | CPU86_LDouble ft0; |
484 | 2c0262af | bellard | union {
|
485 | 2c0262af | bellard | float f;
|
486 | 2c0262af | bellard | double d;
|
487 | 2c0262af | bellard | int i32;
|
488 | 2c0262af | bellard | int64_t i64; |
489 | 2c0262af | bellard | } fp_convert; |
490 | 3b46e624 | ths | |
491 | 7a0e1f41 | bellard | float_status sse_status; |
492 | 664e0f19 | bellard | uint32_t mxcsr; |
493 | 14ce26e7 | bellard | XMMReg xmm_regs[CPU_NB_REGS]; |
494 | 14ce26e7 | bellard | XMMReg xmm_t0; |
495 | 664e0f19 | bellard | MMXReg mmx_t0; |
496 | 14ce26e7 | bellard | |
497 | 2c0262af | bellard | /* sysenter registers */
|
498 | 2c0262af | bellard | uint32_t sysenter_cs; |
499 | 2c0262af | bellard | uint32_t sysenter_esp; |
500 | 2c0262af | bellard | uint32_t sysenter_eip; |
501 | 8d9bfc2b | bellard | uint64_t efer; |
502 | 8d9bfc2b | bellard | uint64_t star; |
503 | 0573fbfc | ths | |
504 | 0573fbfc | ths | target_phys_addr_t vm_hsave; |
505 | 0573fbfc | ths | target_phys_addr_t vm_vmcb; |
506 | 0573fbfc | ths | uint64_t intercept; |
507 | 0573fbfc | ths | uint16_t intercept_cr_read; |
508 | 0573fbfc | ths | uint16_t intercept_cr_write; |
509 | 0573fbfc | ths | uint16_t intercept_dr_read; |
510 | 0573fbfc | ths | uint16_t intercept_dr_write; |
511 | 0573fbfc | ths | uint32_t intercept_exceptions; |
512 | 0573fbfc | ths | |
513 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
514 | 14ce26e7 | bellard | target_ulong lstar; |
515 | 14ce26e7 | bellard | target_ulong cstar; |
516 | 14ce26e7 | bellard | target_ulong fmask; |
517 | 14ce26e7 | bellard | target_ulong kernelgsbase; |
518 | 14ce26e7 | bellard | #endif
|
519 | 58fe2f10 | bellard | |
520 | 8f091a59 | bellard | uint64_t pat; |
521 | 8f091a59 | bellard | |
522 | 58fe2f10 | bellard | /* temporary data for USE_CODE_COPY mode */
|
523 | 7eee2a50 | bellard | #ifdef USE_CODE_COPY
|
524 | 58fe2f10 | bellard | uint32_t tmp0; |
525 | 58fe2f10 | bellard | uint32_t saved_esp; |
526 | 7eee2a50 | bellard | int native_fp_regs; /* if true, the FPU state is in the native CPU regs */ |
527 | 7eee2a50 | bellard | #endif
|
528 | 3b46e624 | ths | |
529 | 2c0262af | bellard | /* exception/interrupt handling */
|
530 | 2c0262af | bellard | jmp_buf jmp_env; |
531 | 2c0262af | bellard | int exception_index;
|
532 | 2c0262af | bellard | int error_code;
|
533 | 2c0262af | bellard | int exception_is_int;
|
534 | 826461bb | bellard | target_ulong exception_next_eip; |
535 | 14ce26e7 | bellard | target_ulong dr[8]; /* debug registers */ |
536 | 3b21e03e | bellard | uint32_t smbase; |
537 | 5fafdf24 | ths | int interrupt_request;
|
538 | 2c0262af | bellard | int user_mode_only; /* user mode only simulation */ |
539 | 678dde13 | ths | int old_exception; /* exception in flight */ |
540 | 2c0262af | bellard | |
541 | a316d335 | bellard | CPU_COMMON |
542 | 2c0262af | bellard | |
543 | 14ce26e7 | bellard | /* processor features (e.g. for CPUID insn) */
|
544 | 8d9bfc2b | bellard | uint32_t cpuid_level; |
545 | 14ce26e7 | bellard | uint32_t cpuid_vendor1; |
546 | 14ce26e7 | bellard | uint32_t cpuid_vendor2; |
547 | 14ce26e7 | bellard | uint32_t cpuid_vendor3; |
548 | 14ce26e7 | bellard | uint32_t cpuid_version; |
549 | 14ce26e7 | bellard | uint32_t cpuid_features; |
550 | 9df217a3 | bellard | uint32_t cpuid_ext_features; |
551 | 8d9bfc2b | bellard | uint32_t cpuid_xlevel; |
552 | 8d9bfc2b | bellard | uint32_t cpuid_model[12];
|
553 | 8d9bfc2b | bellard | uint32_t cpuid_ext2_features; |
554 | 0573fbfc | ths | uint32_t cpuid_ext3_features; |
555 | eae7629b | ths | uint32_t cpuid_apic_id; |
556 | 3b46e624 | ths | |
557 | 9df217a3 | bellard | #ifdef USE_KQEMU
|
558 | 9df217a3 | bellard | int kqemu_enabled;
|
559 | f1c85677 | bellard | int last_io_time;
|
560 | 9df217a3 | bellard | #endif
|
561 | 14ce26e7 | bellard | /* in order to simplify APIC support, we leave this pointer to the
|
562 | 14ce26e7 | bellard | user */
|
563 | 14ce26e7 | bellard | struct APICState *apic_state;
|
564 | 2c0262af | bellard | } CPUX86State; |
565 | 2c0262af | bellard | |
566 | 2c0262af | bellard | CPUX86State *cpu_x86_init(void);
|
567 | 2c0262af | bellard | int cpu_x86_exec(CPUX86State *s);
|
568 | 2c0262af | bellard | void cpu_x86_close(CPUX86State *s);
|
569 | d720b93d | bellard | int cpu_get_pic_interrupt(CPUX86State *s);
|
570 | 2ee73ac3 | bellard | /* MSDOS compatibility mode FPU exception support */
|
571 | 2ee73ac3 | bellard | void cpu_set_ferr(CPUX86State *s);
|
572 | 2c0262af | bellard | |
573 | 2c0262af | bellard | /* this function must always be used to load data in the segment
|
574 | 2c0262af | bellard | cache: it synchronizes the hflags with the segment cache values */
|
575 | 5fafdf24 | ths | static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
576 | 2c0262af | bellard | int seg_reg, unsigned int selector, |
577 | 8988ae89 | bellard | target_ulong base, |
578 | 5fafdf24 | ths | unsigned int limit, |
579 | 2c0262af | bellard | unsigned int flags) |
580 | 2c0262af | bellard | { |
581 | 2c0262af | bellard | SegmentCache *sc; |
582 | 2c0262af | bellard | unsigned int new_hflags; |
583 | 3b46e624 | ths | |
584 | 2c0262af | bellard | sc = &env->segs[seg_reg]; |
585 | 2c0262af | bellard | sc->selector = selector; |
586 | 2c0262af | bellard | sc->base = base; |
587 | 2c0262af | bellard | sc->limit = limit; |
588 | 2c0262af | bellard | sc->flags = flags; |
589 | 2c0262af | bellard | |
590 | 2c0262af | bellard | /* update the hidden flags */
|
591 | 14ce26e7 | bellard | { |
592 | 14ce26e7 | bellard | if (seg_reg == R_CS) {
|
593 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
594 | 14ce26e7 | bellard | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
|
595 | 14ce26e7 | bellard | /* long mode */
|
596 | 14ce26e7 | bellard | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; |
597 | 14ce26e7 | bellard | env->hflags &= ~(HF_ADDSEG_MASK); |
598 | 5fafdf24 | ths | } else
|
599 | 14ce26e7 | bellard | #endif
|
600 | 14ce26e7 | bellard | { |
601 | 14ce26e7 | bellard | /* legacy / compatibility case */
|
602 | 14ce26e7 | bellard | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) |
603 | 14ce26e7 | bellard | >> (DESC_B_SHIFT - HF_CS32_SHIFT); |
604 | 14ce26e7 | bellard | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | |
605 | 14ce26e7 | bellard | new_hflags; |
606 | 14ce26e7 | bellard | } |
607 | 14ce26e7 | bellard | } |
608 | 14ce26e7 | bellard | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) |
609 | 14ce26e7 | bellard | >> (DESC_B_SHIFT - HF_SS32_SHIFT); |
610 | 14ce26e7 | bellard | if (env->hflags & HF_CS64_MASK) {
|
611 | 14ce26e7 | bellard | /* zero base assumed for DS, ES and SS in long mode */
|
612 | 5fafdf24 | ths | } else if (!(env->cr[0] & CR0_PE_MASK) || |
613 | 735a8fd3 | bellard | (env->eflags & VM_MASK) || |
614 | 735a8fd3 | bellard | !(env->hflags & HF_CS32_MASK)) { |
615 | 14ce26e7 | bellard | /* XXX: try to avoid this test. The problem comes from the
|
616 | 14ce26e7 | bellard | fact that is real mode or vm86 mode we only modify the
|
617 | 14ce26e7 | bellard | 'base' and 'selector' fields of the segment cache to go
|
618 | 14ce26e7 | bellard | faster. A solution may be to force addseg to one in
|
619 | 14ce26e7 | bellard | translate-i386.c. */
|
620 | 14ce26e7 | bellard | new_hflags |= HF_ADDSEG_MASK; |
621 | 14ce26e7 | bellard | } else {
|
622 | 5fafdf24 | ths | new_hflags |= ((env->segs[R_DS].base | |
623 | 735a8fd3 | bellard | env->segs[R_ES].base | |
624 | 5fafdf24 | ths | env->segs[R_SS].base) != 0) <<
|
625 | 14ce26e7 | bellard | HF_ADDSEG_SHIFT; |
626 | 14ce26e7 | bellard | } |
627 | 5fafdf24 | ths | env->hflags = (env->hflags & |
628 | 14ce26e7 | bellard | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
629 | 2c0262af | bellard | } |
630 | 2c0262af | bellard | } |
631 | 2c0262af | bellard | |
632 | 2c0262af | bellard | /* wrapper, just in case memory mappings must be changed */
|
633 | 2c0262af | bellard | static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl) |
634 | 2c0262af | bellard | { |
635 | 2c0262af | bellard | #if HF_CPL_MASK == 3 |
636 | 2c0262af | bellard | s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl; |
637 | 2c0262af | bellard | #else
|
638 | 2c0262af | bellard | #error HF_CPL_MASK is hardcoded
|
639 | 2c0262af | bellard | #endif
|
640 | 2c0262af | bellard | } |
641 | 2c0262af | bellard | |
642 | 1f1af9fd | bellard | /* used for debug or cpu save/restore */
|
643 | 1f1af9fd | bellard | void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
|
644 | 1f1af9fd | bellard | CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper); |
645 | 1f1af9fd | bellard | |
646 | 2c0262af | bellard | /* the following helpers are only usable in user mode simulation as
|
647 | 2c0262af | bellard | they can trigger unexpected exceptions */
|
648 | 2c0262af | bellard | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); |
649 | 2c0262af | bellard | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32); |
650 | 2c0262af | bellard | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32); |
651 | 2c0262af | bellard | |
652 | 2c0262af | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
|
653 | 2c0262af | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
|
654 | 2c0262af | bellard | is returned if the signal was handled by the virtual CPU. */
|
655 | 5fafdf24 | ths | int cpu_x86_signal_handler(int host_signum, void *pinfo, |
656 | 2c0262af | bellard | void *puc);
|
657 | 461c0471 | bellard | void cpu_x86_set_a20(CPUX86State *env, int a20_state); |
658 | 2c0262af | bellard | |
659 | 28ab0e2e | bellard | uint64_t cpu_get_tsc(CPUX86State *env); |
660 | 28ab0e2e | bellard | |
661 | 14ce26e7 | bellard | void cpu_set_apic_base(CPUX86State *env, uint64_t val);
|
662 | 14ce26e7 | bellard | uint64_t cpu_get_apic_base(CPUX86State *env); |
663 | 9230e66e | bellard | void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
|
664 | 9230e66e | bellard | #ifndef NO_CPU_IO_DEFS
|
665 | 9230e66e | bellard | uint8_t cpu_get_apic_tpr(CPUX86State *env); |
666 | 9230e66e | bellard | #endif
|
667 | 3b21e03e | bellard | void cpu_smm_update(CPUX86State *env);
|
668 | 14ce26e7 | bellard | |
669 | 64a595f2 | bellard | /* will be suppressed */
|
670 | 64a595f2 | bellard | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
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671 | 64a595f2 | bellard | |
672 | 2c0262af | bellard | /* used to debug */
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673 | 2c0262af | bellard | #define X86_DUMP_FPU 0x0001 /* dump FPU state too */ |
674 | 2c0262af | bellard | #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */ |
675 | 2c0262af | bellard | |
676 | f1c85677 | bellard | #ifdef USE_KQEMU
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677 | f1c85677 | bellard | static inline int cpu_get_time_fast(void) |
678 | f1c85677 | bellard | { |
679 | f1c85677 | bellard | int low, high;
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680 | f1c85677 | bellard | asm volatile("rdtsc" : "=a" (low), "=d" (high)); |
681 | f1c85677 | bellard | return low;
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682 | f1c85677 | bellard | } |
683 | f1c85677 | bellard | #endif
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684 | f1c85677 | bellard | |
685 | 2c0262af | bellard | #define TARGET_PAGE_BITS 12 |
686 | 9467d44c | ths | |
687 | 9467d44c | ths | #define CPUState CPUX86State
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688 | 9467d44c | ths | #define cpu_init cpu_x86_init
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689 | 9467d44c | ths | #define cpu_exec cpu_x86_exec
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690 | 9467d44c | ths | #define cpu_gen_code cpu_x86_gen_code
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691 | 9467d44c | ths | #define cpu_signal_handler cpu_x86_signal_handler
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692 | 9467d44c | ths | |
693 | 6ebbf390 | j_mayer | /* MMU modes definitions */
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694 | 6ebbf390 | j_mayer | #define MMU_MODE0_SUFFIX _kernel
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695 | 6ebbf390 | j_mayer | #define MMU_MODE1_SUFFIX _user
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696 | 6ebbf390 | j_mayer | #define MMU_USER_IDX 1 |
697 | 6ebbf390 | j_mayer | static inline int cpu_mmu_index (CPUState *env) |
698 | 6ebbf390 | j_mayer | { |
699 | 6ebbf390 | j_mayer | return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0; |
700 | 6ebbf390 | j_mayer | } |
701 | 6ebbf390 | j_mayer | |
702 | 2c0262af | bellard | #include "cpu-all.h" |
703 | 2c0262af | bellard | |
704 | 0573fbfc | ths | #include "svm.h" |
705 | 0573fbfc | ths | |
706 | 2c0262af | bellard | #endif /* CPU_I386_H */ |