Revision 802670e6 hw/ppc405.h

b/hw/ppc405.h
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ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
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                                uint32_t flags);
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/* PowerPC 4xx peripheral local bus arbitrer */
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void ppc4xx_plb_init (CPUState *env);
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/* PLB to OPB bridge */
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void ppc4xx_pob_init (CPUState *env);
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/* OPB arbitrer */
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void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
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                       target_phys_addr_t offset);
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/* Peripheral controller */
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void ppc405_ebc_init (CPUState *env);
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/* DMA controller */
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void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]);
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/* GPIO */
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void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
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                       target_phys_addr_t offset);
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/* Serial ports */
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void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
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                         target_phys_addr_t offset, qemu_irq irq,
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                         CharDriverState *chr);
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/* On Chip Memory */
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void ppc405_ocm_init (CPUState *env);
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/* I2C controller */
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void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
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                      target_phys_addr_t offset, qemu_irq irq);
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/* General purpose timers */
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void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
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                      target_phys_addr_t offset, qemu_irq irq[5]);
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/* Memory access layer */
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void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]);
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/* PowerPC 405 microcontrollers */
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CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
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                         target_phys_addr_t ram_sizes[4],
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                         uint32_t sysclk, qemu_irq **picp,

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